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[Blackfin] arch: add support for BF523/BF524/BF526
[deliverable/linux.git] / arch / blackfin / kernel / bfin_gpio.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/bfin_gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
d2b11a46 10 * Copyright 2007 Analog Devices Inc.
1394f032
BW		 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
d2b11a46 31* Number BF537/6/4 BF561 BF533/2/1 BF549/8/4/2
1394f032 32*
d2b11a46 33* GPIO_0 PF0 PF0 PF0 PA0...PJ13
1394f032
BW		 34* GPIO_1 PF1 PF1 PF1
35* GPIO_2 PF2 PF2 PF2
36* GPIO_3 PF3 PF3 PF3
37* GPIO_4 PF4 PF4 PF4
38* GPIO_5 PF5 PF5 PF5
39* GPIO_6 PF6 PF6 PF6
40* GPIO_7 PF7 PF7 PF7
41* GPIO_8 PF8 PF8 PF8
42* GPIO_9 PF9 PF9 PF9
43* GPIO_10 PF10 PF10 PF10
44* GPIO_11 PF11 PF11 PF11
45* GPIO_12 PF12 PF12 PF12
46* GPIO_13 PF13 PF13 PF13
47* GPIO_14 PF14 PF14 PF14
48* GPIO_15 PF15 PF15 PF15
49* GPIO_16 PG0 PF16
50* GPIO_17 PG1 PF17
51* GPIO_18 PG2 PF18
52* GPIO_19 PG3 PF19
53* GPIO_20 PG4 PF20
54* GPIO_21 PG5 PF21
55* GPIO_22 PG6 PF22
56* GPIO_23 PG7 PF23
57* GPIO_24 PG8 PF24
58* GPIO_25 PG9 PF25
59* GPIO_26 PG10 PF26
60* GPIO_27 PG11 PF27
61* GPIO_28 PG12 PF28
62* GPIO_29 PG13 PF29
63* GPIO_30 PG14 PF30
64* GPIO_31 PG15 PF31
65* GPIO_32 PH0 PF32
66* GPIO_33 PH1 PF33
67* GPIO_34 PH2 PF34
68* GPIO_35 PH3 PF35
69* GPIO_36 PH4 PF36
70* GPIO_37 PH5 PF37
71* GPIO_38 PH6 PF38
72* GPIO_39 PH7 PF39
73* GPIO_40 PH8 PF40
74* GPIO_41 PH9 PF41
75* GPIO_42 PH10 PF42
76* GPIO_43 PH11 PF43
77* GPIO_44 PH12 PF44
78* GPIO_45 PH13 PF45
79* GPIO_46 PH14 PF46
80* GPIO_47 PH15 PF47
81*/
82
168f1212 83#include <linux/delay.h>
1394f032
BW		 84#include <linux/module.h>
85#include <linux/err.h>
1545a111 86#include <linux/proc_fs.h>
1394f032
BW		 87#include <asm/blackfin.h>
88#include <asm/gpio.h>
c58c2140 89#include <asm/portmux.h>
1394f032
BW		 90#include <linux/irq.h>
91
2b39331a
MH		 92#if ANOMALY_05000311 || ANOMALY_05000323
93enum {
94 AWA_data = SYSCR,
95 AWA_data_clear = SYSCR,
96 AWA_data_set = SYSCR,
97 AWA_toggle = SYSCR,
98 AWA_maska = UART_SCR,
99 AWA_maska_clear = UART_SCR,
100 AWA_maska_set = UART_SCR,
101 AWA_maska_toggle = UART_SCR,
102 AWA_maskb = UART_GCTL,
103 AWA_maskb_clear = UART_GCTL,
104 AWA_maskb_set = UART_GCTL,
105 AWA_maskb_toggle = UART_GCTL,
106 AWA_dir = SPORT1_STAT,
107 AWA_polar = SPORT1_STAT,
108 AWA_edge = SPORT1_STAT,
109 AWA_both = SPORT1_STAT,
110#if ANOMALY_05000311
111 AWA_inen = TIMER_ENABLE,
112#elif ANOMALY_05000323
113 AWA_inen = DMA1_1_CONFIG,
114#endif
115};
116 /* Anomaly Workaround */
117#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
118#else
119#define AWA_DUMMY_READ(...) do { } while (0)
120#endif
121
1394f032
BW		 122#ifdef BF533_FAMILY
123static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
124 (struct gpio_port_t *) FIO_FLAG_D,
125};
126#endif
127
59003145 128#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
1394f032
BW		 129static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
130 (struct gpio_port_t *) PORTFIO,
131 (struct gpio_port_t *) PORTGIO,
132 (struct gpio_port_t *) PORTHIO,
133};
134
135static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
136 (unsigned short *) PORTF_FER,
137 (unsigned short *) PORTG_FER,
138 (unsigned short *) PORTH_FER,
139};
140
141#endif
142
59003145
MH		 143#ifdef BF527_FAMILY
144static unsigned short *port_mux[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
145 (unsigned short *) PORTF_MUX,
146 (unsigned short *) PORTG_MUX,
147 (unsigned short *) PORTH_MUX,
148};
149
150static const
151u8 pmux_offset[][16] =
152 {{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
153 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
154 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
155 };
156#endif
157
1394f032
BW		 158#ifdef BF561_FAMILY
159static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
160 (struct gpio_port_t *) FIO0_FLAG_D,
161 (struct gpio_port_t *) FIO1_FLAG_D,
162 (struct gpio_port_t *) FIO2_FLAG_D,
163};
164#endif
165
d2b11a46
MH		 166#ifdef BF548_FAMILY
167static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
168 (struct gpio_port_t *)PORTA_FER,
169 (struct gpio_port_t *)PORTB_FER,
170 (struct gpio_port_t *)PORTC_FER,
171 (struct gpio_port_t *)PORTD_FER,
172 (struct gpio_port_t *)PORTE_FER,
173 (struct gpio_port_t *)PORTF_FER,
174 (struct gpio_port_t *)PORTG_FER,
175 (struct gpio_port_t *)PORTH_FER,
176 (struct gpio_port_t *)PORTI_FER,
177 (struct gpio_port_t *)PORTJ_FER,
178};
179#endif
180
c58c2140
MH		 181static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
182static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS + 16)];
c58c2140 183
8c613623
MH		 184#define MAX_RESOURCES 256
185#define RESOURCE_LABEL_SIZE 16
186
187struct str_ident {
188 char name[RESOURCE_LABEL_SIZE];
189} *str_ident;
190
1394f032
BW		 191
192#ifdef CONFIG_PM
193static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
194static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
195static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
196
197#ifdef BF533_FAMILY
198static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB};
199#endif
200
201#ifdef BF537_FAMILY
202static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
203#endif
204
59003145
MH		 205#ifdef BF527_FAMILY
206static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
207#endif
208
1394f032
BW		 209#ifdef BF561_FAMILY
210static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
211#endif
212
213#endif /* CONFIG_PM */
214
d2b11a46
MH		 215#if defined(BF548_FAMILY)
216inline int check_gpio(unsigned short gpio)
217{
218 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
219 || gpio == GPIO_PH14 || gpio == GPIO_PH15
220 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
221 || gpio > MAX_BLACKFIN_GPIOS)
222 return -EINVAL;
223 return 0;
224}
225#else
1394f032
BW		 226inline int check_gpio(unsigned short gpio)
227{
e7613aab 228 if (gpio >= MAX_BLACKFIN_GPIOS)
1394f032
BW		 229 return -EINVAL;
230 return 0;
231}
d2b11a46 232#endif
1394f032 233
c58c2140
MH		 234static void set_label(unsigned short ident, const char *label)
235{
236
237 if (label && str_ident) {
8c613623 238 strncpy(str_ident[ident].name, label,
c58c2140 239 RESOURCE_LABEL_SIZE);
8c613623 240 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH		 241 }
242}
243
244static char *get_label(unsigned short ident)
245{
246 if (!str_ident)
247 return "UNKNOWN";
248
8c613623 249 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH		 250}
251
252static int cmp_label(unsigned short ident, const char *label)
253{
254 if (label && str_ident)
8c613623 255 return strncmp(str_ident[ident].name,
c58c2140
MH		 256 label, strlen(label));
257 else
258 return -EINVAL;
259}
260
59003145 261#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
a161bb05 262static void port_setup(unsigned short gpio, unsigned short usage)
1394f032 263{
cda6a20b 264 if (!check_gpio(gpio)) {
d2b11a46 265 if (usage == GPIO_USAGE)
cda6a20b 266 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
d2b11a46 267 else
cda6a20b
MH		 268 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
269 SSYNC();
270 }
1394f032 271}
d2b11a46
MH		 272#elif defined(BF548_FAMILY)
273static void port_setup(unsigned short gpio, unsigned short usage)
274{
275 if (usage == GPIO_USAGE)
276 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
277 else
278 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
279 SSYNC();
280}
1394f032
BW		 281#else
282# define port_setup(...) do { } while (0)
283#endif
284
c58c2140 285#ifdef BF537_FAMILY
8c613623
MH		 286static struct {
287 unsigned short res;
288 unsigned short offset;
289} port_mux_lut[] = {
290 {.res = P_PPI0_D13, .offset = 11},
291 {.res = P_PPI0_D14, .offset = 11},
292 {.res = P_PPI0_D15, .offset = 11},
293 {.res = P_SPORT1_TFS, .offset = 11},
294 {.res = P_SPORT1_TSCLK, .offset = 11},
295 {.res = P_SPORT1_DTPRI, .offset = 11},
296 {.res = P_PPI0_D10, .offset = 10},
297 {.res = P_PPI0_D11, .offset = 10},
298 {.res = P_PPI0_D12, .offset = 10},
299 {.res = P_SPORT1_RSCLK, .offset = 10},
300 {.res = P_SPORT1_RFS, .offset = 10},
301 {.res = P_SPORT1_DRPRI, .offset = 10},
302 {.res = P_PPI0_D8, .offset = 9},
303 {.res = P_PPI0_D9, .offset = 9},
304 {.res = P_SPORT1_DRSEC, .offset = 9},
305 {.res = P_SPORT1_DTSEC, .offset = 9},
306 {.res = P_TMR2, .offset = 8},
307 {.res = P_PPI0_FS3, .offset = 8},
308 {.res = P_TMR3, .offset = 7},
309 {.res = P_SPI0_SSEL4, .offset = 7},
310 {.res = P_TMR4, .offset = 6},
311 {.res = P_SPI0_SSEL5, .offset = 6},
312 {.res = P_TMR5, .offset = 5},
313 {.res = P_SPI0_SSEL6, .offset = 5},
314 {.res = P_UART1_RX, .offset = 4},
315 {.res = P_UART1_TX, .offset = 4},
316 {.res = P_TMR6, .offset = 4},
317 {.res = P_TMR7, .offset = 4},
318 {.res = P_UART0_RX, .offset = 3},
319 {.res = P_UART0_TX, .offset = 3},
320 {.res = P_DMAR0, .offset = 3},
321 {.res = P_DMAR1, .offset = 3},
322 {.res = P_SPORT0_DTSEC, .offset = 1},
323 {.res = P_SPORT0_DRSEC, .offset = 1},
324 {.res = P_CAN0_RX, .offset = 1},
325 {.res = P_CAN0_TX, .offset = 1},
326 {.res = P_SPI0_SSEL7, .offset = 1},
327 {.res = P_SPORT0_TFS, .offset = 0},
328 {.res = P_SPORT0_DTPRI, .offset = 0},
329 {.res = P_SPI0_SSEL2, .offset = 0},
330 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH		 331};
332
333static void portmux_setup(unsigned short per, unsigned short function)
334{
8c613623 335 u16 y, offset, muxreg;
c58c2140 336
8c613623
MH		 337 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
338 if (port_mux_lut[y].res == per) {
c58c2140
MH		 339
340 /* SET PORTMUX REG */
341
8c613623 342 offset = port_mux_lut[y].offset;
c58c2140
MH		 343 muxreg = bfin_read_PORT_MUX();
344
345 if (offset != 1) {
346 muxreg &= ~(1 << offset);
347 } else {
348 muxreg &= ~(3 << 1);
349 }
350
351 muxreg |= (function << offset);
352 bfin_write_PORT_MUX(muxreg);
353 }
354 }
355}
d2b11a46
MH		 356#elif defined(BF548_FAMILY)
357inline void portmux_setup(unsigned short portno, unsigned short function)
358{
359 u32 pmux;
360
361 pmux = gpio_array[gpio_bank(portno)]->port_mux;
362
363 pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
364 pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
365
366 gpio_array[gpio_bank(portno)]->port_mux = pmux;
367}
368
369inline u16 get_portmux(unsigned short portno)
370{
371 u32 pmux;
c58c2140 372
d2b11a46
MH		 373 pmux = gpio_array[gpio_bank(portno)]->port_mux;
374
375 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
376}
59003145
MH		 377#elif defined(BF527_FAMILY)
378inline void portmux_setup(unsigned short portno, unsigned short function)
379{
380 u16 pmux, ident = P_IDENT(portno);
381 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
382
383 pmux = *port_mux[gpio_bank(ident)];
384 pmux &= ~(3 << offset);
385 pmux |= (function & 3) << offset;
386 *port_mux[gpio_bank(ident)] = pmux;
387 SSYNC();
388}
c58c2140
MH		 389#else
390# define portmux_setup(...) do { } while (0)
391#endif
1394f032 392
d2b11a46 393#ifndef BF548_FAMILY
a161bb05 394static void default_gpio(unsigned short gpio)
1394f032 395{
1f83b8f1 396 unsigned short bank, bitmask;
2b39331a 397 unsigned long flags;
1394f032
BW		 398
399 bank = gpio_bank(gpio);
400 bitmask = gpio_bit(gpio);
401
2b39331a
MH		 402 local_irq_save(flags);
403
1394f032
BW		 404 gpio_bankb[bank]->maska_clear = bitmask;
405 gpio_bankb[bank]->maskb_clear = bitmask;
406 SSYNC();
407 gpio_bankb[bank]->inen &= ~bitmask;
408 gpio_bankb[bank]->dir &= ~bitmask;
409 gpio_bankb[bank]->polar &= ~bitmask;
410 gpio_bankb[bank]->both &= ~bitmask;
411 gpio_bankb[bank]->edge &= ~bitmask;
2b39331a
MH		 412 AWA_DUMMY_READ(edge);
413 local_irq_restore(flags);
414
1394f032 415}
d2b11a46
MH		 416#else
417# define default_gpio(...) do { } while (0)
418#endif
1394f032 419
a161bb05 420static int __init bfin_gpio_init(void)
1394f032 421{
8c613623
MH		 422 str_ident = kcalloc(MAX_RESOURCES,
423 sizeof(struct str_ident), GFP_KERNEL);
424 if (str_ident == NULL)
c58c2140 425 return -ENOMEM;
1394f032 426
8c613623
MH		 427 memset(str_ident, 0, MAX_RESOURCES * sizeof(struct str_ident));
428
c58c2140 429 printk(KERN_INFO "Blackfin GPIO Controller\n");
1394f032
BW		 430
431 return 0;
c58c2140 432
1394f032 433}
1394f032
BW		 434arch_initcall(bfin_gpio_init);
435
436
d2b11a46 437#ifndef BF548_FAMILY
1394f032
BW		 438/***********************************************************
439*
440* FUNCTIONS: Blackfin General Purpose Ports Access Functions
441*
442* INPUTS/OUTPUTS:
443* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
444*
445*
446* DESCRIPTION: These functions abstract direct register access
447* to Blackfin processor General Purpose
448* Ports Regsiters
449*
450* CAUTION: These functions do not belong to the GPIO Driver API
451*************************************************************
452* MODIFICATION HISTORY :
453**************************************************************/
454
455/* Set a specific bit */
456
457#define SET_GPIO(name) \
458void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
459{ \
460 unsigned long flags; \
c58c2140 461 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
1394f032
BW		 462 local_irq_save(flags); \
463 if (arg) \
464 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
465 else \
466 gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 467 AWA_DUMMY_READ(name); \
1394f032
BW		 468 local_irq_restore(flags); \
469} \
470EXPORT_SYMBOL(set_gpio_ ## name);
471
472SET_GPIO(dir)
473SET_GPIO(inen)
474SET_GPIO(polar)
475SET_GPIO(edge)
476SET_GPIO(both)
477
478
2b39331a
MH		 479#if ANOMALY_05000311 || ANOMALY_05000323
480#define SET_GPIO_SC(name) \
481void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
482{ \
483 unsigned long flags; \
484 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
485 local_irq_save(flags); \
486 if (arg) \
487 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
488 else \
489 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
490 AWA_DUMMY_READ(name); \
491 local_irq_restore(flags); \
492} \
493EXPORT_SYMBOL(set_gpio_ ## name);
494#else
1394f032
BW		 495#define SET_GPIO_SC(name) \
496void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
497{ \
c58c2140 498 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
1394f032
BW		 499 if (arg) \
500 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
501 else \
502 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
503} \
504EXPORT_SYMBOL(set_gpio_ ## name);
2b39331a 505#endif
1394f032
BW		 506
507SET_GPIO_SC(maska)
508SET_GPIO_SC(maskb)
1394f032 509SET_GPIO_SC(data)
1394f032 510
2b39331a 511#if ANOMALY_05000311 || ANOMALY_05000323
1394f032
BW		 512void set_gpio_toggle(unsigned short gpio)
513{
514 unsigned long flags;
c58c2140 515 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 516 local_irq_save(flags);
517 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
2b39331a 518 AWA_DUMMY_READ(toggle);
1394f032
BW		 519 local_irq_restore(flags);
520}
521#else
522void set_gpio_toggle(unsigned short gpio)
523{
c58c2140 524 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 525 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
526}
527#endif
528EXPORT_SYMBOL(set_gpio_toggle);
529
530
531/*Set current PORT date (16-bit word)*/
532
2b39331a 533#if ANOMALY_05000311 || ANOMALY_05000323
1394f032
BW		 534#define SET_GPIO_P(name) \
535void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \
536{ \
2b39331a
MH		 537 unsigned long flags; \
538 local_irq_save(flags); \
1394f032 539 gpio_bankb[gpio_bank(gpio)]->name = arg; \
2b39331a
MH		 540 AWA_DUMMY_READ(name); \
541 local_irq_restore(flags); \
1394f032
BW		 542} \
543EXPORT_SYMBOL(set_gpiop_ ## name);
2b39331a
MH		 544#else
545#define SET_GPIO_P(name) \
546void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \
547{ \
548 gpio_bankb[gpio_bank(gpio)]->name = arg; \
549} \
550EXPORT_SYMBOL(set_gpiop_ ## name);
551#endif
1394f032 552
2b39331a 553SET_GPIO_P(data)
1394f032
BW		 554SET_GPIO_P(dir)
555SET_GPIO_P(inen)
556SET_GPIO_P(polar)
557SET_GPIO_P(edge)
558SET_GPIO_P(both)
559SET_GPIO_P(maska)
560SET_GPIO_P(maskb)
561
562
1394f032 563/* Get a specific bit */
2b39331a
MH		 564#if ANOMALY_05000311 || ANOMALY_05000323
565#define GET_GPIO(name) \
566unsigned short get_gpio_ ## name(unsigned short gpio) \
567{ \
568 unsigned long flags; \
569 unsigned short ret; \
570 local_irq_save(flags); \
571 ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
572 AWA_DUMMY_READ(name); \
573 local_irq_restore(flags); \
574 return ret; \
575} \
576EXPORT_SYMBOL(get_gpio_ ## name);
577#else
1394f032
BW		 578#define GET_GPIO(name) \
579unsigned short get_gpio_ ## name(unsigned short gpio) \
580{ \
581 return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \
582} \
583EXPORT_SYMBOL(get_gpio_ ## name);
2b39331a 584#endif
1394f032 585
2b39331a 586GET_GPIO(data)
1394f032
BW		 587GET_GPIO(dir)
588GET_GPIO(inen)
589GET_GPIO(polar)
590GET_GPIO(edge)
591GET_GPIO(both)
592GET_GPIO(maska)
593GET_GPIO(maskb)
594
1394f032
BW		 595/*Get current PORT date (16-bit word)*/
596
2b39331a
MH		 597#if ANOMALY_05000311 || ANOMALY_05000323
598#define GET_GPIO_P(name) \
599unsigned short get_gpiop_ ## name(unsigned short gpio) \
600{ \
601 unsigned long flags; \
602 unsigned short ret; \
603 local_irq_save(flags); \
604 ret = (gpio_bankb[gpio_bank(gpio)]->name); \
605 AWA_DUMMY_READ(name); \
606 local_irq_restore(flags); \
607 return ret; \
608} \
609EXPORT_SYMBOL(get_gpiop_ ## name);
610#else
1394f032
BW		 611#define GET_GPIO_P(name) \
612unsigned short get_gpiop_ ## name(unsigned short gpio) \
613{ \
614 return (gpio_bankb[gpio_bank(gpio)]->name);\
615} \
616EXPORT_SYMBOL(get_gpiop_ ## name);
2b39331a 617#endif
1394f032 618
2b39331a 619GET_GPIO_P(data)
1394f032
BW		 620GET_GPIO_P(dir)
621GET_GPIO_P(inen)
622GET_GPIO_P(polar)
623GET_GPIO_P(edge)
624GET_GPIO_P(both)
625GET_GPIO_P(maska)
626GET_GPIO_P(maskb)
627
1394f032
BW		 628
629#ifdef CONFIG_PM
630/***********************************************************
631*
632* FUNCTIONS: Blackfin PM Setup API
633*
634* INPUTS/OUTPUTS:
635* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
636* type -
637* PM_WAKE_RISING
638* PM_WAKE_FALLING
639* PM_WAKE_HIGH
640* PM_WAKE_LOW
641* PM_WAKE_BOTH_EDGES
642*
643* DESCRIPTION: Blackfin PM Driver API
644*
645* CAUTION:
646*************************************************************
647* MODIFICATION HISTORY :
648**************************************************************/
649int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type)
650{
651 unsigned long flags;
652
653 if ((check_gpio(gpio) < 0) || !type)
654 return -EINVAL;
655
656 local_irq_save(flags);
657
658 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
659 wakeup_flags_map[gpio] = type;
660 local_irq_restore(flags);
661
662 return 0;
663}
664EXPORT_SYMBOL(gpio_pm_wakeup_request);
665
666void gpio_pm_wakeup_free(unsigned short gpio)
667{
668 unsigned long flags;
669
670 if (check_gpio(gpio) < 0)
671 return;
672
673 local_irq_save(flags);
674
675 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
676
677 local_irq_restore(flags);
678}
679EXPORT_SYMBOL(gpio_pm_wakeup_free);
680
681static int bfin_gpio_wakeup_type(unsigned short gpio, unsigned char type)
682{
683 port_setup(gpio, GPIO_USAGE);
684 set_gpio_dir(gpio, 0);
685 set_gpio_inen(gpio, 1);
686
687 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
688 set_gpio_edge(gpio, 1);
689 else
690 set_gpio_edge(gpio, 0);
691
692 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
693 set_gpio_both(gpio, 1);
694 else
695 set_gpio_both(gpio, 0);
696
697 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
698 set_gpio_polar(gpio, 1);
699 else
700 set_gpio_polar(gpio, 0);
701
702 SSYNC();
703
704 return 0;
705}
706
707u32 gpio_pm_setup(void)
708{
709 u32 sic_iwr = 0;
710 u16 bank, mask, i, gpio;
711
1f83b8f1 712 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 713 mask = wakeup_map[gpio_bank(i)];
714 bank = gpio_bank(i);
715
716 gpio_bank_saved[bank].maskb = gpio_bankb[bank]->maskb;
717 gpio_bankb[bank]->maskb = 0;
718
719 if (mask) {
720#ifdef BF537_FAMILY
721 gpio_bank_saved[bank].fer = *port_fer[bank];
722#endif
723 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
724 gpio_bank_saved[bank].polar = gpio_bankb[bank]->polar;
725 gpio_bank_saved[bank].dir = gpio_bankb[bank]->dir;
726 gpio_bank_saved[bank].edge = gpio_bankb[bank]->edge;
727 gpio_bank_saved[bank].both = gpio_bankb[bank]->both;
c58c2140
MH		 728 gpio_bank_saved[bank].reserved =
729 reserved_gpio_map[bank];
1394f032
BW		 730
731 gpio = i;
732
733 while (mask) {
734 if (mask & 1) {
c58c2140 735 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH		 736 gpio_bit(gpio);
737 bfin_gpio_wakeup_type(gpio,
738 wakeup_flags_map[gpio]);
1394f032
BW		 739 set_gpio_data(gpio, 0); /*Clear*/
740 }
741 gpio++;
742 mask >>= 1;
743 }
744
581d62ab
MH		 745 sic_iwr |= 1 <<
746 (sic_iwr_irqs[bank] - (IRQ_CORETMR + 1));
1394f032
BW		 747 gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
748 }
749 }
750
2b39331a
MH		 751 AWA_DUMMY_READ(maskb_set);
752
1394f032
BW		 753 if (sic_iwr)
754 return sic_iwr;
755 else
756 return IWR_ENABLE_ALL;
757}
758
1394f032
BW		 759void gpio_pm_restore(void)
760{
761 u16 bank, mask, i;
762
1f83b8f1 763 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 764 mask = wakeup_map[gpio_bank(i)];
765 bank = gpio_bank(i);
766
767 if (mask) {
768#ifdef BF537_FAMILY
769 *port_fer[bank] = gpio_bank_saved[bank].fer;
770#endif
771 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
772 gpio_bankb[bank]->dir = gpio_bank_saved[bank].dir;
773 gpio_bankb[bank]->polar = gpio_bank_saved[bank].polar;
774 gpio_bankb[bank]->edge = gpio_bank_saved[bank].edge;
775 gpio_bankb[bank]->both = gpio_bank_saved[bank].both;
581d62ab 776
c58c2140
MH		 777 reserved_gpio_map[bank] =
778 gpio_bank_saved[bank].reserved;
581d62ab 779
1394f032
BW		 780 }
781
782 gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
783 }
2b39331a 784 AWA_DUMMY_READ(maskb);
1394f032
BW		 785}
786
787#endif
d2b11a46 788#endif /* BF548_FAMILY */
1394f032 789
d2b11a46
MH		 790/***********************************************************
791*
792* FUNCTIONS: Blackfin Peripheral Resource Allocation
793* and PortMux Setup
794*
795* INPUTS/OUTPUTS:
796* per Peripheral Identifier
797* label String
798*
799* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
800*
801* CAUTION:
802*************************************************************
803* MODIFICATION HISTORY :
804**************************************************************/
805
806#ifdef BF548_FAMILY
807int peripheral_request(unsigned short per, const char *label)
808{
809 unsigned long flags;
810 unsigned short ident = P_IDENT(per);
811
812 /*
813 * Don't cares are pins with only one dedicated function
814 */
c58c2140 815
d2b11a46
MH		 816 if (per & P_DONTCARE)
817 return 0;
818
819 if (!(per & P_DEFINED))
820 return -ENODEV;
821
822 if (check_gpio(ident) < 0)
823 return -EINVAL;
c58c2140 824
d2b11a46
MH		 825 local_irq_save(flags);
826
827 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
828 printk(KERN_ERR
829 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
830 __FUNCTION__, ident, get_label(ident));
831 dump_stack();
832 local_irq_restore(flags);
833 return -EBUSY;
834 }
835
836 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
837
838 u16 funct = get_portmux(ident);
839
840 /*
841 * Pin functions like AMC address strobes my
842 * be requested and used by several drivers
843 */
844
845 if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
846
847 /*
848 * Allow that the identical pin function can
849 * be requested from the same driver twice
850 */
851
852 if (cmp_label(ident, label) == 0)
853 goto anyway;
854
855 printk(KERN_ERR
856 "%s: Peripheral %d function %d is already reserved by %s !\n",
857 __FUNCTION__, ident, P_FUNCT2MUX(per), get_label(ident));
858 dump_stack();
859 local_irq_restore(flags);
860 return -EBUSY;
861 }
862 }
863
864anyway:
865 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
866
867 portmux_setup(ident, P_FUNCT2MUX(per));
868 port_setup(ident, PERIPHERAL_USAGE);
869
870 local_irq_restore(flags);
871 set_label(ident, label);
872
873 return 0;
874}
875EXPORT_SYMBOL(peripheral_request);
876#else
c58c2140
MH		 877
878int peripheral_request(unsigned short per, const char *label)
879{
880 unsigned long flags;
881 unsigned short ident = P_IDENT(per);
882
883 /*
884 * Don't cares are pins with only one dedicated function
885 */
886
887 if (per & P_DONTCARE)
888 return 0;
889
890 if (!(per & P_DEFINED))
891 return -ENODEV;
892
c58c2140
MH		 893 local_irq_save(flags);
894
cda6a20b
MH		 895 if (!check_gpio(ident)) {
896
c58c2140
MH		 897 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
898 printk(KERN_ERR
899 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
900 __FUNCTION__, ident, get_label(ident));
901 dump_stack();
902 local_irq_restore(flags);
903 return -EBUSY;
904 }
905
cda6a20b
MH		 906 }
907
c58c2140
MH		 908 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
909
910 /*
911 * Pin functions like AMC address strobes my
912 * be requested and used by several drivers
913 */
914
915 if (!(per & P_MAYSHARE)) {
916
917 /*
918 * Allow that the identical pin function can
919 * be requested from the same driver twice
920 */
921
922 if (cmp_label(ident, label) == 0)
923 goto anyway;
924
925 printk(KERN_ERR
926 "%s: Peripheral %d function %d is already"
8c613623 927 " reserved by %s !\n",
c58c2140
MH		 928 __FUNCTION__, ident, P_FUNCT2MUX(per),
929 get_label(ident));
930 dump_stack();
931 local_irq_restore(flags);
932 return -EBUSY;
933 }
934
935 }
936
937anyway:
c58c2140
MH		 938 portmux_setup(per, P_FUNCT2MUX(per));
939
940 port_setup(ident, PERIPHERAL_USAGE);
941
942 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
943 local_irq_restore(flags);
944 set_label(ident, label);
945
946 return 0;
947}
948EXPORT_SYMBOL(peripheral_request);
d2b11a46 949#endif
c58c2140
MH		 950
951int peripheral_request_list(unsigned short per[], const char *label)
952{
953 u16 cnt;
954 int ret;
955
956 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 957
c58c2140 958 ret = peripheral_request(per[cnt], label);
314c98d5
MH		 959
960 if (ret < 0) {
961 for ( ; cnt > 0; cnt--) {
962 peripheral_free(per[cnt - 1]);
963 }
964 return ret;
965 }
c58c2140
MH		 966 }
967
968 return 0;
969}
970EXPORT_SYMBOL(peripheral_request_list);
971
972void peripheral_free(unsigned short per)
973{
974 unsigned long flags;
975 unsigned short ident = P_IDENT(per);
976
977 if (per & P_DONTCARE)
978 return;
979
980 if (!(per & P_DEFINED))
981 return;
982
983 if (check_gpio(ident) < 0)
984 return;
985
986 local_irq_save(flags);
987
988 if (unlikely(!(reserved_peri_map[gpio_bank(ident)]
989 & gpio_bit(ident)))) {
990 local_irq_restore(flags);
991 return;
992 }
993
994 if (!(per & P_MAYSHARE)) {
995 port_setup(ident, GPIO_USAGE);
996 }
997
998 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
999
2acde902
MH		 1000 set_label(ident, "free");
1001
c58c2140
MH		 1002 local_irq_restore(flags);
1003}
1004EXPORT_SYMBOL(peripheral_free);
1005
1006void peripheral_free_list(unsigned short per[])
1007{
1008 u16 cnt;
1009
1010 for (cnt = 0; per[cnt] != 0; cnt++) {
1011 peripheral_free(per[cnt]);
1012 }
1013
1014}
1015EXPORT_SYMBOL(peripheral_free_list);
1016
1394f032
BW		 1017/***********************************************************
1018*
1019* FUNCTIONS: Blackfin GPIO Driver
1020*
1021* INPUTS/OUTPUTS:
d2b11a46
MH		 1022* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
1023* label String
1394f032
BW		 1024*
1025* DESCRIPTION: Blackfin GPIO Driver API
1026*
1027* CAUTION:
1028*************************************************************
1029* MODIFICATION HISTORY :
1030**************************************************************/
1031
1032int gpio_request(unsigned short gpio, const char *label)
1033{
1034 unsigned long flags;
1035
1036 if (check_gpio(gpio) < 0)
1037 return -EINVAL;
1038
1039 local_irq_save(flags);
1040
2acde902
MH		 1041 /*
1042 * Allow that the identical GPIO can
1043 * be requested from the same driver twice
1044 * Do nothing and return -
1045 */
1046
1047 if (cmp_label(gpio, label) == 0) {
1048 local_irq_restore(flags);
1049 return 0;
1050 }
1051
c58c2140 1052 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
d2b11a46
MH		 1053 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
1054 gpio, get_label(gpio));
1055 dump_stack();
1056 local_irq_restore(flags);
1057 return -EBUSY;
1058 }
1059 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1060 printk(KERN_ERR
1061 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1062 gpio, get_label(gpio));
1394f032
BW		 1063 dump_stack();
1064 local_irq_restore(flags);
1065 return -EBUSY;
1066 }
d2b11a46 1067
c58c2140 1068 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1394f032
BW		 1069
1070 local_irq_restore(flags);
1071
1072 port_setup(gpio, GPIO_USAGE);
d2b11a46 1073 set_label(gpio, label);
1394f032
BW		 1074
1075 return 0;
1076}
1077EXPORT_SYMBOL(gpio_request);
1078
1394f032
BW		 1079void gpio_free(unsigned short gpio)
1080{
1081 unsigned long flags;
1082
1083 if (check_gpio(gpio) < 0)
1084 return;
1085
1086 local_irq_save(flags);
1087
c58c2140 1088 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1394f032
BW		 1089 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
1090 dump_stack();
1091 local_irq_restore(flags);
1092 return;
1093 }
1094
1095 default_gpio(gpio);
1096
c58c2140 1097 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032 1098
2acde902
MH		 1099 set_label(gpio, "free");
1100
1394f032
BW		 1101 local_irq_restore(flags);
1102}
1103EXPORT_SYMBOL(gpio_free);
1104
d2b11a46
MH		 1105#ifdef BF548_FAMILY
1106void gpio_direction_input(unsigned short gpio)
1107{
1108 unsigned long flags;
1109
1110 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1111
1112 local_irq_save(flags);
1113 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1114 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1115 local_irq_restore(flags);
1116}
1117EXPORT_SYMBOL(gpio_direction_input);
1118
1119void gpio_direction_output(unsigned short gpio)
1120{
1121 unsigned long flags;
1122
1123 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1124
1125 local_irq_save(flags);
1126 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
1127 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
1128 local_irq_restore(flags);
1129}
1130EXPORT_SYMBOL(gpio_direction_output);
1131
1132void gpio_set_value(unsigned short gpio, unsigned short arg)
1133{
1134 if (arg)
1135 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
1136 else
1137 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
1138
1139}
1140EXPORT_SYMBOL(gpio_set_value);
1141
1142unsigned short gpio_get_value(unsigned short gpio)
1143{
1144 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
1145}
1146EXPORT_SYMBOL(gpio_get_value);
1147
1148#else
1149
1394f032
BW		 1150void gpio_direction_input(unsigned short gpio)
1151{
1152 unsigned long flags;
1153
c58c2140 1154 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 1155
1156 local_irq_save(flags);
1157 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1158 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
2b39331a 1159 AWA_DUMMY_READ(inen);
1394f032
BW		 1160 local_irq_restore(flags);
1161}
1162EXPORT_SYMBOL(gpio_direction_input);
1163
1164void gpio_direction_output(unsigned short gpio)
1165{
1166 unsigned long flags;
1167
c58c2140 1168 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 1169
1170 local_irq_save(flags);
1171 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1172 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
2b39331a 1173 AWA_DUMMY_READ(dir);
1394f032
BW		 1174 local_irq_restore(flags);
1175}
1176EXPORT_SYMBOL(gpio_direction_output);
168f1212
MF		 1177
1178/* If we are booting from SPI and our board lacks a strong enough pull up,
1179 * the core can reset and execute the bootrom faster than the resistor can
1180 * pull the signal logically high. To work around this (common) error in
1181 * board design, we explicitly set the pin back to GPIO mode, force /CS
1182 * high, and wait for the electrons to do their thing.
1183 *
1184 * This function only makes sense to be called from reset code, but it
1185 * lives here as we need to force all the GPIO states w/out going through
1186 * BUG() checks and such.
1187 */
1188void bfin_gpio_reset_spi0_ssel1(void)
1189{
4d5f4ed3
MH		 1190 u16 gpio = P_IDENT(P_SPI0_SSEL1);
1191
1192 port_setup(gpio, GPIO_USAGE);
1193 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
168f1212
MF		 1194 udelay(1);
1195}
d2b11a46
MH		 1196
1197#endif /*BF548_FAMILY */
1545a111
MF		 1198
1199#if defined(CONFIG_PROC_FS)
1200static int gpio_proc_read(char *buf, char **start, off_t offset,
1201 int len, int *unused_i, void *unused_v)
1202{
1203 int c, outlen = 0;
1204
1205 for (c = 0; c < MAX_RESOURCES; c++) {
1206 if (!check_gpio(c) && (reserved_gpio_map[gpio_bank(c)] & gpio_bit(c)))
1207 len = sprintf(buf, "GPIO_%d: %s \tGPIO %s\n", c,
1208 get_label(c), get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1209 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
1210 len = sprintf(buf, "GPIO_%d: %s \tPeripheral\n", c, get_label(c));
1211 else
1212 continue;
1213 buf += len;
1214 outlen += len;
1215 }
1216 return outlen;
1217}
1218
1219static __init int gpio_register_proc(void)
1220{
1221 struct proc_dir_entry *proc_gpio;
1222
1223 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1224 if (proc_gpio)
1225 proc_gpio->read_proc = gpio_proc_read;
1226 return proc_gpio != NULL;
1227}
1228
1229__initcall(gpio_register_proc);
1230#endif
Linux kernel - Deliverables
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