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Blackfin arch: fix cmp_label() so it doesnt incorrectly accept partial leading matches
[deliverable/linux.git] / arch / blackfin / kernel / bfin_gpio.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/bfin_gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
a2c8cfef 10 * Copyright 2008 Analog Devices Inc.
1394f032
BW		 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
d2b11a46 31* Number BF537/6/4 BF561 BF533/2/1 BF549/8/4/2
1394f032 32*
d2b11a46 33* GPIO_0 PF0 PF0 PF0 PA0...PJ13
1394f032
BW		 34* GPIO_1 PF1 PF1 PF1
35* GPIO_2 PF2 PF2 PF2
36* GPIO_3 PF3 PF3 PF3
37* GPIO_4 PF4 PF4 PF4
38* GPIO_5 PF5 PF5 PF5
39* GPIO_6 PF6 PF6 PF6
40* GPIO_7 PF7 PF7 PF7
41* GPIO_8 PF8 PF8 PF8
42* GPIO_9 PF9 PF9 PF9
43* GPIO_10 PF10 PF10 PF10
44* GPIO_11 PF11 PF11 PF11
45* GPIO_12 PF12 PF12 PF12
46* GPIO_13 PF13 PF13 PF13
47* GPIO_14 PF14 PF14 PF14
48* GPIO_15 PF15 PF15 PF15
49* GPIO_16 PG0 PF16
50* GPIO_17 PG1 PF17
51* GPIO_18 PG2 PF18
52* GPIO_19 PG3 PF19
53* GPIO_20 PG4 PF20
54* GPIO_21 PG5 PF21
55* GPIO_22 PG6 PF22
56* GPIO_23 PG7 PF23
57* GPIO_24 PG8 PF24
58* GPIO_25 PG9 PF25
59* GPIO_26 PG10 PF26
60* GPIO_27 PG11 PF27
61* GPIO_28 PG12 PF28
62* GPIO_29 PG13 PF29
63* GPIO_30 PG14 PF30
64* GPIO_31 PG15 PF31
65* GPIO_32 PH0 PF32
66* GPIO_33 PH1 PF33
67* GPIO_34 PH2 PF34
68* GPIO_35 PH3 PF35
69* GPIO_36 PH4 PF36
70* GPIO_37 PH5 PF37
71* GPIO_38 PH6 PF38
72* GPIO_39 PH7 PF39
73* GPIO_40 PH8 PF40
74* GPIO_41 PH9 PF41
75* GPIO_42 PH10 PF42
76* GPIO_43 PH11 PF43
77* GPIO_44 PH12 PF44
78* GPIO_45 PH13 PF45
79* GPIO_46 PH14 PF46
80* GPIO_47 PH15 PF47
81*/
82
168f1212 83#include <linux/delay.h>
1394f032
BW		 84#include <linux/module.h>
85#include <linux/err.h>
1545a111 86#include <linux/proc_fs.h>
1394f032
BW		 87#include <asm/blackfin.h>
88#include <asm/gpio.h>
c58c2140 89#include <asm/portmux.h>
1394f032
BW		 90#include <linux/irq.h>
91
2b39331a
MH		 92#if ANOMALY_05000311 || ANOMALY_05000323
93enum {
94 AWA_data = SYSCR,
95 AWA_data_clear = SYSCR,
96 AWA_data_set = SYSCR,
97 AWA_toggle = SYSCR,
6ed83942
GY		 98 AWA_maska = BFIN_UART_SCR,
99 AWA_maska_clear = BFIN_UART_SCR,
100 AWA_maska_set = BFIN_UART_SCR,
101 AWA_maska_toggle = BFIN_UART_SCR,
102 AWA_maskb = BFIN_UART_GCTL,
103 AWA_maskb_clear = BFIN_UART_GCTL,
104 AWA_maskb_set = BFIN_UART_GCTL,
105 AWA_maskb_toggle = BFIN_UART_GCTL,
2b39331a
MH		 106 AWA_dir = SPORT1_STAT,
107 AWA_polar = SPORT1_STAT,
108 AWA_edge = SPORT1_STAT,
109 AWA_both = SPORT1_STAT,
110#if ANOMALY_05000311
111 AWA_inen = TIMER_ENABLE,
112#elif ANOMALY_05000323
113 AWA_inen = DMA1_1_CONFIG,
114#endif
115};
116 /* Anomaly Workaround */
117#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
118#else
119#define AWA_DUMMY_READ(...) do { } while (0)
120#endif
121
dc26aec2 122#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
1394f032
BW		 123static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
124 (struct gpio_port_t *) FIO_FLAG_D,
125};
126#endif
127
2f6f4bcd 128#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1394f032
BW		 129static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
130 (struct gpio_port_t *) PORTFIO,
131 (struct gpio_port_t *) PORTGIO,
132 (struct gpio_port_t *) PORTHIO,
133};
134
135static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
136 (unsigned short *) PORTF_FER,
137 (unsigned short *) PORTG_FER,
138 (unsigned short *) PORTH_FER,
139};
1394f032
BW		 140#endif
141
2f6f4bcd 142#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
59003145
MH		 143static unsigned short *port_mux[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
144 (unsigned short *) PORTF_MUX,
145 (unsigned short *) PORTG_MUX,
146 (unsigned short *) PORTH_MUX,
147};
148
149static const
150u8 pmux_offset[][16] =
151 {{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
152 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
153 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
154 };
155#endif
156
1394f032
BW		 157#ifdef BF561_FAMILY
158static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
159 (struct gpio_port_t *) FIO0_FLAG_D,
160 (struct gpio_port_t *) FIO1_FLAG_D,
161 (struct gpio_port_t *) FIO2_FLAG_D,
162};
163#endif
164
d2b11a46
MH		 165#ifdef BF548_FAMILY
166static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
167 (struct gpio_port_t *)PORTA_FER,
168 (struct gpio_port_t *)PORTB_FER,
169 (struct gpio_port_t *)PORTC_FER,
170 (struct gpio_port_t *)PORTD_FER,
171 (struct gpio_port_t *)PORTE_FER,
172 (struct gpio_port_t *)PORTF_FER,
173 (struct gpio_port_t *)PORTG_FER,
174 (struct gpio_port_t *)PORTH_FER,
175 (struct gpio_port_t *)PORTI_FER,
176 (struct gpio_port_t *)PORTJ_FER,
177};
178#endif
179
c58c2140 180static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
fac3cf43 181static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
c58c2140 182
8c613623
MH		 183#define RESOURCE_LABEL_SIZE 16
184
fac3cf43 185static struct str_ident {
8c613623 186 char name[RESOURCE_LABEL_SIZE];
fac3cf43 187} str_ident[MAX_RESOURCES];
1394f032 188
1efc80b5
MH		 189#if defined(CONFIG_PM)
190#if defined(CONFIG_BF54x)
191static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
192#else
1394f032
BW		 193static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
194static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
195static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
196
197#ifdef BF533_FAMILY
198static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB};
199#endif
200
201#ifdef BF537_FAMILY
202static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
203#endif
204
dc26aec2
MH		 205#ifdef BF538_FAMILY
206static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB};
207#endif
208
2f6f4bcd 209#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
59003145
MH		 210static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB};
211#endif
212
1394f032
BW		 213#ifdef BF561_FAMILY
214static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
215#endif
1efc80b5 216#endif
1394f032
BW		 217#endif /* CONFIG_PM */
218
a2c8cfef 219inline int check_gpio(unsigned gpio)
d2b11a46 220{
27228b2e 221#if defined(BF548_FAMILY)
d2b11a46
MH		 222 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
223 || gpio == GPIO_PH14 || gpio == GPIO_PH15
27228b2e 224 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
d2b11a46 225 return -EINVAL;
27228b2e 226#endif
e7613aab 227 if (gpio >= MAX_BLACKFIN_GPIOS)
1394f032
BW		 228 return -EINVAL;
229 return 0;
230}
231
74c04503 232static void gpio_error(unsigned gpio)
acbcd263
MH		 233{
234 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
235}
236
c58c2140
MH		 237static void set_label(unsigned short ident, const char *label)
238{
e9fae189 239 if (label) {
8c613623 240 strncpy(str_ident[ident].name, label,
c58c2140 241 RESOURCE_LABEL_SIZE);
8c613623 242 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH		 243 }
244}
245
246static char *get_label(unsigned short ident)
247{
8c613623 248 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH		 249}
250
251static int cmp_label(unsigned short ident, const char *label)
252{
fac3cf43
MH		 253 if (label == NULL) {
254 dump_stack();
255 printk(KERN_ERR "Please provide none-null label\n");
256 }
257
e9fae189 258 if (label)
1f7d373f 259 return strcmp(str_ident[ident].name, label);
c58c2140
MH		 260 else
261 return -EINVAL;
262}
263
2f6f4bcd 264#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
a2c8cfef 265static void port_setup(unsigned gpio, unsigned short usage)
1394f032 266{
cda6a20b 267 if (!check_gpio(gpio)) {
d2b11a46 268 if (usage == GPIO_USAGE)
cda6a20b 269 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
d2b11a46 270 else
cda6a20b
MH		 271 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
272 SSYNC();
273 }
1394f032 274}
d2b11a46 275#elif defined(BF548_FAMILY)
a2c8cfef 276static void port_setup(unsigned gpio, unsigned short usage)
d2b11a46
MH		 277{
278 if (usage == GPIO_USAGE)
279 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
280 else
281 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
282 SSYNC();
283}
1394f032
BW		 284#else
285# define port_setup(...) do { } while (0)
286#endif
287
c58c2140 288#ifdef BF537_FAMILY
8c613623
MH		 289static struct {
290 unsigned short res;
291 unsigned short offset;
292} port_mux_lut[] = {
293 {.res = P_PPI0_D13, .offset = 11},
294 {.res = P_PPI0_D14, .offset = 11},
295 {.res = P_PPI0_D15, .offset = 11},
296 {.res = P_SPORT1_TFS, .offset = 11},
297 {.res = P_SPORT1_TSCLK, .offset = 11},
298 {.res = P_SPORT1_DTPRI, .offset = 11},
299 {.res = P_PPI0_D10, .offset = 10},
300 {.res = P_PPI0_D11, .offset = 10},
301 {.res = P_PPI0_D12, .offset = 10},
302 {.res = P_SPORT1_RSCLK, .offset = 10},
303 {.res = P_SPORT1_RFS, .offset = 10},
304 {.res = P_SPORT1_DRPRI, .offset = 10},
305 {.res = P_PPI0_D8, .offset = 9},
306 {.res = P_PPI0_D9, .offset = 9},
307 {.res = P_SPORT1_DRSEC, .offset = 9},
308 {.res = P_SPORT1_DTSEC, .offset = 9},
309 {.res = P_TMR2, .offset = 8},
310 {.res = P_PPI0_FS3, .offset = 8},
311 {.res = P_TMR3, .offset = 7},
312 {.res = P_SPI0_SSEL4, .offset = 7},
313 {.res = P_TMR4, .offset = 6},
314 {.res = P_SPI0_SSEL5, .offset = 6},
315 {.res = P_TMR5, .offset = 5},
316 {.res = P_SPI0_SSEL6, .offset = 5},
317 {.res = P_UART1_RX, .offset = 4},
318 {.res = P_UART1_TX, .offset = 4},
319 {.res = P_TMR6, .offset = 4},
320 {.res = P_TMR7, .offset = 4},
321 {.res = P_UART0_RX, .offset = 3},
322 {.res = P_UART0_TX, .offset = 3},
323 {.res = P_DMAR0, .offset = 3},
324 {.res = P_DMAR1, .offset = 3},
325 {.res = P_SPORT0_DTSEC, .offset = 1},
326 {.res = P_SPORT0_DRSEC, .offset = 1},
327 {.res = P_CAN0_RX, .offset = 1},
328 {.res = P_CAN0_TX, .offset = 1},
329 {.res = P_SPI0_SSEL7, .offset = 1},
330 {.res = P_SPORT0_TFS, .offset = 0},
331 {.res = P_SPORT0_DTPRI, .offset = 0},
332 {.res = P_SPI0_SSEL2, .offset = 0},
333 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH		 334};
335
336static void portmux_setup(unsigned short per, unsigned short function)
337{
8c613623 338 u16 y, offset, muxreg;
c58c2140 339
8c613623
MH		 340 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
341 if (port_mux_lut[y].res == per) {
c58c2140
MH		 342
343 /* SET PORTMUX REG */
344
8c613623 345 offset = port_mux_lut[y].offset;
c58c2140
MH		 346 muxreg = bfin_read_PORT_MUX();
347
d171c233 348 if (offset != 1)
c58c2140 349 muxreg &= ~(1 << offset);
d171c233 350 else
c58c2140 351 muxreg &= ~(3 << 1);
c58c2140
MH		 352
353 muxreg |= (function << offset);
354 bfin_write_PORT_MUX(muxreg);
355 }
356 }
357}
d2b11a46
MH		 358#elif defined(BF548_FAMILY)
359inline void portmux_setup(unsigned short portno, unsigned short function)
360{
361 u32 pmux;
362
363 pmux = gpio_array[gpio_bank(portno)]->port_mux;
364
365 pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
366 pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
367
368 gpio_array[gpio_bank(portno)]->port_mux = pmux;
369}
370
371inline u16 get_portmux(unsigned short portno)
372{
373 u32 pmux;
c58c2140 374
d2b11a46
MH		 375 pmux = gpio_array[gpio_bank(portno)]->port_mux;
376
377 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
378}
2f6f4bcd 379#elif defined(BF527_FAMILY) || defined(BF518_FAMILY)
59003145
MH		 380inline void portmux_setup(unsigned short portno, unsigned short function)
381{
382 u16 pmux, ident = P_IDENT(portno);
383 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
384
385 pmux = *port_mux[gpio_bank(ident)];
386 pmux &= ~(3 << offset);
387 pmux |= (function & 3) << offset;
388 *port_mux[gpio_bank(ident)] = pmux;
389 SSYNC();
390}
c58c2140
MH		 391#else
392# define portmux_setup(...) do { } while (0)
393#endif
1394f032 394
a161bb05 395static int __init bfin_gpio_init(void)
1394f032 396{
c58c2140 397 printk(KERN_INFO "Blackfin GPIO Controller\n");
1394f032
BW		 398
399 return 0;
400}
1394f032
BW		 401arch_initcall(bfin_gpio_init);
402
403
d2b11a46 404#ifndef BF548_FAMILY
1394f032
BW		 405/***********************************************************
406*
407* FUNCTIONS: Blackfin General Purpose Ports Access Functions
408*
409* INPUTS/OUTPUTS:
410* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
411*
412*
413* DESCRIPTION: These functions abstract direct register access
414* to Blackfin processor General Purpose
415* Ports Regsiters
416*
417* CAUTION: These functions do not belong to the GPIO Driver API
418*************************************************************
419* MODIFICATION HISTORY :
420**************************************************************/
421
422/* Set a specific bit */
423
424#define SET_GPIO(name) \
a2c8cfef 425void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032
BW		 426{ \
427 unsigned long flags; \
1394f032
BW		 428 local_irq_save(flags); \
429 if (arg) \
430 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
431 else \
432 gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 433 AWA_DUMMY_READ(name); \
1394f032
BW		 434 local_irq_restore(flags); \
435} \
436EXPORT_SYMBOL(set_gpio_ ## name);
437
438SET_GPIO(dir)
439SET_GPIO(inen)
440SET_GPIO(polar)
441SET_GPIO(edge)
442SET_GPIO(both)
443
444
2b39331a
MH		 445#if ANOMALY_05000311 || ANOMALY_05000323
446#define SET_GPIO_SC(name) \
a2c8cfef 447void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH		 448{ \
449 unsigned long flags; \
2b39331a
MH		 450 local_irq_save(flags); \
451 if (arg) \
452 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
453 else \
454 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
455 AWA_DUMMY_READ(name); \
456 local_irq_restore(flags); \
457} \
458EXPORT_SYMBOL(set_gpio_ ## name);
459#else
1394f032 460#define SET_GPIO_SC(name) \
a2c8cfef 461void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032 462{ \
1394f032
BW		 463 if (arg) \
464 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
465 else \
466 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
467} \
468EXPORT_SYMBOL(set_gpio_ ## name);
2b39331a 469#endif
1394f032
BW		 470
471SET_GPIO_SC(maska)
472SET_GPIO_SC(maskb)
1394f032 473SET_GPIO_SC(data)
1394f032 474
2b39331a 475#if ANOMALY_05000311 || ANOMALY_05000323
a2c8cfef 476void set_gpio_toggle(unsigned gpio)
1394f032
BW		 477{
478 unsigned long flags;
1394f032
BW		 479 local_irq_save(flags);
480 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
2b39331a 481 AWA_DUMMY_READ(toggle);
1394f032
BW		 482 local_irq_restore(flags);
483}
484#else
a2c8cfef 485void set_gpio_toggle(unsigned gpio)
1394f032 486{
1394f032
BW		 487 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
488}
489#endif
490EXPORT_SYMBOL(set_gpio_toggle);
491
492
493/*Set current PORT date (16-bit word)*/
494
2b39331a 495#if ANOMALY_05000311 || ANOMALY_05000323
1394f032 496#define SET_GPIO_P(name) \
a2c8cfef 497void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
1394f032 498{ \
2b39331a
MH		 499 unsigned long flags; \
500 local_irq_save(flags); \
1394f032 501 gpio_bankb[gpio_bank(gpio)]->name = arg; \
2b39331a
MH		 502 AWA_DUMMY_READ(name); \
503 local_irq_restore(flags); \
1394f032
BW		 504} \
505EXPORT_SYMBOL(set_gpiop_ ## name);
2b39331a
MH		 506#else
507#define SET_GPIO_P(name) \
a2c8cfef 508void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH		 509{ \
510 gpio_bankb[gpio_bank(gpio)]->name = arg; \
511} \
512EXPORT_SYMBOL(set_gpiop_ ## name);
513#endif
1394f032 514
2b39331a 515SET_GPIO_P(data)
1394f032
BW		 516SET_GPIO_P(dir)
517SET_GPIO_P(inen)
518SET_GPIO_P(polar)
519SET_GPIO_P(edge)
520SET_GPIO_P(both)
521SET_GPIO_P(maska)
522SET_GPIO_P(maskb)
523
1394f032 524/* Get a specific bit */
2b39331a
MH		 525#if ANOMALY_05000311 || ANOMALY_05000323
526#define GET_GPIO(name) \
a2c8cfef 527unsigned short get_gpio_ ## name(unsigned gpio) \
2b39331a
MH		 528{ \
529 unsigned long flags; \
530 unsigned short ret; \
531 local_irq_save(flags); \
532 ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
533 AWA_DUMMY_READ(name); \
534 local_irq_restore(flags); \
535 return ret; \
536} \
537EXPORT_SYMBOL(get_gpio_ ## name);
538#else
1394f032 539#define GET_GPIO(name) \
a2c8cfef 540unsigned short get_gpio_ ## name(unsigned gpio) \
1394f032
BW		 541{ \
542 return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \
543} \
544EXPORT_SYMBOL(get_gpio_ ## name);
2b39331a 545#endif
1394f032 546
2b39331a 547GET_GPIO(data)
1394f032
BW		 548GET_GPIO(dir)
549GET_GPIO(inen)
550GET_GPIO(polar)
551GET_GPIO(edge)
552GET_GPIO(both)
553GET_GPIO(maska)
554GET_GPIO(maskb)
555
1394f032
BW		 556/*Get current PORT date (16-bit word)*/
557
2b39331a
MH		 558#if ANOMALY_05000311 || ANOMALY_05000323
559#define GET_GPIO_P(name) \
a2c8cfef 560unsigned short get_gpiop_ ## name(unsigned gpio) \
2b39331a
MH		 561{ \
562 unsigned long flags; \
563 unsigned short ret; \
564 local_irq_save(flags); \
565 ret = (gpio_bankb[gpio_bank(gpio)]->name); \
566 AWA_DUMMY_READ(name); \
567 local_irq_restore(flags); \
568 return ret; \
569} \
570EXPORT_SYMBOL(get_gpiop_ ## name);
571#else
1394f032 572#define GET_GPIO_P(name) \
a2c8cfef 573unsigned short get_gpiop_ ## name(unsigned gpio) \
1394f032
BW		 574{ \
575 return (gpio_bankb[gpio_bank(gpio)]->name);\
576} \
577EXPORT_SYMBOL(get_gpiop_ ## name);
2b39331a 578#endif
1394f032 579
2b39331a 580GET_GPIO_P(data)
1394f032
BW		 581GET_GPIO_P(dir)
582GET_GPIO_P(inen)
583GET_GPIO_P(polar)
584GET_GPIO_P(edge)
585GET_GPIO_P(both)
586GET_GPIO_P(maska)
587GET_GPIO_P(maskb)
588
1394f032
BW		 589
590#ifdef CONFIG_PM
591/***********************************************************
592*
593* FUNCTIONS: Blackfin PM Setup API
594*
595* INPUTS/OUTPUTS:
596* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
597* type -
598* PM_WAKE_RISING
599* PM_WAKE_FALLING
600* PM_WAKE_HIGH
601* PM_WAKE_LOW
602* PM_WAKE_BOTH_EDGES
603*
604* DESCRIPTION: Blackfin PM Driver API
605*
606* CAUTION:
607*************************************************************
608* MODIFICATION HISTORY :
609**************************************************************/
a2c8cfef 610int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
1394f032
BW		 611{
612 unsigned long flags;
613
614 if ((check_gpio(gpio) < 0) || !type)
615 return -EINVAL;
616
617 local_irq_save(flags);
1394f032
BW		 618 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
619 wakeup_flags_map[gpio] = type;
620 local_irq_restore(flags);
621
622 return 0;
623}
624EXPORT_SYMBOL(gpio_pm_wakeup_request);
625
a2c8cfef 626void gpio_pm_wakeup_free(unsigned gpio)
1394f032
BW		 627{
628 unsigned long flags;
629
630 if (check_gpio(gpio) < 0)
631 return;
632
633 local_irq_save(flags);
634
635 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
636
637 local_irq_restore(flags);
638}
639EXPORT_SYMBOL(gpio_pm_wakeup_free);
640
a2c8cfef 641static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
1394f032
BW		 642{
643 port_setup(gpio, GPIO_USAGE);
644 set_gpio_dir(gpio, 0);
645 set_gpio_inen(gpio, 1);
646
647 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
648 set_gpio_edge(gpio, 1);
649 else
650 set_gpio_edge(gpio, 0);
651
652 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
653 set_gpio_both(gpio, 1);
654 else
655 set_gpio_both(gpio, 0);
656
657 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
658 set_gpio_polar(gpio, 1);
659 else
660 set_gpio_polar(gpio, 0);
661
662 SSYNC();
663
664 return 0;
665}
666
1efc80b5 667u32 bfin_pm_standby_setup(void)
1394f032 668{
1394f032
BW		 669 u16 bank, mask, i, gpio;
670
1f83b8f1 671 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 672 mask = wakeup_map[gpio_bank(i)];
673 bank = gpio_bank(i);
674
675 gpio_bank_saved[bank].maskb = gpio_bankb[bank]->maskb;
676 gpio_bankb[bank]->maskb = 0;
677
678 if (mask) {
2f6f4bcd 679#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1394f032
BW		 680 gpio_bank_saved[bank].fer = *port_fer[bank];
681#endif
682 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
683 gpio_bank_saved[bank].polar = gpio_bankb[bank]->polar;
684 gpio_bank_saved[bank].dir = gpio_bankb[bank]->dir;
685 gpio_bank_saved[bank].edge = gpio_bankb[bank]->edge;
686 gpio_bank_saved[bank].both = gpio_bankb[bank]->both;
c58c2140
MH		 687 gpio_bank_saved[bank].reserved =
688 reserved_gpio_map[bank];
1394f032
BW		 689
690 gpio = i;
691
692 while (mask) {
cfefe3c6
MH		 693 if ((mask & 1) && (wakeup_flags_map[gpio] !=
694 PM_WAKE_IGNORE)) {
c58c2140 695 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH		 696 gpio_bit(gpio);
697 bfin_gpio_wakeup_type(gpio,
698 wakeup_flags_map[gpio]);
1394f032
BW		 699 set_gpio_data(gpio, 0); /*Clear*/
700 }
701 gpio++;
702 mask >>= 1;
703 }
704
cfefe3c6 705 bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
1394f032
BW		 706 gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
707 }
708 }
709
2b39331a
MH		 710 AWA_DUMMY_READ(maskb_set);
711
cfefe3c6 712 return 0;
1394f032
BW		 713}
714
1efc80b5 715void bfin_pm_standby_restore(void)
1394f032
BW		 716{
717 u16 bank, mask, i;
718
1f83b8f1 719 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 720 mask = wakeup_map[gpio_bank(i)];
721 bank = gpio_bank(i);
722
723 if (mask) {
2f6f4bcd 724#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1394f032
BW		 725 *port_fer[bank] = gpio_bank_saved[bank].fer;
726#endif
727 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
728 gpio_bankb[bank]->dir = gpio_bank_saved[bank].dir;
729 gpio_bankb[bank]->polar = gpio_bank_saved[bank].polar;
730 gpio_bankb[bank]->edge = gpio_bank_saved[bank].edge;
731 gpio_bankb[bank]->both = gpio_bank_saved[bank].both;
581d62ab 732
c58c2140
MH		 733 reserved_gpio_map[bank] =
734 gpio_bank_saved[bank].reserved;
cfefe3c6 735 bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
1394f032
BW		 736 }
737
738 gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
739 }
2b39331a 740 AWA_DUMMY_READ(maskb);
1394f032
BW		 741}
742
1efc80b5
MH		 743void bfin_gpio_pm_hibernate_suspend(void)
744{
745 int i, bank;
746
747 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
748 bank = gpio_bank(i);
749
2f6f4bcd 750#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
1efc80b5 751 gpio_bank_saved[bank].fer = *port_fer[bank];
2f6f4bcd 752#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
1efc80b5
MH		 753 gpio_bank_saved[bank].mux = *port_mux[bank];
754#else
755 if (bank == 0)
756 gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
757#endif
758#endif
759 gpio_bank_saved[bank].data = gpio_bankb[bank]->data;
760 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
761 gpio_bank_saved[bank].polar = gpio_bankb[bank]->polar;
762 gpio_bank_saved[bank].dir = gpio_bankb[bank]->dir;
763 gpio_bank_saved[bank].edge = gpio_bankb[bank]->edge;
764 gpio_bank_saved[bank].both = gpio_bankb[bank]->both;
765 gpio_bank_saved[bank].maska = gpio_bankb[bank]->maska;
766 }
767
768 AWA_DUMMY_READ(maska);
769}
770
771void bfin_gpio_pm_hibernate_restore(void)
772{
773 int i, bank;
774
775 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
776 bank = gpio_bank(i);
777
2f6f4bcd
BW		 778#if defined(BF527_FAMILY) || defined(BF537_FAMILY) || defined(BF518_FAMILY)
779#if defined(BF527_FAMILY) || defined(BF518_FAMILY)
1efc80b5
MH		 780 *port_mux[bank] = gpio_bank_saved[bank].mux;
781#else
782 if (bank == 0)
783 bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
784#endif
785 *port_fer[bank] = gpio_bank_saved[bank].fer;
786#endif
787 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
788 gpio_bankb[bank]->dir = gpio_bank_saved[bank].dir;
789 gpio_bankb[bank]->polar = gpio_bank_saved[bank].polar;
790 gpio_bankb[bank]->edge = gpio_bank_saved[bank].edge;
791 gpio_bankb[bank]->both = gpio_bank_saved[bank].both;
792
793 gpio_bankb[bank]->data_set = gpio_bank_saved[bank].data
794 | gpio_bank_saved[bank].dir;
795
796 gpio_bankb[bank]->maska = gpio_bank_saved[bank].maska;
797 }
798 AWA_DUMMY_READ(maska);
799}
800
801
1394f032 802#endif
fac3cf43 803#else /* BF548_FAMILY */
1efc80b5
MH		 804#ifdef CONFIG_PM
805
806u32 bfin_pm_standby_setup(void)
807{
808 return 0;
809}
810
811void bfin_pm_standby_restore(void)
812{
813
814}
815
816void bfin_gpio_pm_hibernate_suspend(void)
817{
818 int i, bank;
819
820 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
821 bank = gpio_bank(i);
822
823 gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
824 gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
825 gpio_bank_saved[bank].data = gpio_array[bank]->port_data;
826 gpio_bank_saved[bank].data = gpio_array[bank]->port_data;
827 gpio_bank_saved[bank].inen = gpio_array[bank]->port_inen;
828 gpio_bank_saved[bank].dir = gpio_array[bank]->port_dir_set;
829 }
830}
831
832void bfin_gpio_pm_hibernate_restore(void)
833{
834 int i, bank;
835
836 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
837 bank = gpio_bank(i);
838
839 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
840 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
841 gpio_array[bank]->port_inen = gpio_bank_saved[bank].inen;
842 gpio_array[bank]->port_dir_set = gpio_bank_saved[bank].dir;
843 gpio_array[bank]->port_set = gpio_bank_saved[bank].data
844 | gpio_bank_saved[bank].dir;
845 }
846}
847#endif
fac3cf43 848
a2c8cfef 849unsigned short get_gpio_dir(unsigned gpio)
fac3cf43
MH		 850{
851 return (0x01 & (gpio_array[gpio_bank(gpio)]->port_dir_clear >> gpio_sub_n(gpio)));
852}
853EXPORT_SYMBOL(get_gpio_dir);
854
d2b11a46 855#endif /* BF548_FAMILY */
1394f032 856
d2b11a46
MH		 857/***********************************************************
858*
859* FUNCTIONS: Blackfin Peripheral Resource Allocation
860* and PortMux Setup
861*
862* INPUTS/OUTPUTS:
863* per Peripheral Identifier
864* label String
865*
866* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
867*
868* CAUTION:
869*************************************************************
870* MODIFICATION HISTORY :
871**************************************************************/
872
873#ifdef BF548_FAMILY
874int peripheral_request(unsigned short per, const char *label)
875{
876 unsigned long flags;
877 unsigned short ident = P_IDENT(per);
878
879 /*
880 * Don't cares are pins with only one dedicated function
881 */
c58c2140 882
d2b11a46
MH		 883 if (per & P_DONTCARE)
884 return 0;
885
886 if (!(per & P_DEFINED))
887 return -ENODEV;
888
889 if (check_gpio(ident) < 0)
890 return -EINVAL;
c58c2140 891
d2b11a46
MH		 892 local_irq_save(flags);
893
894 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
f85c4abd 895 dump_stack();
d2b11a46
MH		 896 printk(KERN_ERR
897 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 898 __func__, ident, get_label(ident));
d2b11a46
MH		 899 local_irq_restore(flags);
900 return -EBUSY;
901 }
902
903 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
904
905 u16 funct = get_portmux(ident);
906
d171c233
MF		 907 /*
908 * Pin functions like AMC address strobes my
909 * be requested and used by several drivers
910 */
d2b11a46
MH		 911
912 if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
913
d171c233
MF		 914 /*
915 * Allow that the identical pin function can
916 * be requested from the same driver twice
917 */
d2b11a46 918
d171c233
MF		 919 if (cmp_label(ident, label) == 0)
920 goto anyway;
d2b11a46 921
f85c4abd 922 dump_stack();
d2b11a46
MH		 923 printk(KERN_ERR
924 "%s: Peripheral %d function %d is already reserved by %s !\n",
b85d858b 925 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
d2b11a46
MH		 926 local_irq_restore(flags);
927 return -EBUSY;
928 }
929 }
930
d171c233 931 anyway:
d2b11a46
MH		 932 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
933
934 portmux_setup(ident, P_FUNCT2MUX(per));
935 port_setup(ident, PERIPHERAL_USAGE);
936
937 local_irq_restore(flags);
938 set_label(ident, label);
939
940 return 0;
941}
942EXPORT_SYMBOL(peripheral_request);
943#else
c58c2140
MH		 944
945int peripheral_request(unsigned short per, const char *label)
946{
947 unsigned long flags;
948 unsigned short ident = P_IDENT(per);
949
950 /*
951 * Don't cares are pins with only one dedicated function
952 */
953
954 if (per & P_DONTCARE)
955 return 0;
956
957 if (!(per & P_DEFINED))
958 return -ENODEV;
959
c58c2140
MH		 960 local_irq_save(flags);
961
cda6a20b
MH		 962 if (!check_gpio(ident)) {
963
d171c233
MF		 964 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
965 dump_stack();
966 printk(KERN_ERR
967 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 968 __func__, ident, get_label(ident));
d171c233
MF		 969 local_irq_restore(flags);
970 return -EBUSY;
971 }
c58c2140 972
cda6a20b
MH		 973 }
974
c58c2140
MH		 975 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
976
d171c233
MF		 977 /*
978 * Pin functions like AMC address strobes my
979 * be requested and used by several drivers
980 */
c58c2140 981
d171c233 982 if (!(per & P_MAYSHARE)) {
c58c2140 983
d171c233
MF		 984 /*
985 * Allow that the identical pin function can
986 * be requested from the same driver twice
987 */
c58c2140 988
d171c233
MF		 989 if (cmp_label(ident, label) == 0)
990 goto anyway;
c58c2140 991
f85c4abd 992 dump_stack();
c58c2140
MH		 993 printk(KERN_ERR
994 "%s: Peripheral %d function %d is already"
8c613623 995 " reserved by %s !\n",
b85d858b 996 __func__, ident, P_FUNCT2MUX(per),
c58c2140 997 get_label(ident));
c58c2140
MH		 998 local_irq_restore(flags);
999 return -EBUSY;
1000 }
1001
1002 }
1003
d171c233 1004 anyway:
c58c2140
MH		 1005 portmux_setup(per, P_FUNCT2MUX(per));
1006
1007 port_setup(ident, PERIPHERAL_USAGE);
1008
1009 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
1010 local_irq_restore(flags);
1011 set_label(ident, label);
1012
1013 return 0;
1014}
1015EXPORT_SYMBOL(peripheral_request);
d2b11a46 1016#endif
c58c2140 1017
68179371 1018int peripheral_request_list(const unsigned short per[], const char *label)
c58c2140
MH		 1019{
1020 u16 cnt;
1021 int ret;
1022
1023 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 1024
c58c2140 1025 ret = peripheral_request(per[cnt], label);
314c98d5
MH		 1026
1027 if (ret < 0) {
d171c233 1028 for ( ; cnt > 0; cnt--)
314c98d5 1029 peripheral_free(per[cnt - 1]);
d171c233
MF		 1030
1031 return ret;
314c98d5 1032 }
c58c2140
MH		 1033 }
1034
1035 return 0;
1036}
1037EXPORT_SYMBOL(peripheral_request_list);
1038
1039void peripheral_free(unsigned short per)
1040{
1041 unsigned long flags;
1042 unsigned short ident = P_IDENT(per);
1043
1044 if (per & P_DONTCARE)
1045 return;
1046
1047 if (!(per & P_DEFINED))
1048 return;
1049
1050 if (check_gpio(ident) < 0)
1051 return;
1052
1053 local_irq_save(flags);
1054
d171c233 1055 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
c58c2140
MH		 1056 local_irq_restore(flags);
1057 return;
1058 }
1059
d171c233 1060 if (!(per & P_MAYSHARE))
c58c2140 1061 port_setup(ident, GPIO_USAGE);
c58c2140
MH		 1062
1063 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
1064
2acde902
MH		 1065 set_label(ident, "free");
1066
c58c2140
MH		 1067 local_irq_restore(flags);
1068}
1069EXPORT_SYMBOL(peripheral_free);
1070
68179371 1071void peripheral_free_list(const unsigned short per[])
c58c2140
MH		 1072{
1073 u16 cnt;
d171c233 1074 for (cnt = 0; per[cnt] != 0; cnt++)
c58c2140 1075 peripheral_free(per[cnt]);
c58c2140
MH		 1076}
1077EXPORT_SYMBOL(peripheral_free_list);
1078
1394f032
BW		 1079/***********************************************************
1080*
1081* FUNCTIONS: Blackfin GPIO Driver
1082*
1083* INPUTS/OUTPUTS:
d2b11a46
MH		 1084* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
1085* label String
1394f032
BW		 1086*
1087* DESCRIPTION: Blackfin GPIO Driver API
1088*
1089* CAUTION:
1090*************************************************************
1091* MODIFICATION HISTORY :
1092**************************************************************/
1093
acbcd263 1094int gpio_request(unsigned gpio, const char *label)
1394f032
BW		 1095{
1096 unsigned long flags;
1097
1098 if (check_gpio(gpio) < 0)
1099 return -EINVAL;
1100
1101 local_irq_save(flags);
1102
2acde902
MH		 1103 /*
1104 * Allow that the identical GPIO can
1105 * be requested from the same driver twice
1106 * Do nothing and return -
1107 */
1108
1109 if (cmp_label(gpio, label) == 0) {
1110 local_irq_restore(flags);
1111 return 0;
1112 }
1113
c58c2140 1114 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 1115 dump_stack();
d2b11a46
MH		 1116 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
1117 gpio, get_label(gpio));
d2b11a46
MH		 1118 local_irq_restore(flags);
1119 return -EBUSY;
1120 }
1121 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
f85c4abd 1122 dump_stack();
d2b11a46
MH		 1123 printk(KERN_ERR
1124 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1125 gpio, get_label(gpio));
1394f032
BW		 1126 local_irq_restore(flags);
1127 return -EBUSY;
1128 }
d2b11a46 1129
c58c2140 1130 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1394f032
BW		 1131
1132 local_irq_restore(flags);
1133
1134 port_setup(gpio, GPIO_USAGE);
d2b11a46 1135 set_label(gpio, label);
1394f032
BW		 1136
1137 return 0;
1138}
1139EXPORT_SYMBOL(gpio_request);
1140
acbcd263 1141void gpio_free(unsigned gpio)
1394f032
BW		 1142{
1143 unsigned long flags;
1144
1145 if (check_gpio(gpio) < 0)
1146 return;
1147
1148 local_irq_save(flags);
1149
c58c2140 1150 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1394f032 1151 dump_stack();
f85c4abd 1152 gpio_error(gpio);
1394f032
BW		 1153 local_irq_restore(flags);
1154 return;
1155 }
1156
c58c2140 1157 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032 1158
2acde902
MH		 1159 set_label(gpio, "free");
1160
1394f032
BW		 1161 local_irq_restore(flags);
1162}
1163EXPORT_SYMBOL(gpio_free);
1164
acbcd263 1165
d2b11a46 1166#ifdef BF548_FAMILY
acbcd263 1167int gpio_direction_input(unsigned gpio)
d2b11a46
MH		 1168{
1169 unsigned long flags;
1170
acbcd263
MH		 1171 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1172 gpio_error(gpio);
1173 return -EINVAL;
1174 }
1175
d2b11a46
MH		 1176 local_irq_save(flags);
1177 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1178 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1179 local_irq_restore(flags);
acbcd263
MH		 1180
1181 return 0;
d2b11a46
MH		 1182}
1183EXPORT_SYMBOL(gpio_direction_input);
1184
acbcd263 1185int gpio_direction_output(unsigned gpio, int value)
d2b11a46
MH		 1186{
1187 unsigned long flags;
1188
acbcd263
MH		 1189 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1190 gpio_error(gpio);
1191 return -EINVAL;
1192 }
d2b11a46
MH		 1193
1194 local_irq_save(flags);
1195 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
acbcd263 1196 gpio_set_value(gpio, value);
d2b11a46
MH		 1197 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
1198 local_irq_restore(flags);
acbcd263
MH		 1199
1200 return 0;
d2b11a46
MH		 1201}
1202EXPORT_SYMBOL(gpio_direction_output);
1203
acbcd263 1204void gpio_set_value(unsigned gpio, int arg)
d2b11a46
MH		 1205{
1206 if (arg)
1207 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
1208 else
1209 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
d2b11a46
MH		 1210}
1211EXPORT_SYMBOL(gpio_set_value);
1212
acbcd263 1213int gpio_get_value(unsigned gpio)
d2b11a46
MH		 1214{
1215 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
1216}
1217EXPORT_SYMBOL(gpio_get_value);
1218
affee2b2
MH		 1219void bfin_gpio_irq_prepare(unsigned gpio)
1220{
1221 unsigned long flags;
1222
1223 port_setup(gpio, GPIO_USAGE);
1224
1225 local_irq_save(flags);
1226 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1227 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1228 local_irq_restore(flags);
1229}
1230
d2b11a46
MH		 1231#else
1232
803a8d2a
MH		 1233int gpio_get_value(unsigned gpio)
1234{
1235 unsigned long flags;
1236 int ret;
1237
1238 if (unlikely(get_gpio_edge(gpio))) {
1239 local_irq_save(flags);
1240 set_gpio_edge(gpio, 0);
1241 ret = get_gpio_data(gpio);
1242 set_gpio_edge(gpio, 1);
1243 local_irq_restore(flags);
1244
1245 return ret;
1246 } else
1247 return get_gpio_data(gpio);
1248}
1249EXPORT_SYMBOL(gpio_get_value);
1250
1251
acbcd263 1252int gpio_direction_input(unsigned gpio)
1394f032
BW		 1253{
1254 unsigned long flags;
1255
acbcd263
MH		 1256 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1257 gpio_error(gpio);
1258 return -EINVAL;
1259 }
1394f032
BW		 1260
1261 local_irq_save(flags);
1262 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1263 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
2b39331a 1264 AWA_DUMMY_READ(inen);
1394f032 1265 local_irq_restore(flags);
acbcd263
MH		 1266
1267 return 0;
1394f032
BW		 1268}
1269EXPORT_SYMBOL(gpio_direction_input);
1270
acbcd263 1271int gpio_direction_output(unsigned gpio, int value)
1394f032
BW		 1272{
1273 unsigned long flags;
1274
acbcd263
MH		 1275 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1276 gpio_error(gpio);
1277 return -EINVAL;
1278 }
1394f032
BW		 1279
1280 local_irq_save(flags);
1281 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
a2c8cfef
MH		 1282
1283 if (value)
1284 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
1285 else
1286 gpio_bankb[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
1287
1394f032 1288 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
2b39331a 1289 AWA_DUMMY_READ(dir);
1394f032 1290 local_irq_restore(flags);
acbcd263
MH		 1291
1292 return 0;
1394f032
BW		 1293}
1294EXPORT_SYMBOL(gpio_direction_output);
168f1212
MF		 1295
1296/* If we are booting from SPI and our board lacks a strong enough pull up,
1297 * the core can reset and execute the bootrom faster than the resistor can
1298 * pull the signal logically high. To work around this (common) error in
1299 * board design, we explicitly set the pin back to GPIO mode, force /CS
1300 * high, and wait for the electrons to do their thing.
1301 *
1302 * This function only makes sense to be called from reset code, but it
1303 * lives here as we need to force all the GPIO states w/out going through
1304 * BUG() checks and such.
1305 */
1306void bfin_gpio_reset_spi0_ssel1(void)
1307{
4d5f4ed3
MH		 1308 u16 gpio = P_IDENT(P_SPI0_SSEL1);
1309
1310 port_setup(gpio, GPIO_USAGE);
1311 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
a2c8cfef 1312 AWA_DUMMY_READ(data_set);
168f1212
MF		 1313 udelay(1);
1314}
d2b11a46 1315
affee2b2
MH		 1316void bfin_gpio_irq_prepare(unsigned gpio)
1317{
1318 port_setup(gpio, GPIO_USAGE);
1319}
1320
d2b11a46 1321#endif /*BF548_FAMILY */
1545a111
MF		 1322
1323#if defined(CONFIG_PROC_FS)
1324static int gpio_proc_read(char *buf, char **start, off_t offset,
1325 int len, int *unused_i, void *unused_v)
1326{
1327 int c, outlen = 0;
1328
1329 for (c = 0; c < MAX_RESOURCES; c++) {
1330 if (!check_gpio(c) && (reserved_gpio_map[gpio_bank(c)] & gpio_bit(c)))
fac3cf43 1331 len = sprintf(buf, "GPIO_%d: %s \t\tGPIO %s\n", c,
1545a111
MF		 1332 get_label(c), get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1333 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
fac3cf43 1334 len = sprintf(buf, "GPIO_%d: %s \t\tPeripheral\n", c, get_label(c));
1545a111
MF		 1335 else
1336 continue;
1337 buf += len;
1338 outlen += len;
1339 }
1340 return outlen;
1341}
1342
1343static __init int gpio_register_proc(void)
1344{
1345 struct proc_dir_entry *proc_gpio;
1346
1347 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1348 if (proc_gpio)
1349 proc_gpio->read_proc = gpio_proc_read;
1350 return proc_gpio != NULL;
1351}
1545a111
MF		 1352__initcall(gpio_register_proc);
1353#endif
Linux kernel - Deliverables
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