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Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux...
[deliverable/linux.git] / arch / blackfin / kernel / bfin_gpio.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/bfin_gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
a2c8cfef 10 * Copyright 2008 Analog Devices Inc.
1394f032
BW		 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
168f1212 30#include <linux/delay.h>
1394f032
BW		 31#include <linux/module.h>
32#include <linux/err.h>
1545a111 33#include <linux/proc_fs.h>
1394f032
BW		 34#include <asm/blackfin.h>
35#include <asm/gpio.h>
c58c2140 36#include <asm/portmux.h>
1394f032
BW		 37#include <linux/irq.h>
38
2b39331a
MH		 39#if ANOMALY_05000311 || ANOMALY_05000323
40enum {
41 AWA_data = SYSCR,
42 AWA_data_clear = SYSCR,
43 AWA_data_set = SYSCR,
44 AWA_toggle = SYSCR,
6ed83942
GY		 45 AWA_maska = BFIN_UART_SCR,
46 AWA_maska_clear = BFIN_UART_SCR,
47 AWA_maska_set = BFIN_UART_SCR,
48 AWA_maska_toggle = BFIN_UART_SCR,
49 AWA_maskb = BFIN_UART_GCTL,
50 AWA_maskb_clear = BFIN_UART_GCTL,
51 AWA_maskb_set = BFIN_UART_GCTL,
52 AWA_maskb_toggle = BFIN_UART_GCTL,
2b39331a
MH		 53 AWA_dir = SPORT1_STAT,
54 AWA_polar = SPORT1_STAT,
55 AWA_edge = SPORT1_STAT,
56 AWA_both = SPORT1_STAT,
57#if ANOMALY_05000311
58 AWA_inen = TIMER_ENABLE,
59#elif ANOMALY_05000323
60 AWA_inen = DMA1_1_CONFIG,
61#endif
62};
63 /* Anomaly Workaround */
64#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
65#else
66#define AWA_DUMMY_READ(...) do { } while (0)
67#endif
68
f556309e 69static struct gpio_port_t * const gpio_array[] = {
dc26aec2 70#if defined(BF533_FAMILY) || defined(BF538_FAMILY)
1394f032 71 (struct gpio_port_t *) FIO_FLAG_D,
269647dc 72#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
1394f032
BW		 73 (struct gpio_port_t *) PORTFIO,
74 (struct gpio_port_t *) PORTGIO,
75 (struct gpio_port_t *) PORTHIO,
f556309e
MF		 76#elif defined(BF561_FAMILY)
77 (struct gpio_port_t *) FIO0_FLAG_D,
78 (struct gpio_port_t *) FIO1_FLAG_D,
79 (struct gpio_port_t *) FIO2_FLAG_D,
269647dc 80#elif defined(CONFIG_BF54x)
f556309e
MF		 81 (struct gpio_port_t *)PORTA_FER,
82 (struct gpio_port_t *)PORTB_FER,
83 (struct gpio_port_t *)PORTC_FER,
84 (struct gpio_port_t *)PORTD_FER,
85 (struct gpio_port_t *)PORTE_FER,
86 (struct gpio_port_t *)PORTF_FER,
87 (struct gpio_port_t *)PORTG_FER,
88 (struct gpio_port_t *)PORTH_FER,
89 (struct gpio_port_t *)PORTI_FER,
90 (struct gpio_port_t *)PORTJ_FER,
91#else
92# error no gpio arrays defined
93#endif
1394f032
BW		 94};
95
269647dc 96#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
f556309e 97static unsigned short * const port_fer[] = {
1394f032
BW		 98 (unsigned short *) PORTF_FER,
99 (unsigned short *) PORTG_FER,
100 (unsigned short *) PORTH_FER,
101};
1394f032 102
f556309e
MF		 103# if !defined(BF537_FAMILY)
104static unsigned short * const port_mux[] = {
59003145
MH		 105 (unsigned short *) PORTF_MUX,
106 (unsigned short *) PORTG_MUX,
107 (unsigned short *) PORTH_MUX,
108};
109
110static const
0ce5eaf8 111u8 pmux_offset[][16] = {
269647dc 112# if defined(CONFIG_BF52x)
0ce5eaf8
GY		 113 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
114 { 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
115 { 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
269647dc 116# elif defined(CONFIG_BF51x)
0ce5eaf8
GY		 117 { 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
118 { 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
119 { 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
120# endif
121};
f556309e 122# endif
0ce5eaf8 123
d2b11a46
MH		 124#endif
125
397861cd 126static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
fac3cf43 127static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
9570ff4a 128static unsigned short reserved_gpio_irq_map[GPIO_BANK_NUM];
c58c2140 129
8c613623
MH		 130#define RESOURCE_LABEL_SIZE 16
131
fac3cf43 132static struct str_ident {
8c613623 133 char name[RESOURCE_LABEL_SIZE];
fac3cf43 134} str_ident[MAX_RESOURCES];
1394f032 135
1efc80b5 136#if defined(CONFIG_PM)
397861cd 137static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
59003145
MH		 138#endif
139
a2c8cfef 140inline int check_gpio(unsigned gpio)
d2b11a46 141{
269647dc 142#if defined(CONFIG_BF54x)
d2b11a46
MH		 143 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
144 || gpio == GPIO_PH14 || gpio == GPIO_PH15
27228b2e 145 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
d2b11a46 146 return -EINVAL;
27228b2e 147#endif
e7613aab 148 if (gpio >= MAX_BLACKFIN_GPIOS)
1394f032
BW		 149 return -EINVAL;
150 return 0;
151}
152
74c04503 153static void gpio_error(unsigned gpio)
acbcd263
MH		 154{
155 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
156}
157
c58c2140
MH		 158static void set_label(unsigned short ident, const char *label)
159{
e9fae189 160 if (label) {
8c613623 161 strncpy(str_ident[ident].name, label,
c58c2140 162 RESOURCE_LABEL_SIZE);
8c613623 163 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH		 164 }
165}
166
167static char *get_label(unsigned short ident)
168{
8c613623 169 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH		 170}
171
172static int cmp_label(unsigned short ident, const char *label)
173{
fac3cf43
MH		 174 if (label == NULL) {
175 dump_stack();
176 printk(KERN_ERR "Please provide none-null label\n");
177 }
178
e9fae189 179 if (label)
1f7d373f 180 return strcmp(str_ident[ident].name, label);
c58c2140
MH		 181 else
182 return -EINVAL;
183}
184
a2c8cfef 185static void port_setup(unsigned gpio, unsigned short usage)
1394f032 186{
a2d03a1d
MF		 187 if (check_gpio(gpio))
188 return;
189
269647dc 190#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
a2d03a1d
MF		 191 if (usage == GPIO_USAGE)
192 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
193 else
194 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
195 SSYNC();
269647dc 196#elif defined(CONFIG_BF54x)
d2b11a46
MH		 197 if (usage == GPIO_USAGE)
198 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
199 else
200 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
201 SSYNC();
1394f032 202#endif
a2d03a1d 203}
1394f032 204
c58c2140 205#ifdef BF537_FAMILY
8c613623
MH		 206static struct {
207 unsigned short res;
208 unsigned short offset;
209} port_mux_lut[] = {
210 {.res = P_PPI0_D13, .offset = 11},
211 {.res = P_PPI0_D14, .offset = 11},
212 {.res = P_PPI0_D15, .offset = 11},
213 {.res = P_SPORT1_TFS, .offset = 11},
214 {.res = P_SPORT1_TSCLK, .offset = 11},
215 {.res = P_SPORT1_DTPRI, .offset = 11},
216 {.res = P_PPI0_D10, .offset = 10},
217 {.res = P_PPI0_D11, .offset = 10},
218 {.res = P_PPI0_D12, .offset = 10},
219 {.res = P_SPORT1_RSCLK, .offset = 10},
220 {.res = P_SPORT1_RFS, .offset = 10},
221 {.res = P_SPORT1_DRPRI, .offset = 10},
222 {.res = P_PPI0_D8, .offset = 9},
223 {.res = P_PPI0_D9, .offset = 9},
224 {.res = P_SPORT1_DRSEC, .offset = 9},
225 {.res = P_SPORT1_DTSEC, .offset = 9},
226 {.res = P_TMR2, .offset = 8},
227 {.res = P_PPI0_FS3, .offset = 8},
228 {.res = P_TMR3, .offset = 7},
229 {.res = P_SPI0_SSEL4, .offset = 7},
230 {.res = P_TMR4, .offset = 6},
231 {.res = P_SPI0_SSEL5, .offset = 6},
232 {.res = P_TMR5, .offset = 5},
233 {.res = P_SPI0_SSEL6, .offset = 5},
234 {.res = P_UART1_RX, .offset = 4},
235 {.res = P_UART1_TX, .offset = 4},
236 {.res = P_TMR6, .offset = 4},
237 {.res = P_TMR7, .offset = 4},
238 {.res = P_UART0_RX, .offset = 3},
239 {.res = P_UART0_TX, .offset = 3},
240 {.res = P_DMAR0, .offset = 3},
241 {.res = P_DMAR1, .offset = 3},
242 {.res = P_SPORT0_DTSEC, .offset = 1},
243 {.res = P_SPORT0_DRSEC, .offset = 1},
244 {.res = P_CAN0_RX, .offset = 1},
245 {.res = P_CAN0_TX, .offset = 1},
246 {.res = P_SPI0_SSEL7, .offset = 1},
247 {.res = P_SPORT0_TFS, .offset = 0},
248 {.res = P_SPORT0_DTPRI, .offset = 0},
249 {.res = P_SPI0_SSEL2, .offset = 0},
250 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH		 251};
252
f556309e 253static void portmux_setup(unsigned short per)
c58c2140 254{
8c613623 255 u16 y, offset, muxreg;
f556309e 256 u16 function = P_FUNCT2MUX(per);
c58c2140 257
8c613623
MH		 258 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
259 if (port_mux_lut[y].res == per) {
c58c2140
MH		 260
261 /* SET PORTMUX REG */
262
8c613623 263 offset = port_mux_lut[y].offset;
c58c2140
MH		 264 muxreg = bfin_read_PORT_MUX();
265
d171c233 266 if (offset != 1)
c58c2140 267 muxreg &= ~(1 << offset);
d171c233 268 else
c58c2140 269 muxreg &= ~(3 << 1);
c58c2140
MH		 270
271 muxreg |= (function << offset);
272 bfin_write_PORT_MUX(muxreg);
273 }
274 }
275}
269647dc 276#elif defined(CONFIG_BF54x)
f556309e 277inline void portmux_setup(unsigned short per)
d2b11a46
MH		 278{
279 u32 pmux;
f556309e
MF		 280 u16 ident = P_IDENT(per);
281 u16 function = P_FUNCT2MUX(per);
d2b11a46 282
f556309e 283 pmux = gpio_array[gpio_bank(ident)]->port_mux;
d2b11a46 284
f556309e
MF		 285 pmux &= ~(0x3 << (2 * gpio_sub_n(ident)));
286 pmux |= (function & 0x3) << (2 * gpio_sub_n(ident));
d2b11a46 287
f556309e 288 gpio_array[gpio_bank(ident)]->port_mux = pmux;
d2b11a46
MH		 289}
290
f556309e 291inline u16 get_portmux(unsigned short per)
d2b11a46
MH		 292{
293 u32 pmux;
f556309e 294 u16 ident = P_IDENT(per);
c58c2140 295
f556309e 296 pmux = gpio_array[gpio_bank(ident)]->port_mux;
d2b11a46 297
f556309e 298 return (pmux >> (2 * gpio_sub_n(ident)) & 0x3);
d2b11a46 299}
269647dc 300#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 301inline void portmux_setup(unsigned short per)
59003145 302{
f556309e 303 u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per);
59003145
MH		 304 u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
305
306 pmux = *port_mux[gpio_bank(ident)];
307 pmux &= ~(3 << offset);
308 pmux |= (function & 3) << offset;
309 *port_mux[gpio_bank(ident)] = pmux;
310 SSYNC();
311}
c58c2140
MH		 312#else
313# define portmux_setup(...) do { } while (0)
314#endif
1394f032 315
269647dc 316#ifndef CONFIG_BF54x
1394f032
BW		 317/***********************************************************
318*
319* FUNCTIONS: Blackfin General Purpose Ports Access Functions
320*
321* INPUTS/OUTPUTS:
322* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
323*
324*
325* DESCRIPTION: These functions abstract direct register access
326* to Blackfin processor General Purpose
327* Ports Regsiters
328*
329* CAUTION: These functions do not belong to the GPIO Driver API
330*************************************************************
331* MODIFICATION HISTORY :
332**************************************************************/
333
334/* Set a specific bit */
335
336#define SET_GPIO(name) \
a2c8cfef 337void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
1394f032
BW		 338{ \
339 unsigned long flags; \
6a01f230 340 local_irq_save_hw(flags); \
1394f032 341 if (arg) \
f556309e 342 gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
1394f032 343 else \
f556309e 344 gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 345 AWA_DUMMY_READ(name); \
6a01f230 346 local_irq_restore_hw(flags); \
1394f032
BW		 347} \
348EXPORT_SYMBOL(set_gpio_ ## name);
349
f556309e
MF		 350SET_GPIO(dir) /* set_gpio_dir() */
351SET_GPIO(inen) /* set_gpio_inen() */
352SET_GPIO(polar) /* set_gpio_polar() */
353SET_GPIO(edge) /* set_gpio_edge() */
354SET_GPIO(both) /* set_gpio_both() */
1394f032
BW		 355
356
2b39331a 357#define SET_GPIO_SC(name) \
a2c8cfef 358void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
2b39331a
MH		 359{ \
360 unsigned long flags; \
f556309e
MF		 361 if (ANOMALY_05000311 || ANOMALY_05000323) \
362 local_irq_save_hw(flags); \
1394f032 363 if (arg) \
f556309e 364 gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
1394f032 365 else \
f556309e
MF		 366 gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
367 if (ANOMALY_05000311 || ANOMALY_05000323) { \
368 AWA_DUMMY_READ(name); \
369 local_irq_restore_hw(flags); \
370 } \
1394f032
BW		 371} \
372EXPORT_SYMBOL(set_gpio_ ## name);
373
374SET_GPIO_SC(maska)
375SET_GPIO_SC(maskb)
1394f032 376SET_GPIO_SC(data)
1394f032 377
a2c8cfef 378void set_gpio_toggle(unsigned gpio)
1394f032
BW		 379{
380 unsigned long flags;
f556309e
MF		 381 if (ANOMALY_05000311 || ANOMALY_05000323)
382 local_irq_save_hw(flags);
383 gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
384 if (ANOMALY_05000311 || ANOMALY_05000323) {
385 AWA_DUMMY_READ(toggle);
386 local_irq_restore_hw(flags);
387 }
1394f032 388}
1394f032
BW		 389EXPORT_SYMBOL(set_gpio_toggle);
390
391
392/*Set current PORT date (16-bit word)*/
393
394#define SET_GPIO_P(name) \
a2c8cfef 395void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
1394f032 396{ \
2b39331a 397 unsigned long flags; \
f556309e
MF		 398 if (ANOMALY_05000311 || ANOMALY_05000323) \
399 local_irq_save_hw(flags); \
400 gpio_array[gpio_bank(gpio)]->name = arg; \
401 if (ANOMALY_05000311 || ANOMALY_05000323) { \
402 AWA_DUMMY_READ(name); \
403 local_irq_restore_hw(flags); \
404 } \
2b39331a
MH		 405} \
406EXPORT_SYMBOL(set_gpiop_ ## name);
1394f032 407
2b39331a 408SET_GPIO_P(data)
1394f032
BW		 409SET_GPIO_P(dir)
410SET_GPIO_P(inen)
411SET_GPIO_P(polar)
412SET_GPIO_P(edge)
413SET_GPIO_P(both)
414SET_GPIO_P(maska)
415SET_GPIO_P(maskb)
416
1394f032 417/* Get a specific bit */
2b39331a 418#define GET_GPIO(name) \
a2c8cfef 419unsigned short get_gpio_ ## name(unsigned gpio) \
2b39331a
MH		 420{ \
421 unsigned long flags; \
422 unsigned short ret; \
f556309e
MF		 423 if (ANOMALY_05000311 || ANOMALY_05000323) \
424 local_irq_save_hw(flags); \
425 ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
426 if (ANOMALY_05000311 || ANOMALY_05000323) { \
427 AWA_DUMMY_READ(name); \
428 local_irq_restore_hw(flags); \
429 } \
2b39331a
MH		 430 return ret; \
431} \
432EXPORT_SYMBOL(get_gpio_ ## name);
1394f032 433
2b39331a 434GET_GPIO(data)
1394f032
BW		 435GET_GPIO(dir)
436GET_GPIO(inen)
437GET_GPIO(polar)
438GET_GPIO(edge)
439GET_GPIO(both)
440GET_GPIO(maska)
441GET_GPIO(maskb)
442
1394f032
BW		 443/*Get current PORT date (16-bit word)*/
444
2b39331a 445#define GET_GPIO_P(name) \
a2c8cfef 446unsigned short get_gpiop_ ## name(unsigned gpio) \
2b39331a
MH		 447{ \
448 unsigned long flags; \
449 unsigned short ret; \
f556309e
MF		 450 if (ANOMALY_05000311 || ANOMALY_05000323) \
451 local_irq_save_hw(flags); \
452 ret = (gpio_array[gpio_bank(gpio)]->name); \
453 if (ANOMALY_05000311 || ANOMALY_05000323) { \
454 AWA_DUMMY_READ(name); \
455 local_irq_restore_hw(flags); \
456 } \
2b39331a
MH		 457 return ret; \
458} \
459EXPORT_SYMBOL(get_gpiop_ ## name);
1394f032 460
2b39331a 461GET_GPIO_P(data)
1394f032
BW		 462GET_GPIO_P(dir)
463GET_GPIO_P(inen)
464GET_GPIO_P(polar)
465GET_GPIO_P(edge)
466GET_GPIO_P(both)
467GET_GPIO_P(maska)
468GET_GPIO_P(maskb)
469
1394f032
BW		 470
471#ifdef CONFIG_PM
f556309e
MF		 472
473static unsigned short wakeup_map[GPIO_BANK_NUM];
474static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
475
476static const unsigned int sic_iwr_irqs[] = {
477#if defined(BF533_FAMILY)
478 IRQ_PROG_INTB
479#elif defined(BF537_FAMILY)
480 IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX
481#elif defined(BF538_FAMILY)
482 IRQ_PORTF_INTB
269647dc 483#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e
MF		 484 IRQ_PORTF_INTB, IRQ_PORTG_INTB, IRQ_PORTH_INTB
485#elif defined(BF561_FAMILY)
486 IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB
487#else
488# error no SIC_IWR defined
489#endif
490};
491
1394f032
BW		 492/***********************************************************
493*
494* FUNCTIONS: Blackfin PM Setup API
495*
496* INPUTS/OUTPUTS:
497* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
498* type -
499* PM_WAKE_RISING
500* PM_WAKE_FALLING
501* PM_WAKE_HIGH
502* PM_WAKE_LOW
503* PM_WAKE_BOTH_EDGES
504*
505* DESCRIPTION: Blackfin PM Driver API
506*
507* CAUTION:
508*************************************************************
509* MODIFICATION HISTORY :
510**************************************************************/
a2c8cfef 511int gpio_pm_wakeup_request(unsigned gpio, unsigned char type)
1394f032
BW		 512{
513 unsigned long flags;
514
515 if ((check_gpio(gpio) < 0) || !type)
516 return -EINVAL;
517
6a01f230 518 local_irq_save_hw(flags);
1394f032
BW		 519 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
520 wakeup_flags_map[gpio] = type;
6a01f230 521 local_irq_restore_hw(flags);
1394f032
BW		 522
523 return 0;
524}
525EXPORT_SYMBOL(gpio_pm_wakeup_request);
526
a2c8cfef 527void gpio_pm_wakeup_free(unsigned gpio)
1394f032
BW		 528{
529 unsigned long flags;
530
531 if (check_gpio(gpio) < 0)
532 return;
533
6a01f230 534 local_irq_save_hw(flags);
1394f032
BW		 535
536 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
537
6a01f230 538 local_irq_restore_hw(flags);
1394f032
BW		 539}
540EXPORT_SYMBOL(gpio_pm_wakeup_free);
541
a2c8cfef 542static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
1394f032
BW		 543{
544 port_setup(gpio, GPIO_USAGE);
545 set_gpio_dir(gpio, 0);
546 set_gpio_inen(gpio, 1);
547
548 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
549 set_gpio_edge(gpio, 1);
550 else
551 set_gpio_edge(gpio, 0);
552
553 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
554 set_gpio_both(gpio, 1);
555 else
556 set_gpio_both(gpio, 0);
557
558 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
559 set_gpio_polar(gpio, 1);
560 else
561 set_gpio_polar(gpio, 0);
562
563 SSYNC();
564
565 return 0;
566}
567
1efc80b5 568u32 bfin_pm_standby_setup(void)
1394f032 569{
1394f032
BW		 570 u16 bank, mask, i, gpio;
571
1f83b8f1 572 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 573 mask = wakeup_map[gpio_bank(i)];
574 bank = gpio_bank(i);
575
f556309e
MF		 576 gpio_bank_saved[bank].maskb = gpio_array[bank]->maskb;
577 gpio_array[bank]->maskb = 0;
1394f032
BW		 578
579 if (mask) {
269647dc 580#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
1394f032
BW		 581 gpio_bank_saved[bank].fer = *port_fer[bank];
582#endif
f556309e
MF		 583 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
584 gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
585 gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
586 gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
587 gpio_bank_saved[bank].both = gpio_array[bank]->both;
c58c2140
MH		 588 gpio_bank_saved[bank].reserved =
589 reserved_gpio_map[bank];
1394f032
BW		 590
591 gpio = i;
592
593 while (mask) {
cfefe3c6
MH		 594 if ((mask & 1) && (wakeup_flags_map[gpio] !=
595 PM_WAKE_IGNORE)) {
c58c2140 596 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH		 597 gpio_bit(gpio);
598 bfin_gpio_wakeup_type(gpio,
599 wakeup_flags_map[gpio]);
1394f032
BW		 600 set_gpio_data(gpio, 0); /*Clear*/
601 }
602 gpio++;
603 mask >>= 1;
604 }
605
cfefe3c6 606 bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
f556309e 607 gpio_array[bank]->maskb_set = wakeup_map[gpio_bank(i)];
1394f032
BW		 608 }
609 }
610
2b39331a
MH		 611 AWA_DUMMY_READ(maskb_set);
612
cfefe3c6 613 return 0;
1394f032
BW		 614}
615
1efc80b5 616void bfin_pm_standby_restore(void)
1394f032
BW		 617{
618 u16 bank, mask, i;
619
1f83b8f1 620 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 621 mask = wakeup_map[gpio_bank(i)];
622 bank = gpio_bank(i);
623
624 if (mask) {
269647dc 625#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
1394f032
BW		 626 *port_fer[bank] = gpio_bank_saved[bank].fer;
627#endif
f556309e
MF		 628 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
629 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
630 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
631 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
632 gpio_array[bank]->both = gpio_bank_saved[bank].both;
581d62ab 633
c58c2140
MH		 634 reserved_gpio_map[bank] =
635 gpio_bank_saved[bank].reserved;
cfefe3c6 636 bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
1394f032
BW		 637 }
638
f556309e 639 gpio_array[bank]->maskb = gpio_bank_saved[bank].maskb;
1394f032 640 }
2b39331a 641 AWA_DUMMY_READ(maskb);
1394f032
BW		 642}
643
1efc80b5
MH		 644void bfin_gpio_pm_hibernate_suspend(void)
645{
646 int i, bank;
647
648 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
649 bank = gpio_bank(i);
650
269647dc 651#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
f556309e 652 gpio_bank_saved[bank].fer = *port_fer[bank];
269647dc 653#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 654 gpio_bank_saved[bank].mux = *port_mux[bank];
1efc80b5 655#else
f556309e
MF		 656 if (bank == 0)
657 gpio_bank_saved[bank].mux = bfin_read_PORT_MUX();
1efc80b5
MH		 658#endif
659#endif
f556309e
MF		 660 gpio_bank_saved[bank].data = gpio_array[bank]->data;
661 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
662 gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
663 gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
664 gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
665 gpio_bank_saved[bank].both = gpio_array[bank]->both;
666 gpio_bank_saved[bank].maska = gpio_array[bank]->maska;
1efc80b5
MH		 667 }
668
669 AWA_DUMMY_READ(maska);
670}
671
672void bfin_gpio_pm_hibernate_restore(void)
673{
674 int i, bank;
675
676 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
f556309e 677 bank = gpio_bank(i);
1efc80b5 678
269647dc
MF		 679#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
680#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
f556309e 681 *port_mux[bank] = gpio_bank_saved[bank].mux;
1efc80b5 682#else
f556309e
MF		 683 if (bank == 0)
684 bfin_write_PORT_MUX(gpio_bank_saved[bank].mux);
1efc80b5 685#endif
f556309e 686 *port_fer[bank] = gpio_bank_saved[bank].fer;
1efc80b5 687#endif
f556309e 688 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
c03c2a87
MH		 689 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
690 & gpio_bank_saved[bank].dir;
f556309e
MF		 691 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
692 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
693 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
694 gpio_array[bank]->both = gpio_bank_saved[bank].both;
f556309e 695 gpio_array[bank]->maska = gpio_bank_saved[bank].maska;
1efc80b5
MH		 696 }
697 AWA_DUMMY_READ(maska);
698}
699
700
1394f032 701#endif
269647dc 702#else /* CONFIG_BF54x */
1efc80b5
MH		 703#ifdef CONFIG_PM
704
705u32 bfin_pm_standby_setup(void)
706{
707 return 0;
708}
709
710void bfin_pm_standby_restore(void)
711{
712
713}
714
715void bfin_gpio_pm_hibernate_suspend(void)
716{
717 int i, bank;
718
719 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
720 bank = gpio_bank(i);
721
f556309e
MF		 722 gpio_bank_saved[bank].fer = gpio_array[bank]->port_fer;
723 gpio_bank_saved[bank].mux = gpio_array[bank]->port_mux;
724 gpio_bank_saved[bank].data = gpio_array[bank]->data;
f556309e
MF		 725 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
726 gpio_bank_saved[bank].dir = gpio_array[bank]->dir_set;
1efc80b5
MH		 727 }
728}
729
730void bfin_gpio_pm_hibernate_restore(void)
731{
732 int i, bank;
733
734 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
f556309e
MF		 735 bank = gpio_bank(i);
736
737 gpio_array[bank]->port_mux = gpio_bank_saved[bank].mux;
738 gpio_array[bank]->port_fer = gpio_bank_saved[bank].fer;
739 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
740 gpio_array[bank]->dir_set = gpio_bank_saved[bank].dir;
741 gpio_array[bank]->data_set = gpio_bank_saved[bank].data
742 | gpio_bank_saved[bank].dir;
1efc80b5
MH		 743 }
744}
745#endif
fac3cf43 746
a2c8cfef 747unsigned short get_gpio_dir(unsigned gpio)
fac3cf43 748{
f556309e 749 return (0x01 & (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)));
fac3cf43
MH		 750}
751EXPORT_SYMBOL(get_gpio_dir);
752
269647dc 753#endif /* CONFIG_BF54x */
1394f032 754
d2b11a46
MH		 755/***********************************************************
756*
757* FUNCTIONS: Blackfin Peripheral Resource Allocation
758* and PortMux Setup
759*
760* INPUTS/OUTPUTS:
761* per Peripheral Identifier
762* label String
763*
764* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
765*
766* CAUTION:
767*************************************************************
768* MODIFICATION HISTORY :
769**************************************************************/
770
d2b11a46
MH		 771int peripheral_request(unsigned short per, const char *label)
772{
773 unsigned long flags;
774 unsigned short ident = P_IDENT(per);
775
776 /*
777 * Don't cares are pins with only one dedicated function
778 */
c58c2140 779
d2b11a46
MH		 780 if (per & P_DONTCARE)
781 return 0;
782
783 if (!(per & P_DEFINED))
784 return -ENODEV;
785
6a01f230 786 local_irq_save_hw(flags);
d2b11a46 787
6a87d29b
MF		 788 /* If a pin can be muxed as either GPIO or peripheral, make
789 * sure it is not already a GPIO pin when we request it.
790 */
791 if (unlikely(!check_gpio(ident) &&
792 reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
d6879c58
RG		 793 if (system_state == SYSTEM_BOOTING)
794 dump_stack();
d2b11a46 795 printk(KERN_ERR
6c7ec0ec 796 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
b85d858b 797 __func__, ident, get_label(ident));
6a01f230 798 local_irq_restore_hw(flags);
d2b11a46
MH		 799 return -EBUSY;
800 }
801
802 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
803
d171c233
MF		 804 /*
805 * Pin functions like AMC address strobes my
806 * be requested and used by several drivers
807 */
d2b11a46 808
269647dc 809#ifdef CONFIG_BF54x
f556309e 810 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
6c7ec0ec
MF		 811#else
812 if (!(per & P_MAYSHARE)) {
813#endif
d171c233
MF		 814 /*
815 * Allow that the identical pin function can
816 * be requested from the same driver twice
817 */
d2b11a46 818
d171c233
MF		 819 if (cmp_label(ident, label) == 0)
820 goto anyway;
d2b11a46 821
d6879c58
RG		 822 if (system_state == SYSTEM_BOOTING)
823 dump_stack();
d2b11a46
MH		 824 printk(KERN_ERR
825 "%s: Peripheral %d function %d is already reserved by %s !\n",
b85d858b 826 __func__, ident, P_FUNCT2MUX(per), get_label(ident));
6a01f230 827 local_irq_restore_hw(flags);
d2b11a46
MH		 828 return -EBUSY;
829 }
830 }
831
d171c233 832 anyway:
d2b11a46
MH		 833 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
834
f556309e 835 portmux_setup(per);
c58c2140
MH		 836 port_setup(ident, PERIPHERAL_USAGE);
837
6a01f230 838 local_irq_restore_hw(flags);
c58c2140
MH		 839 set_label(ident, label);
840
841 return 0;
842}
843EXPORT_SYMBOL(peripheral_request);
844
68179371 845int peripheral_request_list(const unsigned short per[], const char *label)
c58c2140
MH		 846{
847 u16 cnt;
848 int ret;
849
850 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 851
c58c2140 852 ret = peripheral_request(per[cnt], label);
314c98d5
MH		 853
854 if (ret < 0) {
d171c233 855 for ( ; cnt > 0; cnt--)
314c98d5 856 peripheral_free(per[cnt - 1]);
d171c233
MF		 857
858 return ret;
314c98d5 859 }
c58c2140
MH		 860 }
861
862 return 0;
863}
864EXPORT_SYMBOL(peripheral_request_list);
865
866void peripheral_free(unsigned short per)
867{
868 unsigned long flags;
869 unsigned short ident = P_IDENT(per);
870
871 if (per & P_DONTCARE)
872 return;
873
874 if (!(per & P_DEFINED))
875 return;
876
6a01f230 877 local_irq_save_hw(flags);
c58c2140 878
d171c233 879 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
6a01f230 880 local_irq_restore_hw(flags);
c58c2140
MH		 881 return;
882 }
883
d171c233 884 if (!(per & P_MAYSHARE))
c58c2140 885 port_setup(ident, GPIO_USAGE);
c58c2140
MH		 886
887 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
888
2acde902
MH		 889 set_label(ident, "free");
890
6a01f230 891 local_irq_restore_hw(flags);
c58c2140
MH		 892}
893EXPORT_SYMBOL(peripheral_free);
894
68179371 895void peripheral_free_list(const unsigned short per[])
c58c2140
MH		 896{
897 u16 cnt;
d171c233 898 for (cnt = 0; per[cnt] != 0; cnt++)
c58c2140 899 peripheral_free(per[cnt]);
c58c2140
MH		 900}
901EXPORT_SYMBOL(peripheral_free_list);
902
1394f032
BW		 903/***********************************************************
904*
905* FUNCTIONS: Blackfin GPIO Driver
906*
907* INPUTS/OUTPUTS:
d2b11a46
MH		 908* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
909* label String
1394f032
BW		 910*
911* DESCRIPTION: Blackfin GPIO Driver API
912*
913* CAUTION:
914*************************************************************
915* MODIFICATION HISTORY :
916**************************************************************/
917
a4f0b32c 918int bfin_gpio_request(unsigned gpio, const char *label)
1394f032
BW		 919{
920 unsigned long flags;
921
922 if (check_gpio(gpio) < 0)
923 return -EINVAL;
924
6a01f230 925 local_irq_save_hw(flags);
1394f032 926
2acde902
MH		 927 /*
928 * Allow that the identical GPIO can
929 * be requested from the same driver twice
930 * Do nothing and return -
931 */
932
933 if (cmp_label(gpio, label) == 0) {
6a01f230 934 local_irq_restore_hw(flags);
2acde902
MH		 935 return 0;
936 }
937
c58c2140 938 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
d6879c58
RG		 939 if (system_state == SYSTEM_BOOTING)
940 dump_stack();
d2b11a46 941 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
9570ff4a 942 gpio, get_label(gpio));
6a01f230 943 local_irq_restore_hw(flags);
d2b11a46
MH		 944 return -EBUSY;
945 }
946 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
d6879c58
RG		 947 if (system_state == SYSTEM_BOOTING)
948 dump_stack();
d2b11a46
MH		 949 printk(KERN_ERR
950 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
951 gpio, get_label(gpio));
6a01f230 952 local_irq_restore_hw(flags);
1394f032
BW		 953 return -EBUSY;
954 }
a2be3931 955 if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
9570ff4a
GY		 956 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
957 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
a2be3931 958 }
269647dc 959#ifndef CONFIG_BF54x
a2be3931
MH		 960 else { /* Reset POLAR setting when acquiring a gpio for the first time */
961 set_gpio_polar(gpio, 0);
962 }
963#endif
d2b11a46 964
c58c2140 965 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
9570ff4a 966 set_label(gpio, label);
1394f032 967
6a01f230 968 local_irq_restore_hw(flags);
1394f032
BW		 969
970 port_setup(gpio, GPIO_USAGE);
971
972 return 0;
973}
a4f0b32c 974EXPORT_SYMBOL(bfin_gpio_request);
1394f032 975
a4f0b32c 976void bfin_gpio_free(unsigned gpio)
1394f032
BW		 977{
978 unsigned long flags;
979
980 if (check_gpio(gpio) < 0)
981 return;
982
45c4f2a0
UKK		 983 might_sleep();
984
6a01f230 985 local_irq_save_hw(flags);
1394f032 986
c58c2140 987 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
d6879c58
RG		 988 if (system_state == SYSTEM_BOOTING)
989 dump_stack();
f85c4abd 990 gpio_error(gpio);
6a01f230 991 local_irq_restore_hw(flags);
1394f032
BW		 992 return;
993 }
994
c58c2140 995 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032 996
2acde902
MH		 997 set_label(gpio, "free");
998
6a01f230 999 local_irq_restore_hw(flags);
1394f032 1000}
a4f0b32c 1001EXPORT_SYMBOL(bfin_gpio_free);
1394f032 1002
9570ff4a
GY		 1003int bfin_gpio_irq_request(unsigned gpio, const char *label)
1004{
1005 unsigned long flags;
1006
1007 if (check_gpio(gpio) < 0)
1008 return -EINVAL;
1009
6a01f230 1010 local_irq_save_hw(flags);
9570ff4a 1011
9570ff4a 1012 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
d6879c58
RG		 1013 if (system_state == SYSTEM_BOOTING)
1014 dump_stack();
9570ff4a
GY		 1015 printk(KERN_ERR
1016 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1017 gpio, get_label(gpio));
6a01f230 1018 local_irq_restore_hw(flags);
9570ff4a
GY		 1019 return -EBUSY;
1020 }
1021 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))
1022 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
1023 "(Documentation/blackfin/bfin-gpio-notes.txt)\n",
1024 gpio, get_label(gpio));
1025
1026 reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1027 set_label(gpio, label);
1028
6a01f230 1029 local_irq_restore_hw(flags);
9570ff4a
GY		 1030
1031 port_setup(gpio, GPIO_USAGE);
1032
1033 return 0;
1034}
1035
1036void bfin_gpio_irq_free(unsigned gpio)
1037{
1038 unsigned long flags;
1039
1040 if (check_gpio(gpio) < 0)
1041 return;
1042
6a01f230 1043 local_irq_save_hw(flags);
9570ff4a
GY		 1044
1045 if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
d6879c58
RG		 1046 if (system_state == SYSTEM_BOOTING)
1047 dump_stack();
9570ff4a 1048 gpio_error(gpio);
6a01f230 1049 local_irq_restore_hw(flags);
9570ff4a
GY		 1050 return;
1051 }
1052
1053 reserved_gpio_irq_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1054
1055 set_label(gpio, "free");
1056
6a01f230 1057 local_irq_restore_hw(flags);
9570ff4a
GY		 1058}
1059
f556309e
MF		 1060static inline void __bfin_gpio_direction_input(unsigned gpio)
1061{
269647dc 1062#ifdef CONFIG_BF54x
f556309e
MF		 1063 gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
1064#else
1065 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1066#endif
1067 gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
1068}
1069
a4f0b32c 1070int bfin_gpio_direction_input(unsigned gpio)
d2b11a46
MH		 1071{
1072 unsigned long flags;
1073
acbcd263
MH		 1074 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1075 gpio_error(gpio);
1076 return -EINVAL;
1077 }
1078
6a01f230 1079 local_irq_save_hw(flags);
f556309e
MF		 1080 __bfin_gpio_direction_input(gpio);
1081 AWA_DUMMY_READ(inen);
6a01f230 1082 local_irq_restore_hw(flags);
acbcd263
MH		 1083
1084 return 0;
d2b11a46 1085}
a4f0b32c 1086EXPORT_SYMBOL(bfin_gpio_direction_input);
d2b11a46 1087
f556309e 1088void bfin_gpio_irq_prepare(unsigned gpio)
d2b11a46 1089{
269647dc 1090#ifdef CONFIG_BF54x
d2b11a46 1091 unsigned long flags;
f556309e 1092#endif
d2b11a46 1093
f556309e 1094 port_setup(gpio, GPIO_USAGE);
d2b11a46 1095
269647dc 1096#ifdef CONFIG_BF54x
6a01f230 1097 local_irq_save_hw(flags);
f556309e 1098 __bfin_gpio_direction_input(gpio);
6a01f230 1099 local_irq_restore_hw(flags);
f556309e 1100#endif
d2b11a46 1101}
d2b11a46 1102
a4f0b32c 1103void bfin_gpio_set_value(unsigned gpio, int arg)
d2b11a46
MH		 1104{
1105 if (arg)
f556309e 1106 gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
d2b11a46 1107 else
f556309e 1108 gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
d2b11a46 1109}
a4f0b32c 1110EXPORT_SYMBOL(bfin_gpio_set_value);
d2b11a46 1111
f556309e 1112int bfin_gpio_direction_output(unsigned gpio, int value)
affee2b2
MH		 1113{
1114 unsigned long flags;
1115
f556309e
MF		 1116 if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1117 gpio_error(gpio);
1118 return -EINVAL;
1119 }
affee2b2 1120
6a01f230 1121 local_irq_save_hw(flags);
affee2b2 1122
f556309e
MF		 1123 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1124 gpio_set_value(gpio, value);
269647dc 1125#ifdef CONFIG_BF54x
f556309e 1126 gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
d2b11a46 1127#else
f556309e
MF		 1128 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
1129#endif
1130
1131 AWA_DUMMY_READ(dir);
1132 local_irq_restore_hw(flags);
1133
1134 return 0;
1135}
1136EXPORT_SYMBOL(bfin_gpio_direction_output);
d2b11a46 1137
a4f0b32c 1138int bfin_gpio_get_value(unsigned gpio)
803a8d2a 1139{
269647dc 1140#ifdef CONFIG_BF54x
f556309e
MF		 1141 return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
1142#else
803a8d2a 1143 unsigned long flags;
803a8d2a
MH		 1144
1145 if (unlikely(get_gpio_edge(gpio))) {
f556309e 1146 int ret;
6a01f230 1147 local_irq_save_hw(flags);
803a8d2a
MH		 1148 set_gpio_edge(gpio, 0);
1149 ret = get_gpio_data(gpio);
1150 set_gpio_edge(gpio, 1);
6a01f230 1151 local_irq_restore_hw(flags);
803a8d2a
MH		 1152 return ret;
1153 } else
1154 return get_gpio_data(gpio);
f556309e 1155#endif
803a8d2a 1156}
a4f0b32c 1157EXPORT_SYMBOL(bfin_gpio_get_value);
803a8d2a 1158
168f1212
MF		 1159/* If we are booting from SPI and our board lacks a strong enough pull up,
1160 * the core can reset and execute the bootrom faster than the resistor can
1161 * pull the signal logically high. To work around this (common) error in
1162 * board design, we explicitly set the pin back to GPIO mode, force /CS
1163 * high, and wait for the electrons to do their thing.
1164 *
1165 * This function only makes sense to be called from reset code, but it
1166 * lives here as we need to force all the GPIO states w/out going through
1167 * BUG() checks and such.
1168 */
b52dae31 1169void bfin_reset_boot_spi_cs(unsigned short pin)
168f1212 1170{
b52dae31 1171 unsigned short gpio = P_IDENT(pin);
4d5f4ed3 1172 port_setup(gpio, GPIO_USAGE);
f556309e 1173 gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
a2c8cfef 1174 AWA_DUMMY_READ(data_set);
168f1212
MF		 1175 udelay(1);
1176}
d2b11a46 1177
1545a111
MF		 1178#if defined(CONFIG_PROC_FS)
1179static int gpio_proc_read(char *buf, char **start, off_t offset,
1180 int len, int *unused_i, void *unused_v)
1181{
9570ff4a 1182 int c, irq, gpio, outlen = 0;
1545a111
MF		 1183
1184 for (c = 0; c < MAX_RESOURCES; c++) {
9570ff4a
GY		 1185 irq = reserved_gpio_irq_map[gpio_bank(c)] & gpio_bit(c);
1186 gpio = reserved_gpio_map[gpio_bank(c)] & gpio_bit(c);
1187 if (!check_gpio(c) && (gpio || irq))
1188 len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
1189 get_label(c), (gpio && irq) ? " *" : "",
1190 get_gpio_dir(c) ? "OUTPUT" : "INPUT");
1545a111 1191 else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
8eb3e3bf 1192 len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
1545a111
MF		 1193 else
1194 continue;
1195 buf += len;
1196 outlen += len;
1197 }
1198 return outlen;
1199}
1200
1201static __init int gpio_register_proc(void)
1202{
1203 struct proc_dir_entry *proc_gpio;
1204
1205 proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
1206 if (proc_gpio)
1207 proc_gpio->read_proc = gpio_proc_read;
1208 return proc_gpio != NULL;
1209}
1545a111
MF		 1210__initcall(gpio_register_proc);
1211#endif
a4f0b32c
MH		 1212
1213#ifdef CONFIG_GPIOLIB
1214int bfin_gpiolib_direction_input(struct gpio_chip *chip, unsigned gpio)
1215{
1216 return bfin_gpio_direction_input(gpio);
1217}
1218
1219int bfin_gpiolib_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
1220{
1221 return bfin_gpio_direction_output(gpio, level);
1222}
1223
1224int bfin_gpiolib_get_value(struct gpio_chip *chip, unsigned gpio)
1225{
1226 return bfin_gpio_get_value(gpio);
1227}
1228
1229void bfin_gpiolib_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1230{
a4f0b32c 1231 return bfin_gpio_set_value(gpio, value);
a4f0b32c
MH		 1232}
1233
1234int bfin_gpiolib_gpio_request(struct gpio_chip *chip, unsigned gpio)
1235{
1236 return bfin_gpio_request(gpio, chip->label);
1237}
1238
1239void bfin_gpiolib_gpio_free(struct gpio_chip *chip, unsigned gpio)
1240{
1241 return bfin_gpio_free(gpio);
1242}
1243
1244static struct gpio_chip bfin_chip = {
1245 .label = "Blackfin-GPIOlib",
1246 .direction_input = bfin_gpiolib_direction_input,
1247 .get = bfin_gpiolib_get_value,
1248 .direction_output = bfin_gpiolib_direction_output,
1249 .set = bfin_gpiolib_set_value,
1250 .request = bfin_gpiolib_gpio_request,
1251 .free = bfin_gpiolib_gpio_free,
1252 .base = 0,
1253 .ngpio = MAX_BLACKFIN_GPIOS,
1254};
1255
1256static int __init bfin_gpiolib_setup(void)
1257{
1258 return gpiochip_add(&bfin_chip);
1259}
1260arch_initcall(bfin_gpiolib_setup);
1261#endif
Linux kernel - Deliverables
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