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Blackfin arch: For compatibility reasons change IRQ_XXX_ERR into IRQ_XXX_ERROR like...
[deliverable/linux.git] / arch / blackfin / kernel / bfin_gpio.c
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1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/bfin_gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
d2b11a46 10 * Copyright 2007 Analog Devices Inc.
1394f032
BW		 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
d2b11a46 31* Number BF537/6/4 BF561 BF533/2/1 BF549/8/4/2
1394f032 32*
d2b11a46 33* GPIO_0 PF0 PF0 PF0 PA0...PJ13
1394f032
BW		 34* GPIO_1 PF1 PF1 PF1
35* GPIO_2 PF2 PF2 PF2
36* GPIO_3 PF3 PF3 PF3
37* GPIO_4 PF4 PF4 PF4
38* GPIO_5 PF5 PF5 PF5
39* GPIO_6 PF6 PF6 PF6
40* GPIO_7 PF7 PF7 PF7
41* GPIO_8 PF8 PF8 PF8
42* GPIO_9 PF9 PF9 PF9
43* GPIO_10 PF10 PF10 PF10
44* GPIO_11 PF11 PF11 PF11
45* GPIO_12 PF12 PF12 PF12
46* GPIO_13 PF13 PF13 PF13
47* GPIO_14 PF14 PF14 PF14
48* GPIO_15 PF15 PF15 PF15
49* GPIO_16 PG0 PF16
50* GPIO_17 PG1 PF17
51* GPIO_18 PG2 PF18
52* GPIO_19 PG3 PF19
53* GPIO_20 PG4 PF20
54* GPIO_21 PG5 PF21
55* GPIO_22 PG6 PF22
56* GPIO_23 PG7 PF23
57* GPIO_24 PG8 PF24
58* GPIO_25 PG9 PF25
59* GPIO_26 PG10 PF26
60* GPIO_27 PG11 PF27
61* GPIO_28 PG12 PF28
62* GPIO_29 PG13 PF29
63* GPIO_30 PG14 PF30
64* GPIO_31 PG15 PF31
65* GPIO_32 PH0 PF32
66* GPIO_33 PH1 PF33
67* GPIO_34 PH2 PF34
68* GPIO_35 PH3 PF35
69* GPIO_36 PH4 PF36
70* GPIO_37 PH5 PF37
71* GPIO_38 PH6 PF38
72* GPIO_39 PH7 PF39
73* GPIO_40 PH8 PF40
74* GPIO_41 PH9 PF41
75* GPIO_42 PH10 PF42
76* GPIO_43 PH11 PF43
77* GPIO_44 PH12 PF44
78* GPIO_45 PH13 PF45
79* GPIO_46 PH14 PF46
80* GPIO_47 PH15 PF47
81*/
82
168f1212 83#include <linux/delay.h>
1394f032
BW		 84#include <linux/module.h>
85#include <linux/err.h>
86#include <asm/blackfin.h>
87#include <asm/gpio.h>
c58c2140 88#include <asm/portmux.h>
1394f032
BW		 89#include <linux/irq.h>
90
91#ifdef BF533_FAMILY
92static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
93 (struct gpio_port_t *) FIO_FLAG_D,
94};
95#endif
96
97#ifdef BF537_FAMILY
98static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
99 (struct gpio_port_t *) PORTFIO,
100 (struct gpio_port_t *) PORTGIO,
101 (struct gpio_port_t *) PORTHIO,
102};
103
104static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
105 (unsigned short *) PORTF_FER,
106 (unsigned short *) PORTG_FER,
107 (unsigned short *) PORTH_FER,
108};
109
110#endif
111
112#ifdef BF561_FAMILY
113static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
114 (struct gpio_port_t *) FIO0_FLAG_D,
115 (struct gpio_port_t *) FIO1_FLAG_D,
116 (struct gpio_port_t *) FIO2_FLAG_D,
117};
118#endif
119
d2b11a46
MH		 120#ifdef BF548_FAMILY
121static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
122 (struct gpio_port_t *)PORTA_FER,
123 (struct gpio_port_t *)PORTB_FER,
124 (struct gpio_port_t *)PORTC_FER,
125 (struct gpio_port_t *)PORTD_FER,
126 (struct gpio_port_t *)PORTE_FER,
127 (struct gpio_port_t *)PORTF_FER,
128 (struct gpio_port_t *)PORTG_FER,
129 (struct gpio_port_t *)PORTH_FER,
130 (struct gpio_port_t *)PORTI_FER,
131 (struct gpio_port_t *)PORTJ_FER,
132};
133#endif
134
c58c2140
MH		 135static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
136static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS + 16)];
c58c2140 137
8c613623
MH		 138#define MAX_RESOURCES 256
139#define RESOURCE_LABEL_SIZE 16
140
141struct str_ident {
142 char name[RESOURCE_LABEL_SIZE];
143} *str_ident;
144
1394f032
BW		 145
146#ifdef CONFIG_PM
147static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
148static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
149static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
150
151#ifdef BF533_FAMILY
152static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB};
153#endif
154
155#ifdef BF537_FAMILY
156static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
157#endif
158
159#ifdef BF561_FAMILY
160static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
161#endif
162
163#endif /* CONFIG_PM */
164
d2b11a46
MH		 165#if defined(BF548_FAMILY)
166inline int check_gpio(unsigned short gpio)
167{
168 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
169 || gpio == GPIO_PH14 || gpio == GPIO_PH15
170 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
171 || gpio > MAX_BLACKFIN_GPIOS)
172 return -EINVAL;
173 return 0;
174}
175#else
1394f032
BW		 176inline int check_gpio(unsigned short gpio)
177{
e7613aab 178 if (gpio >= MAX_BLACKFIN_GPIOS)
1394f032
BW		 179 return -EINVAL;
180 return 0;
181}
d2b11a46 182#endif
1394f032 183
c58c2140
MH		 184static void set_label(unsigned short ident, const char *label)
185{
186
187 if (label && str_ident) {
8c613623 188 strncpy(str_ident[ident].name, label,
c58c2140 189 RESOURCE_LABEL_SIZE);
8c613623 190 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH		 191 }
192}
193
194static char *get_label(unsigned short ident)
195{
196 if (!str_ident)
197 return "UNKNOWN";
198
8c613623 199 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH		 200}
201
202static int cmp_label(unsigned short ident, const char *label)
203{
204 if (label && str_ident)
8c613623 205 return strncmp(str_ident[ident].name,
c58c2140
MH		 206 label, strlen(label));
207 else
208 return -EINVAL;
209}
210
1394f032 211#ifdef BF537_FAMILY
a161bb05 212static void port_setup(unsigned short gpio, unsigned short usage)
1394f032 213{
cda6a20b 214 if (!check_gpio(gpio)) {
d2b11a46 215 if (usage == GPIO_USAGE)
cda6a20b 216 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
d2b11a46 217 else
cda6a20b
MH		 218 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
219 SSYNC();
220 }
1394f032 221}
d2b11a46
MH		 222#elif defined(BF548_FAMILY)
223static void port_setup(unsigned short gpio, unsigned short usage)
224{
225 if (usage == GPIO_USAGE)
226 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
227 else
228 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
229 SSYNC();
230}
1394f032
BW		 231#else
232# define port_setup(...) do { } while (0)
233#endif
234
c58c2140 235#ifdef BF537_FAMILY
8c613623
MH		 236static struct {
237 unsigned short res;
238 unsigned short offset;
239} port_mux_lut[] = {
240 {.res = P_PPI0_D13, .offset = 11},
241 {.res = P_PPI0_D14, .offset = 11},
242 {.res = P_PPI0_D15, .offset = 11},
243 {.res = P_SPORT1_TFS, .offset = 11},
244 {.res = P_SPORT1_TSCLK, .offset = 11},
245 {.res = P_SPORT1_DTPRI, .offset = 11},
246 {.res = P_PPI0_D10, .offset = 10},
247 {.res = P_PPI0_D11, .offset = 10},
248 {.res = P_PPI0_D12, .offset = 10},
249 {.res = P_SPORT1_RSCLK, .offset = 10},
250 {.res = P_SPORT1_RFS, .offset = 10},
251 {.res = P_SPORT1_DRPRI, .offset = 10},
252 {.res = P_PPI0_D8, .offset = 9},
253 {.res = P_PPI0_D9, .offset = 9},
254 {.res = P_SPORT1_DRSEC, .offset = 9},
255 {.res = P_SPORT1_DTSEC, .offset = 9},
256 {.res = P_TMR2, .offset = 8},
257 {.res = P_PPI0_FS3, .offset = 8},
258 {.res = P_TMR3, .offset = 7},
259 {.res = P_SPI0_SSEL4, .offset = 7},
260 {.res = P_TMR4, .offset = 6},
261 {.res = P_SPI0_SSEL5, .offset = 6},
262 {.res = P_TMR5, .offset = 5},
263 {.res = P_SPI0_SSEL6, .offset = 5},
264 {.res = P_UART1_RX, .offset = 4},
265 {.res = P_UART1_TX, .offset = 4},
266 {.res = P_TMR6, .offset = 4},
267 {.res = P_TMR7, .offset = 4},
268 {.res = P_UART0_RX, .offset = 3},
269 {.res = P_UART0_TX, .offset = 3},
270 {.res = P_DMAR0, .offset = 3},
271 {.res = P_DMAR1, .offset = 3},
272 {.res = P_SPORT0_DTSEC, .offset = 1},
273 {.res = P_SPORT0_DRSEC, .offset = 1},
274 {.res = P_CAN0_RX, .offset = 1},
275 {.res = P_CAN0_TX, .offset = 1},
276 {.res = P_SPI0_SSEL7, .offset = 1},
277 {.res = P_SPORT0_TFS, .offset = 0},
278 {.res = P_SPORT0_DTPRI, .offset = 0},
279 {.res = P_SPI0_SSEL2, .offset = 0},
280 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH		 281};
282
283static void portmux_setup(unsigned short per, unsigned short function)
284{
8c613623 285 u16 y, offset, muxreg;
c58c2140 286
8c613623
MH		 287 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
288 if (port_mux_lut[y].res == per) {
c58c2140
MH		 289
290 /* SET PORTMUX REG */
291
8c613623 292 offset = port_mux_lut[y].offset;
c58c2140
MH		 293 muxreg = bfin_read_PORT_MUX();
294
295 if (offset != 1) {
296 muxreg &= ~(1 << offset);
297 } else {
298 muxreg &= ~(3 << 1);
299 }
300
301 muxreg |= (function << offset);
302 bfin_write_PORT_MUX(muxreg);
303 }
304 }
305}
d2b11a46
MH		 306#elif defined(BF548_FAMILY)
307inline void portmux_setup(unsigned short portno, unsigned short function)
308{
309 u32 pmux;
310
311 pmux = gpio_array[gpio_bank(portno)]->port_mux;
312
313 pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
314 pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
315
316 gpio_array[gpio_bank(portno)]->port_mux = pmux;
317}
318
319inline u16 get_portmux(unsigned short portno)
320{
321 u32 pmux;
c58c2140 322
d2b11a46
MH		 323 pmux = gpio_array[gpio_bank(portno)]->port_mux;
324
325 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
326}
c58c2140
MH		 327#else
328# define portmux_setup(...) do { } while (0)
329#endif
1394f032 330
d2b11a46 331#ifndef BF548_FAMILY
a161bb05 332static void default_gpio(unsigned short gpio)
1394f032 333{
1f83b8f1 334 unsigned short bank, bitmask;
1394f032
BW		 335
336 bank = gpio_bank(gpio);
337 bitmask = gpio_bit(gpio);
338
339 gpio_bankb[bank]->maska_clear = bitmask;
340 gpio_bankb[bank]->maskb_clear = bitmask;
341 SSYNC();
342 gpio_bankb[bank]->inen &= ~bitmask;
343 gpio_bankb[bank]->dir &= ~bitmask;
344 gpio_bankb[bank]->polar &= ~bitmask;
345 gpio_bankb[bank]->both &= ~bitmask;
346 gpio_bankb[bank]->edge &= ~bitmask;
347}
d2b11a46
MH		 348#else
349# define default_gpio(...) do { } while (0)
350#endif
1394f032 351
a161bb05 352static int __init bfin_gpio_init(void)
1394f032 353{
8c613623
MH		 354 str_ident = kcalloc(MAX_RESOURCES,
355 sizeof(struct str_ident), GFP_KERNEL);
356 if (str_ident == NULL)
c58c2140 357 return -ENOMEM;
1394f032 358
8c613623
MH		 359 memset(str_ident, 0, MAX_RESOURCES * sizeof(struct str_ident));
360
c58c2140 361 printk(KERN_INFO "Blackfin GPIO Controller\n");
1394f032
BW		 362
363 return 0;
c58c2140 364
1394f032 365}
1394f032
BW		 366arch_initcall(bfin_gpio_init);
367
368
d2b11a46 369#ifndef BF548_FAMILY
1394f032
BW		 370/***********************************************************
371*
372* FUNCTIONS: Blackfin General Purpose Ports Access Functions
373*
374* INPUTS/OUTPUTS:
375* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
376*
377*
378* DESCRIPTION: These functions abstract direct register access
379* to Blackfin processor General Purpose
380* Ports Regsiters
381*
382* CAUTION: These functions do not belong to the GPIO Driver API
383*************************************************************
384* MODIFICATION HISTORY :
385**************************************************************/
386
387/* Set a specific bit */
388
389#define SET_GPIO(name) \
390void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
391{ \
392 unsigned long flags; \
c58c2140 393 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
1394f032
BW		 394 local_irq_save(flags); \
395 if (arg) \
396 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
397 else \
398 gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
399 local_irq_restore(flags); \
400} \
401EXPORT_SYMBOL(set_gpio_ ## name);
402
403SET_GPIO(dir)
404SET_GPIO(inen)
405SET_GPIO(polar)
406SET_GPIO(edge)
407SET_GPIO(both)
408
409
410#define SET_GPIO_SC(name) \
411void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
412{ \
c58c2140 413 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
1394f032
BW		 414 if (arg) \
415 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
416 else \
417 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
418} \
419EXPORT_SYMBOL(set_gpio_ ## name);
420
421SET_GPIO_SC(maska)
422SET_GPIO_SC(maskb)
423
1aafd909 424#if ANOMALY_05000311
1394f032
BW		 425void set_gpio_data(unsigned short gpio, unsigned short arg)
426{
427 unsigned long flags;
c58c2140 428 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 429 local_irq_save(flags);
430 if (arg)
431 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
432 else
433 gpio_bankb[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
434 bfin_read_CHIPID();
435 local_irq_restore(flags);
436}
437EXPORT_SYMBOL(set_gpio_data);
438#else
439SET_GPIO_SC(data)
440#endif
441
442
1aafd909 443#if ANOMALY_05000311
1394f032
BW		 444void set_gpio_toggle(unsigned short gpio)
445{
446 unsigned long flags;
c58c2140 447 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 448 local_irq_save(flags);
449 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
450 bfin_read_CHIPID();
451 local_irq_restore(flags);
452}
453#else
454void set_gpio_toggle(unsigned short gpio)
455{
c58c2140 456 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 457 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
458}
459#endif
460EXPORT_SYMBOL(set_gpio_toggle);
461
462
463/*Set current PORT date (16-bit word)*/
464
465#define SET_GPIO_P(name) \
466void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \
467{ \
468 gpio_bankb[gpio_bank(gpio)]->name = arg; \
469} \
470EXPORT_SYMBOL(set_gpiop_ ## name);
471
472SET_GPIO_P(dir)
473SET_GPIO_P(inen)
474SET_GPIO_P(polar)
475SET_GPIO_P(edge)
476SET_GPIO_P(both)
477SET_GPIO_P(maska)
478SET_GPIO_P(maskb)
479
480
1aafd909 481#if ANOMALY_05000311
1394f032
BW		 482void set_gpiop_data(unsigned short gpio, unsigned short arg)
483{
484 unsigned long flags;
485 local_irq_save(flags);
486 gpio_bankb[gpio_bank(gpio)]->data = arg;
487 bfin_read_CHIPID();
488 local_irq_restore(flags);
489}
490EXPORT_SYMBOL(set_gpiop_data);
491#else
492SET_GPIO_P(data)
493#endif
494
495
496
497/* Get a specific bit */
498
499#define GET_GPIO(name) \
500unsigned short get_gpio_ ## name(unsigned short gpio) \
501{ \
502 return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \
503} \
504EXPORT_SYMBOL(get_gpio_ ## name);
505
506GET_GPIO(dir)
507GET_GPIO(inen)
508GET_GPIO(polar)
509GET_GPIO(edge)
510GET_GPIO(both)
511GET_GPIO(maska)
512GET_GPIO(maskb)
513
514
1aafd909 515#if ANOMALY_05000311
1394f032
BW		 516unsigned short get_gpio_data(unsigned short gpio)
517{
518 unsigned long flags;
519 unsigned short ret;
c58c2140 520 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 521 local_irq_save(flags);
522 ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->data >> gpio_sub_n(gpio));
523 bfin_read_CHIPID();
524 local_irq_restore(flags);
525 return ret;
526}
527EXPORT_SYMBOL(get_gpio_data);
528#else
529GET_GPIO(data)
530#endif
531
532/*Get current PORT date (16-bit word)*/
533
534#define GET_GPIO_P(name) \
535unsigned short get_gpiop_ ## name(unsigned short gpio) \
536{ \
537 return (gpio_bankb[gpio_bank(gpio)]->name);\
538} \
539EXPORT_SYMBOL(get_gpiop_ ## name);
540
541GET_GPIO_P(dir)
542GET_GPIO_P(inen)
543GET_GPIO_P(polar)
544GET_GPIO_P(edge)
545GET_GPIO_P(both)
546GET_GPIO_P(maska)
547GET_GPIO_P(maskb)
548
1aafd909 549#if ANOMALY_05000311
1394f032
BW		 550unsigned short get_gpiop_data(unsigned short gpio)
551{
552 unsigned long flags;
553 unsigned short ret;
554 local_irq_save(flags);
555 ret = gpio_bankb[gpio_bank(gpio)]->data;
556 bfin_read_CHIPID();
557 local_irq_restore(flags);
558 return ret;
559}
560EXPORT_SYMBOL(get_gpiop_data);
561#else
562GET_GPIO_P(data)
563#endif
564
565#ifdef CONFIG_PM
566/***********************************************************
567*
568* FUNCTIONS: Blackfin PM Setup API
569*
570* INPUTS/OUTPUTS:
571* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
572* type -
573* PM_WAKE_RISING
574* PM_WAKE_FALLING
575* PM_WAKE_HIGH
576* PM_WAKE_LOW
577* PM_WAKE_BOTH_EDGES
578*
579* DESCRIPTION: Blackfin PM Driver API
580*
581* CAUTION:
582*************************************************************
583* MODIFICATION HISTORY :
584**************************************************************/
585int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type)
586{
587 unsigned long flags;
588
589 if ((check_gpio(gpio) < 0) || !type)
590 return -EINVAL;
591
592 local_irq_save(flags);
593
594 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
595 wakeup_flags_map[gpio] = type;
596 local_irq_restore(flags);
597
598 return 0;
599}
600EXPORT_SYMBOL(gpio_pm_wakeup_request);
601
602void gpio_pm_wakeup_free(unsigned short gpio)
603{
604 unsigned long flags;
605
606 if (check_gpio(gpio) < 0)
607 return;
608
609 local_irq_save(flags);
610
611 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
612
613 local_irq_restore(flags);
614}
615EXPORT_SYMBOL(gpio_pm_wakeup_free);
616
617static int bfin_gpio_wakeup_type(unsigned short gpio, unsigned char type)
618{
619 port_setup(gpio, GPIO_USAGE);
620 set_gpio_dir(gpio, 0);
621 set_gpio_inen(gpio, 1);
622
623 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
624 set_gpio_edge(gpio, 1);
625 else
626 set_gpio_edge(gpio, 0);
627
628 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
629 set_gpio_both(gpio, 1);
630 else
631 set_gpio_both(gpio, 0);
632
633 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
634 set_gpio_polar(gpio, 1);
635 else
636 set_gpio_polar(gpio, 0);
637
638 SSYNC();
639
640 return 0;
641}
642
643u32 gpio_pm_setup(void)
644{
645 u32 sic_iwr = 0;
646 u16 bank, mask, i, gpio;
647
1f83b8f1 648 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 649 mask = wakeup_map[gpio_bank(i)];
650 bank = gpio_bank(i);
651
652 gpio_bank_saved[bank].maskb = gpio_bankb[bank]->maskb;
653 gpio_bankb[bank]->maskb = 0;
654
655 if (mask) {
656#ifdef BF537_FAMILY
657 gpio_bank_saved[bank].fer = *port_fer[bank];
658#endif
659 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
660 gpio_bank_saved[bank].polar = gpio_bankb[bank]->polar;
661 gpio_bank_saved[bank].dir = gpio_bankb[bank]->dir;
662 gpio_bank_saved[bank].edge = gpio_bankb[bank]->edge;
663 gpio_bank_saved[bank].both = gpio_bankb[bank]->both;
c58c2140
MH		 664 gpio_bank_saved[bank].reserved =
665 reserved_gpio_map[bank];
1394f032
BW		 666
667 gpio = i;
668
669 while (mask) {
670 if (mask & 1) {
c58c2140 671 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH		 672 gpio_bit(gpio);
673 bfin_gpio_wakeup_type(gpio,
674 wakeup_flags_map[gpio]);
1394f032
BW		 675 set_gpio_data(gpio, 0); /*Clear*/
676 }
677 gpio++;
678 mask >>= 1;
679 }
680
581d62ab
MH		 681 sic_iwr |= 1 <<
682 (sic_iwr_irqs[bank] - (IRQ_CORETMR + 1));
1394f032
BW		 683 gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
684 }
685 }
686
687 if (sic_iwr)
688 return sic_iwr;
689 else
690 return IWR_ENABLE_ALL;
691}
692
1394f032
BW		 693void gpio_pm_restore(void)
694{
695 u16 bank, mask, i;
696
1f83b8f1 697 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 698 mask = wakeup_map[gpio_bank(i)];
699 bank = gpio_bank(i);
700
701 if (mask) {
702#ifdef BF537_FAMILY
703 *port_fer[bank] = gpio_bank_saved[bank].fer;
704#endif
705 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
706 gpio_bankb[bank]->dir = gpio_bank_saved[bank].dir;
707 gpio_bankb[bank]->polar = gpio_bank_saved[bank].polar;
708 gpio_bankb[bank]->edge = gpio_bank_saved[bank].edge;
709 gpio_bankb[bank]->both = gpio_bank_saved[bank].both;
581d62ab 710
c58c2140
MH		 711 reserved_gpio_map[bank] =
712 gpio_bank_saved[bank].reserved;
581d62ab 713
1394f032
BW		 714 }
715
716 gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
717 }
718}
719
720#endif
d2b11a46 721#endif /* BF548_FAMILY */
1394f032 722
d2b11a46
MH		 723/***********************************************************
724*
725* FUNCTIONS: Blackfin Peripheral Resource Allocation
726* and PortMux Setup
727*
728* INPUTS/OUTPUTS:
729* per Peripheral Identifier
730* label String
731*
732* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
733*
734* CAUTION:
735*************************************************************
736* MODIFICATION HISTORY :
737**************************************************************/
738
739#ifdef BF548_FAMILY
740int peripheral_request(unsigned short per, const char *label)
741{
742 unsigned long flags;
743 unsigned short ident = P_IDENT(per);
744
745 /*
746 * Don't cares are pins with only one dedicated function
747 */
c58c2140 748
d2b11a46
MH		 749 if (per & P_DONTCARE)
750 return 0;
751
752 if (!(per & P_DEFINED))
753 return -ENODEV;
754
755 if (check_gpio(ident) < 0)
756 return -EINVAL;
c58c2140 757
d2b11a46
MH		 758 local_irq_save(flags);
759
760 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
761 printk(KERN_ERR
762 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
763 __FUNCTION__, ident, get_label(ident));
764 dump_stack();
765 local_irq_restore(flags);
766 return -EBUSY;
767 }
768
769 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
770
771 u16 funct = get_portmux(ident);
772
773 /*
774 * Pin functions like AMC address strobes my
775 * be requested and used by several drivers
776 */
777
778 if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
779
780 /*
781 * Allow that the identical pin function can
782 * be requested from the same driver twice
783 */
784
785 if (cmp_label(ident, label) == 0)
786 goto anyway;
787
788 printk(KERN_ERR
789 "%s: Peripheral %d function %d is already reserved by %s !\n",
790 __FUNCTION__, ident, P_FUNCT2MUX(per), get_label(ident));
791 dump_stack();
792 local_irq_restore(flags);
793 return -EBUSY;
794 }
795 }
796
797anyway:
798 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
799
800 portmux_setup(ident, P_FUNCT2MUX(per));
801 port_setup(ident, PERIPHERAL_USAGE);
802
803 local_irq_restore(flags);
804 set_label(ident, label);
805
806 return 0;
807}
808EXPORT_SYMBOL(peripheral_request);
809#else
c58c2140
MH		 810
811int peripheral_request(unsigned short per, const char *label)
812{
813 unsigned long flags;
814 unsigned short ident = P_IDENT(per);
815
816 /*
817 * Don't cares are pins with only one dedicated function
818 */
819
820 if (per & P_DONTCARE)
821 return 0;
822
823 if (!(per & P_DEFINED))
824 return -ENODEV;
825
c58c2140
MH		 826 local_irq_save(flags);
827
cda6a20b
MH		 828 if (!check_gpio(ident)) {
829
c58c2140
MH		 830 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
831 printk(KERN_ERR
832 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
833 __FUNCTION__, ident, get_label(ident));
834 dump_stack();
835 local_irq_restore(flags);
836 return -EBUSY;
837 }
838
cda6a20b
MH		 839 }
840
c58c2140
MH		 841 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
842
843 /*
844 * Pin functions like AMC address strobes my
845 * be requested and used by several drivers
846 */
847
848 if (!(per & P_MAYSHARE)) {
849
850 /*
851 * Allow that the identical pin function can
852 * be requested from the same driver twice
853 */
854
855 if (cmp_label(ident, label) == 0)
856 goto anyway;
857
858 printk(KERN_ERR
859 "%s: Peripheral %d function %d is already"
8c613623 860 " reserved by %s !\n",
c58c2140
MH		 861 __FUNCTION__, ident, P_FUNCT2MUX(per),
862 get_label(ident));
863 dump_stack();
864 local_irq_restore(flags);
865 return -EBUSY;
866 }
867
868 }
869
870anyway:
c58c2140
MH		 871 portmux_setup(per, P_FUNCT2MUX(per));
872
873 port_setup(ident, PERIPHERAL_USAGE);
874
875 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
876 local_irq_restore(flags);
877 set_label(ident, label);
878
879 return 0;
880}
881EXPORT_SYMBOL(peripheral_request);
d2b11a46 882#endif
c58c2140
MH		 883
884int peripheral_request_list(unsigned short per[], const char *label)
885{
886 u16 cnt;
887 int ret;
888
889 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 890
c58c2140 891 ret = peripheral_request(per[cnt], label);
314c98d5
MH		 892
893 if (ret < 0) {
894 for ( ; cnt > 0; cnt--) {
895 peripheral_free(per[cnt - 1]);
896 }
897 return ret;
898 }
c58c2140
MH		 899 }
900
901 return 0;
902}
903EXPORT_SYMBOL(peripheral_request_list);
904
905void peripheral_free(unsigned short per)
906{
907 unsigned long flags;
908 unsigned short ident = P_IDENT(per);
909
910 if (per & P_DONTCARE)
911 return;
912
913 if (!(per & P_DEFINED))
914 return;
915
916 if (check_gpio(ident) < 0)
917 return;
918
919 local_irq_save(flags);
920
921 if (unlikely(!(reserved_peri_map[gpio_bank(ident)]
922 & gpio_bit(ident)))) {
923 local_irq_restore(flags);
924 return;
925 }
926
927 if (!(per & P_MAYSHARE)) {
928 port_setup(ident, GPIO_USAGE);
929 }
930
931 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
932
933 local_irq_restore(flags);
934}
935EXPORT_SYMBOL(peripheral_free);
936
937void peripheral_free_list(unsigned short per[])
938{
939 u16 cnt;
940
941 for (cnt = 0; per[cnt] != 0; cnt++) {
942 peripheral_free(per[cnt]);
943 }
944
945}
946EXPORT_SYMBOL(peripheral_free_list);
947
1394f032
BW		 948/***********************************************************
949*
950* FUNCTIONS: Blackfin GPIO Driver
951*
952* INPUTS/OUTPUTS:
d2b11a46
MH		 953* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
954* label String
1394f032
BW		 955*
956* DESCRIPTION: Blackfin GPIO Driver API
957*
958* CAUTION:
959*************************************************************
960* MODIFICATION HISTORY :
961**************************************************************/
962
963int gpio_request(unsigned short gpio, const char *label)
964{
965 unsigned long flags;
966
967 if (check_gpio(gpio) < 0)
968 return -EINVAL;
969
970 local_irq_save(flags);
971
c58c2140 972 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
d2b11a46
MH		 973 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
974 gpio, get_label(gpio));
975 dump_stack();
976 local_irq_restore(flags);
977 return -EBUSY;
978 }
979 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
980 printk(KERN_ERR
981 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
982 gpio, get_label(gpio));
1394f032
BW		 983 dump_stack();
984 local_irq_restore(flags);
985 return -EBUSY;
986 }
d2b11a46 987
c58c2140 988 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1394f032
BW		 989
990 local_irq_restore(flags);
991
992 port_setup(gpio, GPIO_USAGE);
d2b11a46 993 set_label(gpio, label);
1394f032
BW		 994
995 return 0;
996}
997EXPORT_SYMBOL(gpio_request);
998
1394f032
BW		 999void gpio_free(unsigned short gpio)
1000{
1001 unsigned long flags;
1002
1003 if (check_gpio(gpio) < 0)
1004 return;
1005
1006 local_irq_save(flags);
1007
c58c2140 1008 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1394f032
BW		 1009 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
1010 dump_stack();
1011 local_irq_restore(flags);
1012 return;
1013 }
1014
1015 default_gpio(gpio);
1016
c58c2140 1017 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032
BW		 1018
1019 local_irq_restore(flags);
1020}
1021EXPORT_SYMBOL(gpio_free);
1022
d2b11a46
MH		 1023#ifdef BF548_FAMILY
1024void gpio_direction_input(unsigned short gpio)
1025{
1026 unsigned long flags;
1027
1028 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1029
1030 local_irq_save(flags);
1031 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1032 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1033 local_irq_restore(flags);
1034}
1035EXPORT_SYMBOL(gpio_direction_input);
1036
1037void gpio_direction_output(unsigned short gpio)
1038{
1039 unsigned long flags;
1040
1041 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1042
1043 local_irq_save(flags);
1044 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
1045 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
1046 local_irq_restore(flags);
1047}
1048EXPORT_SYMBOL(gpio_direction_output);
1049
1050void gpio_set_value(unsigned short gpio, unsigned short arg)
1051{
1052 if (arg)
1053 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
1054 else
1055 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
1056
1057}
1058EXPORT_SYMBOL(gpio_set_value);
1059
1060unsigned short gpio_get_value(unsigned short gpio)
1061{
1062 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
1063}
1064EXPORT_SYMBOL(gpio_get_value);
1065
1066#else
1067
1394f032
BW		 1068void gpio_direction_input(unsigned short gpio)
1069{
1070 unsigned long flags;
1071
c58c2140 1072 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 1073
1074 local_irq_save(flags);
1075 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1076 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
1077 local_irq_restore(flags);
1078}
1079EXPORT_SYMBOL(gpio_direction_input);
1080
1081void gpio_direction_output(unsigned short gpio)
1082{
1083 unsigned long flags;
1084
c58c2140 1085 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 1086
1087 local_irq_save(flags);
1088 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1089 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
1090 local_irq_restore(flags);
1091}
1092EXPORT_SYMBOL(gpio_direction_output);
168f1212
MF		 1093
1094/* If we are booting from SPI and our board lacks a strong enough pull up,
1095 * the core can reset and execute the bootrom faster than the resistor can
1096 * pull the signal logically high. To work around this (common) error in
1097 * board design, we explicitly set the pin back to GPIO mode, force /CS
1098 * high, and wait for the electrons to do their thing.
1099 *
1100 * This function only makes sense to be called from reset code, but it
1101 * lives here as we need to force all the GPIO states w/out going through
1102 * BUG() checks and such.
1103 */
1104void bfin_gpio_reset_spi0_ssel1(void)
1105{
4d5f4ed3
MH		 1106 u16 gpio = P_IDENT(P_SPI0_SSEL1);
1107
1108 port_setup(gpio, GPIO_USAGE);
1109 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
168f1212
MF		 1110 udelay(1);
1111}
d2b11a46
MH		 1112
1113#endif /*BF548_FAMILY */
Linux kernel - Deliverables
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