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Merge branch 'master' of hera.kernel.org:/pub/scm/linux/kernel/git/kyle/parisc-2.6
[deliverable/linux.git] / arch / blackfin / kernel / bfin_gpio.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/bfin_gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
d2b11a46 10 * Copyright 2007 Analog Devices Inc.
1394f032
BW		 11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30/*
d2b11a46 31* Number BF537/6/4 BF561 BF533/2/1 BF549/8/4/2
1394f032 32*
d2b11a46 33* GPIO_0 PF0 PF0 PF0 PA0...PJ13
1394f032
BW		 34* GPIO_1 PF1 PF1 PF1
35* GPIO_2 PF2 PF2 PF2
36* GPIO_3 PF3 PF3 PF3
37* GPIO_4 PF4 PF4 PF4
38* GPIO_5 PF5 PF5 PF5
39* GPIO_6 PF6 PF6 PF6
40* GPIO_7 PF7 PF7 PF7
41* GPIO_8 PF8 PF8 PF8
42* GPIO_9 PF9 PF9 PF9
43* GPIO_10 PF10 PF10 PF10
44* GPIO_11 PF11 PF11 PF11
45* GPIO_12 PF12 PF12 PF12
46* GPIO_13 PF13 PF13 PF13
47* GPIO_14 PF14 PF14 PF14
48* GPIO_15 PF15 PF15 PF15
49* GPIO_16 PG0 PF16
50* GPIO_17 PG1 PF17
51* GPIO_18 PG2 PF18
52* GPIO_19 PG3 PF19
53* GPIO_20 PG4 PF20
54* GPIO_21 PG5 PF21
55* GPIO_22 PG6 PF22
56* GPIO_23 PG7 PF23
57* GPIO_24 PG8 PF24
58* GPIO_25 PG9 PF25
59* GPIO_26 PG10 PF26
60* GPIO_27 PG11 PF27
61* GPIO_28 PG12 PF28
62* GPIO_29 PG13 PF29
63* GPIO_30 PG14 PF30
64* GPIO_31 PG15 PF31
65* GPIO_32 PH0 PF32
66* GPIO_33 PH1 PF33
67* GPIO_34 PH2 PF34
68* GPIO_35 PH3 PF35
69* GPIO_36 PH4 PF36
70* GPIO_37 PH5 PF37
71* GPIO_38 PH6 PF38
72* GPIO_39 PH7 PF39
73* GPIO_40 PH8 PF40
74* GPIO_41 PH9 PF41
75* GPIO_42 PH10 PF42
76* GPIO_43 PH11 PF43
77* GPIO_44 PH12 PF44
78* GPIO_45 PH13 PF45
79* GPIO_46 PH14 PF46
80* GPIO_47 PH15 PF47
81*/
82
168f1212 83#include <linux/delay.h>
1394f032
BW		 84#include <linux/module.h>
85#include <linux/err.h>
86#include <asm/blackfin.h>
87#include <asm/gpio.h>
c58c2140 88#include <asm/portmux.h>
1394f032
BW		 89#include <linux/irq.h>
90
2b39331a
MH		 91#if ANOMALY_05000311 || ANOMALY_05000323
92enum {
93 AWA_data = SYSCR,
94 AWA_data_clear = SYSCR,
95 AWA_data_set = SYSCR,
96 AWA_toggle = SYSCR,
97 AWA_maska = UART_SCR,
98 AWA_maska_clear = UART_SCR,
99 AWA_maska_set = UART_SCR,
100 AWA_maska_toggle = UART_SCR,
101 AWA_maskb = UART_GCTL,
102 AWA_maskb_clear = UART_GCTL,
103 AWA_maskb_set = UART_GCTL,
104 AWA_maskb_toggle = UART_GCTL,
105 AWA_dir = SPORT1_STAT,
106 AWA_polar = SPORT1_STAT,
107 AWA_edge = SPORT1_STAT,
108 AWA_both = SPORT1_STAT,
109#if ANOMALY_05000311
110 AWA_inen = TIMER_ENABLE,
111#elif ANOMALY_05000323
112 AWA_inen = DMA1_1_CONFIG,
113#endif
114};
115 /* Anomaly Workaround */
116#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
117#else
118#define AWA_DUMMY_READ(...) do { } while (0)
119#endif
120
1394f032
BW		 121#ifdef BF533_FAMILY
122static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
123 (struct gpio_port_t *) FIO_FLAG_D,
124};
125#endif
126
127#ifdef BF537_FAMILY
128static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
129 (struct gpio_port_t *) PORTFIO,
130 (struct gpio_port_t *) PORTGIO,
131 (struct gpio_port_t *) PORTHIO,
132};
133
134static unsigned short *port_fer[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
135 (unsigned short *) PORTF_FER,
136 (unsigned short *) PORTG_FER,
137 (unsigned short *) PORTH_FER,
138};
139
140#endif
141
142#ifdef BF561_FAMILY
143static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
144 (struct gpio_port_t *) FIO0_FLAG_D,
145 (struct gpio_port_t *) FIO1_FLAG_D,
146 (struct gpio_port_t *) FIO2_FLAG_D,
147};
148#endif
149
d2b11a46
MH		 150#ifdef BF548_FAMILY
151static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
152 (struct gpio_port_t *)PORTA_FER,
153 (struct gpio_port_t *)PORTB_FER,
154 (struct gpio_port_t *)PORTC_FER,
155 (struct gpio_port_t *)PORTD_FER,
156 (struct gpio_port_t *)PORTE_FER,
157 (struct gpio_port_t *)PORTF_FER,
158 (struct gpio_port_t *)PORTG_FER,
159 (struct gpio_port_t *)PORTH_FER,
160 (struct gpio_port_t *)PORTI_FER,
161 (struct gpio_port_t *)PORTJ_FER,
162};
163#endif
164
c58c2140
MH		 165static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
166static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS + 16)];
c58c2140 167
8c613623
MH		 168#define MAX_RESOURCES 256
169#define RESOURCE_LABEL_SIZE 16
170
171struct str_ident {
172 char name[RESOURCE_LABEL_SIZE];
173} *str_ident;
174
1394f032
BW		 175
176#ifdef CONFIG_PM
177static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
178static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
179static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
180
181#ifdef BF533_FAMILY
182static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB};
183#endif
184
185#ifdef BF537_FAMILY
186static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX};
187#endif
188
189#ifdef BF561_FAMILY
190static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INTB, IRQ_PROG1_INTB, IRQ_PROG2_INTB};
191#endif
192
193#endif /* CONFIG_PM */
194
d2b11a46
MH		 195#if defined(BF548_FAMILY)
196inline int check_gpio(unsigned short gpio)
197{
198 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
199 || gpio == GPIO_PH14 || gpio == GPIO_PH15
200 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
201 || gpio > MAX_BLACKFIN_GPIOS)
202 return -EINVAL;
203 return 0;
204}
205#else
1394f032
BW		 206inline int check_gpio(unsigned short gpio)
207{
e7613aab 208 if (gpio >= MAX_BLACKFIN_GPIOS)
1394f032
BW		 209 return -EINVAL;
210 return 0;
211}
d2b11a46 212#endif
1394f032 213
c58c2140
MH		 214static void set_label(unsigned short ident, const char *label)
215{
216
217 if (label && str_ident) {
8c613623 218 strncpy(str_ident[ident].name, label,
c58c2140 219 RESOURCE_LABEL_SIZE);
8c613623 220 str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
c58c2140
MH		 221 }
222}
223
224static char *get_label(unsigned short ident)
225{
226 if (!str_ident)
227 return "UNKNOWN";
228
8c613623 229 return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
c58c2140
MH		 230}
231
232static int cmp_label(unsigned short ident, const char *label)
233{
234 if (label && str_ident)
8c613623 235 return strncmp(str_ident[ident].name,
c58c2140
MH		 236 label, strlen(label));
237 else
238 return -EINVAL;
239}
240
1394f032 241#ifdef BF537_FAMILY
a161bb05 242static void port_setup(unsigned short gpio, unsigned short usage)
1394f032 243{
cda6a20b 244 if (!check_gpio(gpio)) {
d2b11a46 245 if (usage == GPIO_USAGE)
cda6a20b 246 *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
d2b11a46 247 else
cda6a20b
MH		 248 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
249 SSYNC();
250 }
1394f032 251}
d2b11a46
MH		 252#elif defined(BF548_FAMILY)
253static void port_setup(unsigned short gpio, unsigned short usage)
254{
255 if (usage == GPIO_USAGE)
256 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
257 else
258 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
259 SSYNC();
260}
1394f032
BW		 261#else
262# define port_setup(...) do { } while (0)
263#endif
264
c58c2140 265#ifdef BF537_FAMILY
8c613623
MH		 266static struct {
267 unsigned short res;
268 unsigned short offset;
269} port_mux_lut[] = {
270 {.res = P_PPI0_D13, .offset = 11},
271 {.res = P_PPI0_D14, .offset = 11},
272 {.res = P_PPI0_D15, .offset = 11},
273 {.res = P_SPORT1_TFS, .offset = 11},
274 {.res = P_SPORT1_TSCLK, .offset = 11},
275 {.res = P_SPORT1_DTPRI, .offset = 11},
276 {.res = P_PPI0_D10, .offset = 10},
277 {.res = P_PPI0_D11, .offset = 10},
278 {.res = P_PPI0_D12, .offset = 10},
279 {.res = P_SPORT1_RSCLK, .offset = 10},
280 {.res = P_SPORT1_RFS, .offset = 10},
281 {.res = P_SPORT1_DRPRI, .offset = 10},
282 {.res = P_PPI0_D8, .offset = 9},
283 {.res = P_PPI0_D9, .offset = 9},
284 {.res = P_SPORT1_DRSEC, .offset = 9},
285 {.res = P_SPORT1_DTSEC, .offset = 9},
286 {.res = P_TMR2, .offset = 8},
287 {.res = P_PPI0_FS3, .offset = 8},
288 {.res = P_TMR3, .offset = 7},
289 {.res = P_SPI0_SSEL4, .offset = 7},
290 {.res = P_TMR4, .offset = 6},
291 {.res = P_SPI0_SSEL5, .offset = 6},
292 {.res = P_TMR5, .offset = 5},
293 {.res = P_SPI0_SSEL6, .offset = 5},
294 {.res = P_UART1_RX, .offset = 4},
295 {.res = P_UART1_TX, .offset = 4},
296 {.res = P_TMR6, .offset = 4},
297 {.res = P_TMR7, .offset = 4},
298 {.res = P_UART0_RX, .offset = 3},
299 {.res = P_UART0_TX, .offset = 3},
300 {.res = P_DMAR0, .offset = 3},
301 {.res = P_DMAR1, .offset = 3},
302 {.res = P_SPORT0_DTSEC, .offset = 1},
303 {.res = P_SPORT0_DRSEC, .offset = 1},
304 {.res = P_CAN0_RX, .offset = 1},
305 {.res = P_CAN0_TX, .offset = 1},
306 {.res = P_SPI0_SSEL7, .offset = 1},
307 {.res = P_SPORT0_TFS, .offset = 0},
308 {.res = P_SPORT0_DTPRI, .offset = 0},
309 {.res = P_SPI0_SSEL2, .offset = 0},
310 {.res = P_SPI0_SSEL3, .offset = 0},
c58c2140
MH		 311};
312
313static void portmux_setup(unsigned short per, unsigned short function)
314{
8c613623 315 u16 y, offset, muxreg;
c58c2140 316
8c613623
MH		 317 for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
318 if (port_mux_lut[y].res == per) {
c58c2140
MH		 319
320 /* SET PORTMUX REG */
321
8c613623 322 offset = port_mux_lut[y].offset;
c58c2140
MH		 323 muxreg = bfin_read_PORT_MUX();
324
325 if (offset != 1) {
326 muxreg &= ~(1 << offset);
327 } else {
328 muxreg &= ~(3 << 1);
329 }
330
331 muxreg |= (function << offset);
332 bfin_write_PORT_MUX(muxreg);
333 }
334 }
335}
d2b11a46
MH		 336#elif defined(BF548_FAMILY)
337inline void portmux_setup(unsigned short portno, unsigned short function)
338{
339 u32 pmux;
340
341 pmux = gpio_array[gpio_bank(portno)]->port_mux;
342
343 pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
344 pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
345
346 gpio_array[gpio_bank(portno)]->port_mux = pmux;
347}
348
349inline u16 get_portmux(unsigned short portno)
350{
351 u32 pmux;
c58c2140 352
d2b11a46
MH		 353 pmux = gpio_array[gpio_bank(portno)]->port_mux;
354
355 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
356}
c58c2140
MH		 357#else
358# define portmux_setup(...) do { } while (0)
359#endif
1394f032 360
d2b11a46 361#ifndef BF548_FAMILY
a161bb05 362static void default_gpio(unsigned short gpio)
1394f032 363{
1f83b8f1 364 unsigned short bank, bitmask;
2b39331a 365 unsigned long flags;
1394f032
BW		 366
367 bank = gpio_bank(gpio);
368 bitmask = gpio_bit(gpio);
369
2b39331a
MH		 370 local_irq_save(flags);
371
1394f032
BW		 372 gpio_bankb[bank]->maska_clear = bitmask;
373 gpio_bankb[bank]->maskb_clear = bitmask;
374 SSYNC();
375 gpio_bankb[bank]->inen &= ~bitmask;
376 gpio_bankb[bank]->dir &= ~bitmask;
377 gpio_bankb[bank]->polar &= ~bitmask;
378 gpio_bankb[bank]->both &= ~bitmask;
379 gpio_bankb[bank]->edge &= ~bitmask;
2b39331a
MH		 380 AWA_DUMMY_READ(edge);
381 local_irq_restore(flags);
382
1394f032 383}
d2b11a46
MH		 384#else
385# define default_gpio(...) do { } while (0)
386#endif
1394f032 387
a161bb05 388static int __init bfin_gpio_init(void)
1394f032 389{
8c613623
MH		 390 str_ident = kcalloc(MAX_RESOURCES,
391 sizeof(struct str_ident), GFP_KERNEL);
392 if (str_ident == NULL)
c58c2140 393 return -ENOMEM;
1394f032 394
8c613623
MH		 395 memset(str_ident, 0, MAX_RESOURCES * sizeof(struct str_ident));
396
c58c2140 397 printk(KERN_INFO "Blackfin GPIO Controller\n");
1394f032
BW		 398
399 return 0;
c58c2140 400
1394f032 401}
1394f032
BW		 402arch_initcall(bfin_gpio_init);
403
404
d2b11a46 405#ifndef BF548_FAMILY
1394f032
BW		 406/***********************************************************
407*
408* FUNCTIONS: Blackfin General Purpose Ports Access Functions
409*
410* INPUTS/OUTPUTS:
411* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
412*
413*
414* DESCRIPTION: These functions abstract direct register access
415* to Blackfin processor General Purpose
416* Ports Regsiters
417*
418* CAUTION: These functions do not belong to the GPIO Driver API
419*************************************************************
420* MODIFICATION HISTORY :
421**************************************************************/
422
423/* Set a specific bit */
424
425#define SET_GPIO(name) \
426void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
427{ \
428 unsigned long flags; \
c58c2140 429 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
1394f032
BW		 430 local_irq_save(flags); \
431 if (arg) \
432 gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
433 else \
434 gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
2b39331a 435 AWA_DUMMY_READ(name); \
1394f032
BW		 436 local_irq_restore(flags); \
437} \
438EXPORT_SYMBOL(set_gpio_ ## name);
439
440SET_GPIO(dir)
441SET_GPIO(inen)
442SET_GPIO(polar)
443SET_GPIO(edge)
444SET_GPIO(both)
445
446
2b39331a
MH		 447#if ANOMALY_05000311 || ANOMALY_05000323
448#define SET_GPIO_SC(name) \
449void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
450{ \
451 unsigned long flags; \
452 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
453 local_irq_save(flags); \
454 if (arg) \
455 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
456 else \
457 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
458 AWA_DUMMY_READ(name); \
459 local_irq_restore(flags); \
460} \
461EXPORT_SYMBOL(set_gpio_ ## name);
462#else
1394f032
BW		 463#define SET_GPIO_SC(name) \
464void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
465{ \
c58c2140 466 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
1394f032
BW		 467 if (arg) \
468 gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
469 else \
470 gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
471} \
472EXPORT_SYMBOL(set_gpio_ ## name);
2b39331a 473#endif
1394f032
BW		 474
475SET_GPIO_SC(maska)
476SET_GPIO_SC(maskb)
1394f032 477SET_GPIO_SC(data)
1394f032 478
2b39331a 479#if ANOMALY_05000311 || ANOMALY_05000323
1394f032
BW		 480void set_gpio_toggle(unsigned short gpio)
481{
482 unsigned long flags;
c58c2140 483 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 484 local_irq_save(flags);
485 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
2b39331a 486 AWA_DUMMY_READ(toggle);
1394f032
BW		 487 local_irq_restore(flags);
488}
489#else
490void set_gpio_toggle(unsigned short gpio)
491{
c58c2140 492 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 493 gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
494}
495#endif
496EXPORT_SYMBOL(set_gpio_toggle);
497
498
499/*Set current PORT date (16-bit word)*/
500
2b39331a 501#if ANOMALY_05000311 || ANOMALY_05000323
1394f032
BW		 502#define SET_GPIO_P(name) \
503void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \
504{ \
2b39331a
MH		 505 unsigned long flags; \
506 local_irq_save(flags); \
1394f032 507 gpio_bankb[gpio_bank(gpio)]->name = arg; \
2b39331a
MH		 508 AWA_DUMMY_READ(name); \
509 local_irq_restore(flags); \
1394f032
BW		 510} \
511EXPORT_SYMBOL(set_gpiop_ ## name);
2b39331a
MH		 512#else
513#define SET_GPIO_P(name) \
514void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \
515{ \
516 gpio_bankb[gpio_bank(gpio)]->name = arg; \
517} \
518EXPORT_SYMBOL(set_gpiop_ ## name);
519#endif
1394f032 520
2b39331a 521SET_GPIO_P(data)
1394f032
BW		 522SET_GPIO_P(dir)
523SET_GPIO_P(inen)
524SET_GPIO_P(polar)
525SET_GPIO_P(edge)
526SET_GPIO_P(both)
527SET_GPIO_P(maska)
528SET_GPIO_P(maskb)
529
530
1394f032 531/* Get a specific bit */
2b39331a
MH		 532#if ANOMALY_05000311 || ANOMALY_05000323
533#define GET_GPIO(name) \
534unsigned short get_gpio_ ## name(unsigned short gpio) \
535{ \
536 unsigned long flags; \
537 unsigned short ret; \
538 local_irq_save(flags); \
539 ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
540 AWA_DUMMY_READ(name); \
541 local_irq_restore(flags); \
542 return ret; \
543} \
544EXPORT_SYMBOL(get_gpio_ ## name);
545#else
1394f032
BW		 546#define GET_GPIO(name) \
547unsigned short get_gpio_ ## name(unsigned short gpio) \
548{ \
549 return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \
550} \
551EXPORT_SYMBOL(get_gpio_ ## name);
2b39331a 552#endif
1394f032 553
2b39331a 554GET_GPIO(data)
1394f032
BW		 555GET_GPIO(dir)
556GET_GPIO(inen)
557GET_GPIO(polar)
558GET_GPIO(edge)
559GET_GPIO(both)
560GET_GPIO(maska)
561GET_GPIO(maskb)
562
1394f032
BW		 563/*Get current PORT date (16-bit word)*/
564
2b39331a
MH		 565#if ANOMALY_05000311 || ANOMALY_05000323
566#define GET_GPIO_P(name) \
567unsigned short get_gpiop_ ## name(unsigned short gpio) \
568{ \
569 unsigned long flags; \
570 unsigned short ret; \
571 local_irq_save(flags); \
572 ret = (gpio_bankb[gpio_bank(gpio)]->name); \
573 AWA_DUMMY_READ(name); \
574 local_irq_restore(flags); \
575 return ret; \
576} \
577EXPORT_SYMBOL(get_gpiop_ ## name);
578#else
1394f032
BW		 579#define GET_GPIO_P(name) \
580unsigned short get_gpiop_ ## name(unsigned short gpio) \
581{ \
582 return (gpio_bankb[gpio_bank(gpio)]->name);\
583} \
584EXPORT_SYMBOL(get_gpiop_ ## name);
2b39331a 585#endif
1394f032 586
2b39331a 587GET_GPIO_P(data)
1394f032
BW		 588GET_GPIO_P(dir)
589GET_GPIO_P(inen)
590GET_GPIO_P(polar)
591GET_GPIO_P(edge)
592GET_GPIO_P(both)
593GET_GPIO_P(maska)
594GET_GPIO_P(maskb)
595
1394f032
BW		 596
597#ifdef CONFIG_PM
598/***********************************************************
599*
600* FUNCTIONS: Blackfin PM Setup API
601*
602* INPUTS/OUTPUTS:
603* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
604* type -
605* PM_WAKE_RISING
606* PM_WAKE_FALLING
607* PM_WAKE_HIGH
608* PM_WAKE_LOW
609* PM_WAKE_BOTH_EDGES
610*
611* DESCRIPTION: Blackfin PM Driver API
612*
613* CAUTION:
614*************************************************************
615* MODIFICATION HISTORY :
616**************************************************************/
617int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type)
618{
619 unsigned long flags;
620
621 if ((check_gpio(gpio) < 0) || !type)
622 return -EINVAL;
623
624 local_irq_save(flags);
625
626 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
627 wakeup_flags_map[gpio] = type;
628 local_irq_restore(flags);
629
630 return 0;
631}
632EXPORT_SYMBOL(gpio_pm_wakeup_request);
633
634void gpio_pm_wakeup_free(unsigned short gpio)
635{
636 unsigned long flags;
637
638 if (check_gpio(gpio) < 0)
639 return;
640
641 local_irq_save(flags);
642
643 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
644
645 local_irq_restore(flags);
646}
647EXPORT_SYMBOL(gpio_pm_wakeup_free);
648
649static int bfin_gpio_wakeup_type(unsigned short gpio, unsigned char type)
650{
651 port_setup(gpio, GPIO_USAGE);
652 set_gpio_dir(gpio, 0);
653 set_gpio_inen(gpio, 1);
654
655 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
656 set_gpio_edge(gpio, 1);
657 else
658 set_gpio_edge(gpio, 0);
659
660 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
661 set_gpio_both(gpio, 1);
662 else
663 set_gpio_both(gpio, 0);
664
665 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
666 set_gpio_polar(gpio, 1);
667 else
668 set_gpio_polar(gpio, 0);
669
670 SSYNC();
671
672 return 0;
673}
674
675u32 gpio_pm_setup(void)
676{
677 u32 sic_iwr = 0;
678 u16 bank, mask, i, gpio;
679
1f83b8f1 680 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 681 mask = wakeup_map[gpio_bank(i)];
682 bank = gpio_bank(i);
683
684 gpio_bank_saved[bank].maskb = gpio_bankb[bank]->maskb;
685 gpio_bankb[bank]->maskb = 0;
686
687 if (mask) {
688#ifdef BF537_FAMILY
689 gpio_bank_saved[bank].fer = *port_fer[bank];
690#endif
691 gpio_bank_saved[bank].inen = gpio_bankb[bank]->inen;
692 gpio_bank_saved[bank].polar = gpio_bankb[bank]->polar;
693 gpio_bank_saved[bank].dir = gpio_bankb[bank]->dir;
694 gpio_bank_saved[bank].edge = gpio_bankb[bank]->edge;
695 gpio_bank_saved[bank].both = gpio_bankb[bank]->both;
c58c2140
MH		 696 gpio_bank_saved[bank].reserved =
697 reserved_gpio_map[bank];
1394f032
BW		 698
699 gpio = i;
700
701 while (mask) {
702 if (mask & 1) {
c58c2140 703 reserved_gpio_map[gpio_bank(gpio)] |=
581d62ab
MH		 704 gpio_bit(gpio);
705 bfin_gpio_wakeup_type(gpio,
706 wakeup_flags_map[gpio]);
1394f032
BW		 707 set_gpio_data(gpio, 0); /*Clear*/
708 }
709 gpio++;
710 mask >>= 1;
711 }
712
581d62ab
MH		 713 sic_iwr |= 1 <<
714 (sic_iwr_irqs[bank] - (IRQ_CORETMR + 1));
1394f032
BW		 715 gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
716 }
717 }
718
2b39331a
MH		 719 AWA_DUMMY_READ(maskb_set);
720
1394f032
BW		 721 if (sic_iwr)
722 return sic_iwr;
723 else
724 return IWR_ENABLE_ALL;
725}
726
1394f032
BW		 727void gpio_pm_restore(void)
728{
729 u16 bank, mask, i;
730
1f83b8f1 731 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
1394f032
BW		 732 mask = wakeup_map[gpio_bank(i)];
733 bank = gpio_bank(i);
734
735 if (mask) {
736#ifdef BF537_FAMILY
737 *port_fer[bank] = gpio_bank_saved[bank].fer;
738#endif
739 gpio_bankb[bank]->inen = gpio_bank_saved[bank].inen;
740 gpio_bankb[bank]->dir = gpio_bank_saved[bank].dir;
741 gpio_bankb[bank]->polar = gpio_bank_saved[bank].polar;
742 gpio_bankb[bank]->edge = gpio_bank_saved[bank].edge;
743 gpio_bankb[bank]->both = gpio_bank_saved[bank].both;
581d62ab 744
c58c2140
MH		 745 reserved_gpio_map[bank] =
746 gpio_bank_saved[bank].reserved;
581d62ab 747
1394f032
BW		 748 }
749
750 gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
751 }
2b39331a 752 AWA_DUMMY_READ(maskb);
1394f032
BW		 753}
754
755#endif
d2b11a46 756#endif /* BF548_FAMILY */
1394f032 757
d2b11a46
MH		 758/***********************************************************
759*
760* FUNCTIONS: Blackfin Peripheral Resource Allocation
761* and PortMux Setup
762*
763* INPUTS/OUTPUTS:
764* per Peripheral Identifier
765* label String
766*
767* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
768*
769* CAUTION:
770*************************************************************
771* MODIFICATION HISTORY :
772**************************************************************/
773
774#ifdef BF548_FAMILY
775int peripheral_request(unsigned short per, const char *label)
776{
777 unsigned long flags;
778 unsigned short ident = P_IDENT(per);
779
780 /*
781 * Don't cares are pins with only one dedicated function
782 */
c58c2140 783
d2b11a46
MH		 784 if (per & P_DONTCARE)
785 return 0;
786
787 if (!(per & P_DEFINED))
788 return -ENODEV;
789
790 if (check_gpio(ident) < 0)
791 return -EINVAL;
c58c2140 792
d2b11a46
MH		 793 local_irq_save(flags);
794
795 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
796 printk(KERN_ERR
797 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
798 __FUNCTION__, ident, get_label(ident));
799 dump_stack();
800 local_irq_restore(flags);
801 return -EBUSY;
802 }
803
804 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
805
806 u16 funct = get_portmux(ident);
807
808 /*
809 * Pin functions like AMC address strobes my
810 * be requested and used by several drivers
811 */
812
813 if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
814
815 /*
816 * Allow that the identical pin function can
817 * be requested from the same driver twice
818 */
819
820 if (cmp_label(ident, label) == 0)
821 goto anyway;
822
823 printk(KERN_ERR
824 "%s: Peripheral %d function %d is already reserved by %s !\n",
825 __FUNCTION__, ident, P_FUNCT2MUX(per), get_label(ident));
826 dump_stack();
827 local_irq_restore(flags);
828 return -EBUSY;
829 }
830 }
831
832anyway:
833 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
834
835 portmux_setup(ident, P_FUNCT2MUX(per));
836 port_setup(ident, PERIPHERAL_USAGE);
837
838 local_irq_restore(flags);
839 set_label(ident, label);
840
841 return 0;
842}
843EXPORT_SYMBOL(peripheral_request);
844#else
c58c2140
MH		 845
846int peripheral_request(unsigned short per, const char *label)
847{
848 unsigned long flags;
849 unsigned short ident = P_IDENT(per);
850
851 /*
852 * Don't cares are pins with only one dedicated function
853 */
854
855 if (per & P_DONTCARE)
856 return 0;
857
858 if (!(per & P_DEFINED))
859 return -ENODEV;
860
c58c2140
MH		 861 local_irq_save(flags);
862
cda6a20b
MH		 863 if (!check_gpio(ident)) {
864
c58c2140
MH		 865 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
866 printk(KERN_ERR
867 "%s: Peripheral %d is already reserved as GPIO by %s !\n",
868 __FUNCTION__, ident, get_label(ident));
869 dump_stack();
870 local_irq_restore(flags);
871 return -EBUSY;
872 }
873
cda6a20b
MH		 874 }
875
c58c2140
MH		 876 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
877
878 /*
879 * Pin functions like AMC address strobes my
880 * be requested and used by several drivers
881 */
882
883 if (!(per & P_MAYSHARE)) {
884
885 /*
886 * Allow that the identical pin function can
887 * be requested from the same driver twice
888 */
889
890 if (cmp_label(ident, label) == 0)
891 goto anyway;
892
893 printk(KERN_ERR
894 "%s: Peripheral %d function %d is already"
8c613623 895 " reserved by %s !\n",
c58c2140
MH		 896 __FUNCTION__, ident, P_FUNCT2MUX(per),
897 get_label(ident));
898 dump_stack();
899 local_irq_restore(flags);
900 return -EBUSY;
901 }
902
903 }
904
905anyway:
c58c2140
MH		 906 portmux_setup(per, P_FUNCT2MUX(per));
907
908 port_setup(ident, PERIPHERAL_USAGE);
909
910 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
911 local_irq_restore(flags);
912 set_label(ident, label);
913
914 return 0;
915}
916EXPORT_SYMBOL(peripheral_request);
d2b11a46 917#endif
c58c2140
MH		 918
919int peripheral_request_list(unsigned short per[], const char *label)
920{
921 u16 cnt;
922 int ret;
923
924 for (cnt = 0; per[cnt] != 0; cnt++) {
314c98d5 925
c58c2140 926 ret = peripheral_request(per[cnt], label);
314c98d5
MH		 927
928 if (ret < 0) {
929 for ( ; cnt > 0; cnt--) {
930 peripheral_free(per[cnt - 1]);
931 }
932 return ret;
933 }
c58c2140
MH		 934 }
935
936 return 0;
937}
938EXPORT_SYMBOL(peripheral_request_list);
939
940void peripheral_free(unsigned short per)
941{
942 unsigned long flags;
943 unsigned short ident = P_IDENT(per);
944
945 if (per & P_DONTCARE)
946 return;
947
948 if (!(per & P_DEFINED))
949 return;
950
951 if (check_gpio(ident) < 0)
952 return;
953
954 local_irq_save(flags);
955
956 if (unlikely(!(reserved_peri_map[gpio_bank(ident)]
957 & gpio_bit(ident)))) {
958 local_irq_restore(flags);
959 return;
960 }
961
962 if (!(per & P_MAYSHARE)) {
963 port_setup(ident, GPIO_USAGE);
964 }
965
966 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
967
2acde902
MH		 968 set_label(ident, "free");
969
c58c2140
MH		 970 local_irq_restore(flags);
971}
972EXPORT_SYMBOL(peripheral_free);
973
974void peripheral_free_list(unsigned short per[])
975{
976 u16 cnt;
977
978 for (cnt = 0; per[cnt] != 0; cnt++) {
979 peripheral_free(per[cnt]);
980 }
981
982}
983EXPORT_SYMBOL(peripheral_free_list);
984
1394f032
BW		 985/***********************************************************
986*
987* FUNCTIONS: Blackfin GPIO Driver
988*
989* INPUTS/OUTPUTS:
d2b11a46
MH		 990* gpio PIO Number between 0 and MAX_BLACKFIN_GPIOS
991* label String
1394f032
BW		 992*
993* DESCRIPTION: Blackfin GPIO Driver API
994*
995* CAUTION:
996*************************************************************
997* MODIFICATION HISTORY :
998**************************************************************/
999
1000int gpio_request(unsigned short gpio, const char *label)
1001{
1002 unsigned long flags;
1003
1004 if (check_gpio(gpio) < 0)
1005 return -EINVAL;
1006
1007 local_irq_save(flags);
1008
2acde902
MH		 1009 /*
1010 * Allow that the identical GPIO can
1011 * be requested from the same driver twice
1012 * Do nothing and return -
1013 */
1014
1015 if (cmp_label(gpio, label) == 0) {
1016 local_irq_restore(flags);
1017 return 0;
1018 }
1019
c58c2140 1020 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
d2b11a46
MH		 1021 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
1022 gpio, get_label(gpio));
1023 dump_stack();
1024 local_irq_restore(flags);
1025 return -EBUSY;
1026 }
1027 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
1028 printk(KERN_ERR
1029 "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
1030 gpio, get_label(gpio));
1394f032
BW		 1031 dump_stack();
1032 local_irq_restore(flags);
1033 return -EBUSY;
1034 }
d2b11a46 1035
c58c2140 1036 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
1394f032
BW		 1037
1038 local_irq_restore(flags);
1039
1040 port_setup(gpio, GPIO_USAGE);
d2b11a46 1041 set_label(gpio, label);
1394f032
BW		 1042
1043 return 0;
1044}
1045EXPORT_SYMBOL(gpio_request);
1046
1394f032
BW		 1047void gpio_free(unsigned short gpio)
1048{
1049 unsigned long flags;
1050
1051 if (check_gpio(gpio) < 0)
1052 return;
1053
1054 local_irq_save(flags);
1055
c58c2140 1056 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
1394f032
BW		 1057 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
1058 dump_stack();
1059 local_irq_restore(flags);
1060 return;
1061 }
1062
1063 default_gpio(gpio);
1064
c58c2140 1065 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
1394f032 1066
2acde902
MH		 1067 set_label(gpio, "free");
1068
1394f032
BW		 1069 local_irq_restore(flags);
1070}
1071EXPORT_SYMBOL(gpio_free);
1072
d2b11a46
MH		 1073#ifdef BF548_FAMILY
1074void gpio_direction_input(unsigned short gpio)
1075{
1076 unsigned long flags;
1077
1078 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1079
1080 local_irq_save(flags);
1081 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
1082 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
1083 local_irq_restore(flags);
1084}
1085EXPORT_SYMBOL(gpio_direction_input);
1086
1087void gpio_direction_output(unsigned short gpio)
1088{
1089 unsigned long flags;
1090
1091 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1092
1093 local_irq_save(flags);
1094 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
1095 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
1096 local_irq_restore(flags);
1097}
1098EXPORT_SYMBOL(gpio_direction_output);
1099
1100void gpio_set_value(unsigned short gpio, unsigned short arg)
1101{
1102 if (arg)
1103 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
1104 else
1105 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
1106
1107}
1108EXPORT_SYMBOL(gpio_set_value);
1109
1110unsigned short gpio_get_value(unsigned short gpio)
1111{
1112 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
1113}
1114EXPORT_SYMBOL(gpio_get_value);
1115
1116#else
1117
1394f032
BW		 1118void gpio_direction_input(unsigned short gpio)
1119{
1120 unsigned long flags;
1121
c58c2140 1122 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 1123
1124 local_irq_save(flags);
1125 gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
1126 gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
2b39331a 1127 AWA_DUMMY_READ(inen);
1394f032
BW		 1128 local_irq_restore(flags);
1129}
1130EXPORT_SYMBOL(gpio_direction_input);
1131
1132void gpio_direction_output(unsigned short gpio)
1133{
1134 unsigned long flags;
1135
c58c2140 1136 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
1394f032
BW		 1137
1138 local_irq_save(flags);
1139 gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1140 gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
2b39331a 1141 AWA_DUMMY_READ(dir);
1394f032
BW		 1142 local_irq_restore(flags);
1143}
1144EXPORT_SYMBOL(gpio_direction_output);
168f1212
MF		 1145
1146/* If we are booting from SPI and our board lacks a strong enough pull up,
1147 * the core can reset and execute the bootrom faster than the resistor can
1148 * pull the signal logically high. To work around this (common) error in
1149 * board design, we explicitly set the pin back to GPIO mode, force /CS
1150 * high, and wait for the electrons to do their thing.
1151 *
1152 * This function only makes sense to be called from reset code, but it
1153 * lives here as we need to force all the GPIO states w/out going through
1154 * BUG() checks and such.
1155 */
1156void bfin_gpio_reset_spi0_ssel1(void)
1157{
4d5f4ed3
MH		 1158 u16 gpio = P_IDENT(P_SPI0_SSEL1);
1159
1160 port_setup(gpio, GPIO_USAGE);
1161 gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
168f1212
MF		 1162 udelay(1);
1163}
d2b11a46
MH		 1164
1165#endif /*BF548_FAMILY */
Linux kernel - Deliverables
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