[deliverable/linux.git] / arch / blackfin / kernel / cplb-mpu / cplbinit.c

/*
 * Blackfin CPLB initialization
 *
 * Copyright 2008-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>

#include <asm/blackfin.h>
#include <asm/cplb.h>
#include <asm/cplbinit.h>
#include <asm/mem_map.h>

#if ANOMALY_05000263
# error the MPU will not function safely while Anomaly 05000263 applies
#endif

struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];

int first_switched_icplb, first_switched_dcplb;
int first_mask_dcplb;

void __init generate_cplb_tables_cpu(unsigned int cpu)
{
	int i_d, i_i;
	unsigned long addr;
	unsigned long d_data, i_data;
	unsigned long d_cache = 0, i_cache = 0;

	printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");

#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
	i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
#endif

#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
	d_cache = CPLB_L1_CHBL;
#ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
	d_cache |= CPLB_L1_AOW | CPLB_WT;
#endif
#endif

	i_d = i_i = 0;

	/* Set up the zero page.  */
	dcplb_tbl[cpu][i_d].addr = 0;
	dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;

	icplb_tbl[cpu][i_i].addr = 0;
	icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;

	/* Cover kernel memory with 4M pages.  */
	addr = 0;
	d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
	i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;

	for (; addr < memory_start; addr += 4 * 1024 * 1024) {
		dcplb_tbl[cpu][i_d].addr = addr;
		dcplb_tbl[cpu][i_d++].data = d_data;
		icplb_tbl[cpu][i_i].addr = addr;
		icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
	}

	/* Cover L1 memory.  One 4M area for code and data each is enough.  */
#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
	dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
	dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
#endif
#if L1_CODE_LENGTH > 0
	icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
	icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
#endif

	/* Cover L2 memory */
#if L2_LENGTH > 0
	dcplb_tbl[cpu][i_d].addr = L2_START;
	dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
	icplb_tbl[cpu][i_i].addr = L2_START;
	icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
#endif

	first_mask_dcplb = i_d;
	first_switched_dcplb = i_d + (1 << page_mask_order);
	first_switched_icplb = i_i;

	while (i_d < MAX_CPLBS)
		dcplb_tbl[cpu][i_d++].data = 0;
	while (i_i < MAX_CPLBS)
		icplb_tbl[cpu][i_i++].data = 0;
}

void generate_cplb_tables_all(void)
{
}
Commit	Line	Data
b97b8a99 BS	1	/*
	2	* Blackfin CPLB initialization
	3	*
96f1050d	4	* Copyright 2008-2009 Analog Devices Inc.
b97b8a99	5	*
96f1050d	6	* Licensed under the GPL-2 or later.
b97b8a99	7	*/
96f1050d	8
b97b8a99 BS	9	#include <linux/module.h>
	10
	11	#include <asm/blackfin.h>
	12	#include <asm/cplb.h>
	13	#include <asm/cplbinit.h>
dbc895f9	14	#include <asm/mem_map.h>
b97b8a99	15
c605999b MF	16	#if ANOMALY_05000263
	17	# error the MPU will not function safely while Anomaly 05000263 applies
	18	#endif
	19
b8a98989 GY	20	struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
b8a98989 GY	21	struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
b97b8a99 BS	22
	23	int first_switched_icplb, first_switched_dcplb;
	24	int first_mask_dcplb;
	25
b8a98989	26	void __init generate_cplb_tables_cpu(unsigned int cpu)
b97b8a99 BS	27	{
	28	int i_d, i_i;
	29	unsigned long addr;
	30	unsigned long d_data, i_data;
	31	unsigned long d_cache = 0, i_cache = 0;
	32
8cab0288 MF	33	printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
8cab0288 MF	34
41ba653f	35	#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
b97b8a99 BS	36	i_cache = CPLB_L1_CHBL \| ANOMALY_05000158_WORKAROUND;
	37	#endif
	38
41ba653f	39	#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
b97b8a99	40	d_cache = CPLB_L1_CHBL;
7bae2c48	41	#ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
b97b8a99 BS	42	d_cache \|= CPLB_L1_AOW \| CPLB_WT;
	43	#endif
	44	#endif
b8a98989	45
b97b8a99 BS	46	i_d = i_i = 0;
	47
	48	/* Set up the zero page. */
b8a98989 GY	49	dcplb_tbl[cpu][i_d].addr = 0;
b8a98989 GY	50	dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS \| PAGE_SIZE_1KB;
b97b8a99	51
b8a98989	52	icplb_tbl[cpu][i_i].addr = 0;
a17c7f6f	53	icplb_tbl[cpu][i_i++].data = CPLB_VALID \| i_cache \| CPLB_USER_RD \| PAGE_SIZE_1KB;
b97b8a99 BS	54
	55	/* Cover kernel memory with 4M pages. */
	56	addr = 0;
	57	d_data = d_cache \| CPLB_SUPV_WR \| CPLB_VALID \| PAGE_SIZE_4MB \| CPLB_DIRTY;
	58	i_data = i_cache \| CPLB_VALID \| CPLB_PORTPRIO \| PAGE_SIZE_4MB;
	59
	60	for (; addr < memory_start; addr += 4 * 1024 * 1024) {
b8a98989 GY	61	dcplb_tbl[cpu][i_d].addr = addr;
	62	dcplb_tbl[cpu][i_d++].data = d_data;
	63	icplb_tbl[cpu][i_i].addr = addr;
	64	icplb_tbl[cpu][i_i++].data = i_data \| (addr == 0 ? CPLB_USER_RD : 0);
b97b8a99 BS	65	}
	66
	67	/* Cover L1 memory. One 4M area for code and data each is enough. */
	68	#if L1_DATA_A_LENGTH > 0 \|\| L1_DATA_B_LENGTH > 0
b8a98989 GY	69	dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
b8a98989 GY	70	dcplb_tbl[cpu][i_d++].data = L1_DMEMORY \| PAGE_SIZE_4MB;
b97b8a99	71	#endif
f099f39a	72	#if L1_CODE_LENGTH > 0
b8a98989 GY	73	icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
b8a98989 GY	74	icplb_tbl[cpu][i_i++].data = L1_IMEMORY \| PAGE_SIZE_4MB;
f099f39a SZ	75	#endif
	76
	77	/* Cover L2 memory */
	78	#if L2_LENGTH > 0
b8a98989	79	dcplb_tbl[cpu][i_d].addr = L2_START;
41ba653f	80	dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
b8a98989	81	icplb_tbl[cpu][i_i].addr = L2_START;
41ba653f	82	icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
f099f39a	83	#endif
b97b8a99 BS	84
	85	first_mask_dcplb = i_d;
	86	first_switched_dcplb = i_d + (1 << page_mask_order);
	87	first_switched_icplb = i_i;
	88
	89	while (i_d < MAX_CPLBS)
b8a98989	90	dcplb_tbl[cpu][i_d++].data = 0;
b97b8a99	91	while (i_i < MAX_CPLBS)
b8a98989	92	icplb_tbl[cpu][i_i++].data = 0;
b97b8a99	93	}
dbdf20db BS	94
	95	void generate_cplb_tables_all(void)
	96	{
	97	}