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29440a2b BS |
1 | /* |
2 | * Blackfin CPLB initialization | |
3 | * | |
4 | * Copyright 2004-2007 Analog Devices Inc. | |
5 | * | |
6 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, see the file COPYING, or write | |
20 | * to the Free Software Foundation, Inc., | |
21 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | */ | |
38316382 | 23 | |
29440a2b BS |
24 | #include <linux/module.h> |
25 | ||
26 | #include <asm/blackfin.h> | |
04be80ef | 27 | #include <asm/cacheflush.h> |
3bebca2d | 28 | #include <asm/cplb.h> |
29440a2b | 29 | #include <asm/cplbinit.h> |
dbc895f9 | 30 | #include <asm/mem_map.h> |
29440a2b | 31 | |
dbdf20db BS |
32 | struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR; |
33 | struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR; | |
29440a2b | 34 | |
dbdf20db BS |
35 | int first_switched_icplb PDT_ATTR; |
36 | int first_switched_dcplb PDT_ATTR; | |
29440a2b | 37 | |
dbdf20db | 38 | struct cplb_boundary dcplb_bounds[9] PDT_ATTR; |
4663f6ef | 39 | struct cplb_boundary icplb_bounds[9] PDT_ATTR; |
29440a2b | 40 | |
dbdf20db BS |
41 | int icplb_nr_bounds PDT_ATTR; |
42 | int dcplb_nr_bounds PDT_ATTR; | |
29440a2b | 43 | |
dbdf20db | 44 | void __init generate_cplb_tables_cpu(unsigned int cpu) |
29440a2b | 45 | { |
dbdf20db BS |
46 | int i_d, i_i; |
47 | unsigned long addr; | |
29440a2b | 48 | |
dbdf20db BS |
49 | struct cplb_entry *d_tbl = dcplb_tbl[cpu]; |
50 | struct cplb_entry *i_tbl = icplb_tbl[cpu]; | |
29440a2b | 51 | |
dbdf20db | 52 | printk(KERN_INFO "NOMPU: setting up cplb tables\n"); |
29440a2b | 53 | |
dbdf20db | 54 | i_d = i_i = 0; |
29440a2b | 55 | |
e84dcaa1 | 56 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO |
dbdf20db BS |
57 | /* Set up the zero page. */ |
58 | d_tbl[i_d].addr = 0; | |
59 | d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; | |
e84dcaa1 BS |
60 | i_tbl[i_i].addr = 0; |
61 | i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB; | |
62 | #endif | |
29440a2b | 63 | |
dbdf20db BS |
64 | /* Cover kernel memory with 4M pages. */ |
65 | addr = 0; | |
29440a2b | 66 | |
dbdf20db BS |
67 | for (; addr < memory_start; addr += 4 * 1024 * 1024) { |
68 | d_tbl[i_d].addr = addr; | |
69 | d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB; | |
70 | i_tbl[i_i].addr = addr; | |
71 | i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; | |
72 | } | |
29440a2b | 73 | |
dbdf20db | 74 | /* Cover L1 memory. One 4M area for code and data each is enough. */ |
5bc6e3cf GY |
75 | if (cpu == 0) { |
76 | if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { | |
77 | d_tbl[i_d].addr = L1_DATA_A_START; | |
78 | d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; | |
79 | } | |
80 | i_tbl[i_i].addr = L1_CODE_START; | |
81 | i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; | |
29440a2b | 82 | } |
5bc6e3cf GY |
83 | #ifdef CONFIG_SMP |
84 | else { | |
85 | if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) { | |
86 | d_tbl[i_d].addr = COREB_L1_DATA_A_START; | |
87 | d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB; | |
88 | } | |
89 | i_tbl[i_i].addr = COREB_L1_CODE_START; | |
90 | i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB; | |
91 | } | |
92 | #endif | |
dbdf20db BS |
93 | first_switched_dcplb = i_d; |
94 | first_switched_icplb = i_i; | |
29440a2b | 95 | |
dbdf20db BS |
96 | BUG_ON(first_switched_dcplb > MAX_CPLBS); |
97 | BUG_ON(first_switched_icplb > MAX_CPLBS); | |
29440a2b | 98 | |
dbdf20db BS |
99 | while (i_d < MAX_CPLBS) |
100 | d_tbl[i_d++].data = 0; | |
101 | while (i_i < MAX_CPLBS) | |
102 | i_tbl[i_i++].data = 0; | |
29440a2b BS |
103 | } |
104 | ||
dbdf20db | 105 | void __init generate_cplb_tables_all(void) |
29440a2b | 106 | { |
dbdf20db | 107 | int i_d, i_i; |
29440a2b | 108 | |
dbdf20db BS |
109 | i_d = 0; |
110 | /* Normal RAM, including MTD FS. */ | |
29440a2b | 111 | #ifdef CONFIG_MTD_UCLINUX |
dbdf20db | 112 | dcplb_bounds[i_d].eaddr = memory_mtd_start + mtd_size; |
29440a2b | 113 | #else |
dbdf20db | 114 | dcplb_bounds[i_d].eaddr = memory_end; |
29440a2b | 115 | #endif |
dbdf20db BS |
116 | dcplb_bounds[i_d++].data = SDRAM_DGENERIC; |
117 | /* DMA uncached region. */ | |
118 | if (DMA_UNCACHED_REGION) { | |
119 | dcplb_bounds[i_d].eaddr = _ramend; | |
120 | dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL; | |
121 | } | |
122 | if (_ramend != physical_mem_end) { | |
123 | /* Reserved memory. */ | |
124 | dcplb_bounds[i_d].eaddr = physical_mem_end; | |
125 | dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ? | |
126 | SDRAM_DGENERIC : SDRAM_DNON_CHBL); | |
127 | } | |
128 | /* Addressing hole up to the async bank. */ | |
129 | dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE; | |
130 | dcplb_bounds[i_d++].data = 0; | |
131 | /* ASYNC banks. */ | |
132 | dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE; | |
133 | dcplb_bounds[i_d++].data = SDRAM_EBIU; | |
134 | /* Addressing hole up to BootROM. */ | |
135 | dcplb_bounds[i_d].eaddr = BOOT_ROM_START; | |
136 | dcplb_bounds[i_d++].data = 0; | |
137 | /* BootROM -- largest one should be less than 1 meg. */ | |
138 | dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); | |
139 | dcplb_bounds[i_d++].data = SDRAM_DGENERIC; | |
140 | if (L2_LENGTH) { | |
141 | /* Addressing hole up to L2 SRAM. */ | |
142 | dcplb_bounds[i_d].eaddr = L2_START; | |
143 | dcplb_bounds[i_d++].data = 0; | |
144 | /* L2 SRAM. */ | |
145 | dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH; | |
146 | dcplb_bounds[i_d++].data = L2_DMEMORY; | |
147 | } | |
148 | dcplb_nr_bounds = i_d; | |
149 | BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds)); | |
29440a2b | 150 | |
dbdf20db BS |
151 | i_i = 0; |
152 | /* Normal RAM, including MTD FS. */ | |
29440a2b | 153 | #ifdef CONFIG_MTD_UCLINUX |
dbdf20db BS |
154 | icplb_bounds[i_i].eaddr = memory_mtd_start + mtd_size; |
155 | #else | |
156 | icplb_bounds[i_i].eaddr = memory_end; | |
29440a2b | 157 | #endif |
dbdf20db BS |
158 | icplb_bounds[i_i++].data = SDRAM_IGENERIC; |
159 | /* DMA uncached region. */ | |
160 | if (DMA_UNCACHED_REGION) { | |
161 | icplb_bounds[i_i].eaddr = _ramend; | |
162 | icplb_bounds[i_i++].data = 0; | |
29440a2b | 163 | } |
dbdf20db BS |
164 | if (_ramend != physical_mem_end) { |
165 | /* Reserved memory. */ | |
166 | icplb_bounds[i_i].eaddr = physical_mem_end; | |
167 | icplb_bounds[i_i++].data = (reserved_mem_icache_on ? | |
168 | SDRAM_IGENERIC : SDRAM_INON_CHBL); | |
169 | } | |
4663f6ef BS |
170 | /* Addressing hole up to the async bank. */ |
171 | icplb_bounds[i_i].eaddr = ASYNC_BANK0_BASE; | |
172 | icplb_bounds[i_i++].data = 0; | |
173 | /* ASYNC banks. */ | |
174 | icplb_bounds[i_i].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE; | |
175 | icplb_bounds[i_i++].data = SDRAM_EBIU; | |
dbdf20db BS |
176 | /* Addressing hole up to BootROM. */ |
177 | icplb_bounds[i_i].eaddr = BOOT_ROM_START; | |
178 | icplb_bounds[i_i++].data = 0; | |
179 | /* BootROM -- largest one should be less than 1 meg. */ | |
180 | icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); | |
181 | icplb_bounds[i_i++].data = SDRAM_IGENERIC; | |
4663f6ef | 182 | |
dbdf20db | 183 | if (L2_LENGTH) { |
4663f6ef | 184 | /* Addressing hole up to L2 SRAM. */ |
dbdf20db BS |
185 | icplb_bounds[i_i].eaddr = L2_START; |
186 | icplb_bounds[i_i++].data = 0; | |
187 | /* L2 SRAM. */ | |
188 | icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH; | |
189 | icplb_bounds[i_i++].data = L2_IMEMORY; | |
190 | } | |
191 | icplb_nr_bounds = i_i; | |
192 | BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds)); | |
29440a2b | 193 | } |