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Blackfin arch: new kernel config for BF548-EZKIT
[deliverable/linux.git] / arch / blackfin / kernel / setup.c
CommitLineData
1394f032
BW		 1/*
2 * File: arch/blackfin/kernel/setup.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/delay.h>
31#include <linux/console.h>
32#include <linux/bootmem.h>
33#include <linux/seq_file.h>
34#include <linux/cpu.h>
35#include <linux/module.h>
1394f032
BW		 36#include <linux/tty.h>
37
38#include <linux/ext2_fs.h>
39#include <linux/cramfs_fs.h>
40#include <linux/romfs_fs.h>
41
42#include <asm/cacheflush.h>
43#include <asm/blackfin.h>
44#include <asm/cplbinit.h>
45
a9c59c27
MF		 46u16 _bfin_swrst;
47
1394f032
BW		 48unsigned long memory_start, memory_end, physical_mem_end;
49unsigned long reserved_mem_dcache_on;
50unsigned long reserved_mem_icache_on;
51EXPORT_SYMBOL(memory_start);
52EXPORT_SYMBOL(memory_end);
53EXPORT_SYMBOL(physical_mem_end);
54EXPORT_SYMBOL(_ramend);
55
56#ifdef CONFIG_MTD_UCLINUX
57unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
58unsigned long _ebss;
59EXPORT_SYMBOL(memory_mtd_end);
60EXPORT_SYMBOL(memory_mtd_start);
61EXPORT_SYMBOL(mtd_size);
62#endif
63
5e10b4a6 64char __initdata command_line[COMMAND_LINE_SIZE];
1394f032
BW		 65
66#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
67static void generate_cpl_tables(void);
68#endif
69
70void __init bf53x_cache_init(void)
71{
72#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
73 generate_cpl_tables();
74#endif
75
76#ifdef CONFIG_BLKFIN_CACHE
77 bfin_icache_init();
78 printk(KERN_INFO "Instruction Cache Enabled\n");
79#endif
80
81#ifdef CONFIG_BLKFIN_DCACHE
82 bfin_dcache_init();
83 printk(KERN_INFO "Data Cache Enabled"
84# if defined CONFIG_BLKFIN_WB
85 " (write-back)"
86# elif defined CONFIG_BLKFIN_WT
87 " (write-through)"
88# endif
89 "\n");
90#endif
91}
92
52a07812 93void __init bf53x_relocate_l1_mem(void)
1394f032
BW		 94{
95 unsigned long l1_code_length;
96 unsigned long l1_data_a_length;
97 unsigned long l1_data_b_length;
98
99 l1_code_length = _etext_l1 - _stext_l1;
100 if (l1_code_length > L1_CODE_LENGTH)
101 l1_code_length = L1_CODE_LENGTH;
102 /* cannot complain as printk is not available as yet.
103 * But we can continue booting and complain later!
104 */
105
106 /* Copy _stext_l1 to _etext_l1 to L1 instruction SRAM */
107 dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length);
108
109 l1_data_a_length = _ebss_l1 - _sdata_l1;
110 if (l1_data_a_length > L1_DATA_A_LENGTH)
111 l1_data_a_length = L1_DATA_A_LENGTH;
112
113 /* Copy _sdata_l1 to _ebss_l1 to L1 data bank A SRAM */
114 dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length);
115
116 l1_data_b_length = _ebss_b_l1 - _sdata_b_l1;
117 if (l1_data_b_length > L1_DATA_B_LENGTH)
118 l1_data_b_length = L1_DATA_B_LENGTH;
119
120 /* Copy _sdata_b_l1 to _ebss_b_l1 to L1 data bank B SRAM */
121 dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length +
122 l1_data_a_length, l1_data_b_length);
123
124}
125
126/*
127 * Initial parsing of the command line. Currently, we support:
128 * - Controlling the linux memory size: mem=xxx[KMG]
129 * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
130 * $ -> reserved memory is dcacheable
131 * # -> reserved memory is icacheable
132 */
133static __init void parse_cmdline_early(char *cmdline_p)
134{
135 char c = ' ', *to = cmdline_p;
136 unsigned int memsize;
137 for (;;) {
138 if (c == ' ') {
139
140 if (!memcmp(to, "mem=", 4)) {
141 to += 4;
142 memsize = memparse(to, &to);
143 if (memsize)
144 _ramend = memsize;
145
146 } else if (!memcmp(to, "max_mem=", 8)) {
147 to += 8;
148 memsize = memparse(to, &to);
149 if (memsize) {
150 physical_mem_end = memsize;
151 if (*to != ' ') {
152 if (*to == '$'
153 || *(to + 1) == '$')
154 reserved_mem_dcache_on =
155 1;
156 if (*to == '#'
157 || *(to + 1) == '#')
158 reserved_mem_icache_on =
159 1;
160 }
161 }
162 }
163
164 }
165 c = *(to++);
166 if (!c)
167 break;
168 }
169}
170
171void __init setup_arch(char **cmdline_p)
172{
173 int bootmap_size;
174 unsigned long l1_length, sclk, cclk;
175#ifdef CONFIG_MTD_UCLINUX
176 unsigned long mtd_phys = 0;
177#endif
178
6e537e93
MH		 179#ifdef CONFIG_DUMMY_CONSOLE
180 conswitchp = &dummy_con;
181#endif
1394f032
BW		 182 cclk = get_cclk();
183 sclk = get_sclk();
184
185#if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273)
186 if (cclk == sclk)
187 panic("ANOMALY 05000273, SCLK can not be same as CCLK");
188#endif
189
190#if defined(ANOMALY_05000266)
191 bfin_read_IMDMA_D0_IRQ_STATUS();
192 bfin_read_IMDMA_D1_IRQ_STATUS();
193#endif
194
195#ifdef DEBUG_SERIAL_EARLY_INIT
196 bfin_console_init(); /* early console registration */
197 /* this give a chance to get printk() working before crash. */
198#endif
199
200#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
201 /* we need to initialize the Flashrom device here since we might
202 * do things with flash early on in the boot
203 */
204 flash_probe();
205#endif
206
207#if defined(CONFIG_CMDLINE_BOOL)
1394f032
BW		 208 strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
209 command_line[sizeof(command_line) - 1] = 0;
210#endif
211
212 /* Keep a copy of command line */
213 *cmdline_p = &command_line[0];
214 memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
5e10b4a6 215 boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
1394f032
BW		 216
217 /* setup memory defaults from the user config */
218 physical_mem_end = 0;
219 _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
220
221 parse_cmdline_early(&command_line[0]);
222
223 if (physical_mem_end == 0)
224 physical_mem_end = _ramend;
225
226 /* by now the stack is part of the init task */
227 memory_end = _ramend - DMA_UNCACHED_REGION;
228
229 _ramstart = (unsigned long)__bss_stop;
230 memory_start = PAGE_ALIGN(_ramstart);
231
232#if defined(CONFIG_MTD_UCLINUX)
233 /* generic memory mapped MTD driver */
234 memory_mtd_end = memory_end;
235
236 mtd_phys = _ramstart;
237 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
238
239# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
240 if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
241 mtd_size =
242 PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
243# endif
244
245# if defined(CONFIG_CRAMFS)
246 if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
247 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
248# endif
249
250# if defined(CONFIG_ROMFS_FS)
251 if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
252 && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
253 mtd_size =
254 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
255# if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
256 /* Due to a Hardware Anomaly we need to limit the size of usable
257 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
258 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
259 */
260# if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
261 if (memory_end >= 56 * 1024 * 1024)
262 memory_end = 56 * 1024 * 1024;
263# else
264 if (memory_end >= 60 * 1024 * 1024)
265 memory_end = 60 * 1024 * 1024;
266# endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
267# endif /* ANOMALY_05000263 */
268# endif /* CONFIG_ROMFS_FS */
269
270 memory_end -= mtd_size;
271
272 if (mtd_size == 0) {
273 console_init();
274 panic("Don't boot kernel without rootfs attached.\n");
275 }
276
277 /* Relocate MTD image to the top of memory after the uncached memory area */
278 dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
279
280 memory_mtd_start = memory_end;
281 _ebss = memory_mtd_start; /* define _ebss for compatible */
282#endif /* CONFIG_MTD_UCLINUX */
283
284#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
285 /* Due to a Hardware Anomaly we need to limit the size of usable
286 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
287 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
288 */
289#if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
290 if (memory_end >= 56 * 1024 * 1024)
291 memory_end = 56 * 1024 * 1024;
292#else
293 if (memory_end >= 60 * 1024 * 1024)
294 memory_end = 60 * 1024 * 1024;
295#endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
296 printk(KERN_NOTICE "Warning: limiting memory to %liMB due to hardware anomaly 05000263\n", memory_end >> 20);
297#endif /* ANOMALY_05000263 */
298
299#if !defined(CONFIG_MTD_UCLINUX)
300 memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
301#endif
302 init_mm.start_code = (unsigned long)_stext;
303 init_mm.end_code = (unsigned long)_etext;
304 init_mm.end_data = (unsigned long)_edata;
305 init_mm.brk = (unsigned long)0;
306
307 init_leds();
308
309 printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
de3025f4
JZ		 310 if (bfin_compiled_revid() == 0xffff)
311 printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
312 else if (bfin_compiled_revid() == -1)
313 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
314 else
315 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
316 if (bfin_revid() != bfin_compiled_revid()) {
317 if (bfin_compiled_revid() == -1)
318 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
319 bfin_revid());
320 else if (bfin_compiled_revid() != 0xffff)
321 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
322 bfin_compiled_revid(), bfin_revid());
323 }
1394f032
BW		 324 if (bfin_revid() < SUPPORTED_REVID)
325 printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
326 CPU, bfin_revid());
327 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
328
329 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
330 cclk / 1000000, sclk / 1000000);
331
332#if defined(ANOMALY_05000273)
333 if ((cclk >> 1) <= sclk)
334 printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
335#endif
336
337 printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
338 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
339
340 printk(KERN_INFO "Memory map:\n"
341 KERN_INFO " text = 0x%p-0x%p\n"
86b73c8c 342 KERN_INFO " rodata = 0x%p-0x%p\n"
1394f032 343 KERN_INFO " data = 0x%p-0x%p\n"
86b73c8c
RG		 344 KERN_INFO " stack = 0x%p-0x%p\n"
345 KERN_INFO " init = 0x%p-0x%p\n"
1394f032
BW		 346 KERN_INFO " bss = 0x%p-0x%p\n"
347 KERN_INFO " available = 0x%p-0x%p\n"
348#ifdef CONFIG_MTD_UCLINUX
349 KERN_INFO " rootfs = 0x%p-0x%p\n"
350#endif
351#if DMA_UNCACHED_REGION > 0
352 KERN_INFO " DMA Zone = 0x%p-0x%p\n"
353#endif
354 , _stext, _etext,
86b73c8c 355 __start_rodata, __end_rodata,
1394f032
BW		 356 _sdata, _edata,
357 (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000),
86b73c8c 358 __init_begin, __init_end,
1394f032
BW		 359 __bss_start, __bss_stop,
360 (void*)_ramstart, (void*)memory_end
361#ifdef CONFIG_MTD_UCLINUX
362 , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size)
363#endif
364#if DMA_UNCACHED_REGION > 0
365 , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend)
366#endif
367 );
368
369 /*
370 * give all the memory to the bootmap allocator, tell it to put the
371 * boot mem_map at the start of memory
372 */
373 bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT, /* map goes here */
374 PAGE_OFFSET >> PAGE_SHIFT,
375 memory_end >> PAGE_SHIFT);
376 /*
377 * free the usable memory, we have to make sure we do not free
378 * the bootmem bitmap so we then reserve it after freeing it :-)
379 */
380 free_bootmem(memory_start, memory_end - memory_start);
381
382 reserve_bootmem(memory_start, bootmap_size);
383 /*
384 * get kmalloc into gear
385 */
386 paging_init();
387
388 /* check the size of the l1 area */
389 l1_length = _etext_l1 - _stext_l1;
390 if (l1_length > L1_CODE_LENGTH)
391 panic("L1 memory overflow\n");
392
393 l1_length = _ebss_l1 - _sdata_l1;
394 if (l1_length > L1_DATA_A_LENGTH)
395 panic("L1 memory overflow\n");
396
a9c59c27
MF		 397#ifdef BF561_FAMILY
398 _bfin_swrst = bfin_read_SICA_SWRST();
399#else
400 _bfin_swrst = bfin_read_SWRST();
401#endif
402
1394f032
BW		 403 bf53x_cache_init();
404
1394f032
BW		 405 printk(KERN_INFO "Hardware Trace Enabled\n");
406 bfin_write_TBUFCTL(0x03);
407}
408
1394f032
BW		 409static int __init topology_init(void)
410{
411#if defined (CONFIG_BF561)
c0fc525d 412 static struct cpu cpu[2];
1394f032
BW		 413 register_cpu(&cpu[0], 0);
414 register_cpu(&cpu[1], 1);
415 return 0;
416#else
c0fc525d 417 static struct cpu cpu[1];
1394f032
BW		 418 return register_cpu(cpu, 0);
419#endif
420}
421
422subsys_initcall(topology_init);
423
424#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
52a07812 425static u16 __init lock_kernel_check(u32 start, u32 end)
1394f032
BW		 426{
427 if ((start <= (u32) _stext && end >= (u32) _end)
428 || (start >= (u32) _stext && end <= (u32) _end))
429 return IN_KERNEL;
430 return 0;
431}
432
433static unsigned short __init
434fill_cplbtab(struct cplb_tab *table,
435 unsigned long start, unsigned long end,
436 unsigned long block_size, unsigned long cplb_data)
437{
438 int i;
439
440 switch (block_size) {
441 case SIZE_4M:
442 i = 3;
443 break;
444 case SIZE_1M:
445 i = 2;
446 break;
447 case SIZE_4K:
448 i = 1;
449 break;
450 case SIZE_1K:
451 default:
452 i = 0;
453 break;
454 }
455
456 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
457
458 while ((start < end) && (table->pos < table->size)) {
459
460 table->tab[table->pos++] = start;
461
462 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
463 table->tab[table->pos++] =
464 cplb_data | CPLB_LOCK | CPLB_DIRTY;
465 else
466 table->tab[table->pos++] = cplb_data;
467
468 start += block_size;
469 }
470 return 0;
471}
472
473static unsigned short __init
474close_cplbtab(struct cplb_tab *table)
475{
476
477 while (table->pos < table->size) {
478
479 table->tab[table->pos++] = 0;
480 table->tab[table->pos++] = 0; /* !CPLB_VALID */
481 }
482 return 0;
483}
484
5af4c2b3
AL		 485/* helper function */
486static void __fill_code_cplbtab(struct cplb_tab *t, int i,
487 u32 a_start, u32 a_end)
488{
489 if (cplb_data[i].psize) {
490 fill_cplbtab(t,
491 cplb_data[i].start,
492 cplb_data[i].end,
493 cplb_data[i].psize,
494 cplb_data[i].i_conf);
495 } else {
496#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
497 if (i == SDRAM_KERN) {
498 fill_cplbtab(t,
499 cplb_data[i].start,
500 cplb_data[i].end,
501 SIZE_4M,
502 cplb_data[i].i_conf);
24a07a12 503 } else
5af4c2b3 504#endif
24a07a12 505 {
5af4c2b3
AL		 506 fill_cplbtab(t,
507 cplb_data[i].start,
508 a_start,
509 SIZE_1M,
510 cplb_data[i].i_conf);
511 fill_cplbtab(t,
512 a_start,
513 a_end,
514 SIZE_4M,
515 cplb_data[i].i_conf);
516 fill_cplbtab(t, a_end,
517 cplb_data[i].end,
518 SIZE_1M,
519 cplb_data[i].i_conf);
520 }
521 }
522}
523
524static void __fill_data_cplbtab(struct cplb_tab *t, int i,
525 u32 a_start, u32 a_end)
526{
527 if (cplb_data[i].psize) {
528 fill_cplbtab(t,
529 cplb_data[i].start,
530 cplb_data[i].end,
531 cplb_data[i].psize,
532 cplb_data[i].d_conf);
533 } else {
534 fill_cplbtab(t,
535 cplb_data[i].start,
536 a_start, SIZE_1M,
537 cplb_data[i].d_conf);
538 fill_cplbtab(t, a_start,
539 a_end, SIZE_4M,
540 cplb_data[i].d_conf);
541 fill_cplbtab(t, a_end,
542 cplb_data[i].end,
543 SIZE_1M,
544 cplb_data[i].d_conf);
545 }
546}
1394f032
BW		 547static void __init generate_cpl_tables(void)
548{
549
550 u16 i, j, process;
551 u32 a_start, a_end, as, ae, as_1m;
552
553 struct cplb_tab *t_i = NULL;
554 struct cplb_tab *t_d = NULL;
555 struct s_cplb cplb;
556
557 cplb.init_i.size = MAX_CPLBS;
558 cplb.init_d.size = MAX_CPLBS;
559 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
560 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
561
562 cplb.init_i.pos = 0;
563 cplb.init_d.pos = 0;
564 cplb.switch_i.pos = 0;
565 cplb.switch_d.pos = 0;
566
567 cplb.init_i.tab = icplb_table;
568 cplb.init_d.tab = dcplb_table;
569 cplb.switch_i.tab = ipdt_table;
570 cplb.switch_d.tab = dpdt_table;
571
572 cplb_data[SDRAM_KERN].end = memory_end;
573
574#ifdef CONFIG_MTD_UCLINUX
575 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
576 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
577 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
578# if defined(CONFIG_ROMFS_FS)
579 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
580
581 /*
582 * The ROMFS_FS size is often not multiple of 1MB.
583 * This can cause multiple CPLB sets covering the same memory area.
584 * This will then cause multiple CPLB hit exceptions.
585 * Workaround: We ensure a contiguous memory area by extending the kernel
586 * memory section over the mtd section.
587 * For ROMFS_FS memory must be covered with ICPLBs anyways.
588 * So there is no difference between kernel and mtd memory setup.
589 */
590
591 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
592 cplb_data[SDRAM_RAM_MTD].valid = 0;
593
594# endif
595#else
596 cplb_data[SDRAM_RAM_MTD].valid = 0;
597#endif
598
599 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
600 cplb_data[SDRAM_DMAZ].end = _ramend;
601
602 cplb_data[RES_MEM].start = _ramend;
603 cplb_data[RES_MEM].end = physical_mem_end;
604
605 if (reserved_mem_dcache_on)
606 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
607 else
608 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
609
610 if (reserved_mem_icache_on)
611 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
612 else
613 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
614
615 for (i = ZERO_P; i <= L2_MEM; i++) {
5af4c2b3
AL		 616 if (!cplb_data[i].valid)
617 continue;
1394f032 618
5af4c2b3 619 as_1m = cplb_data[i].start % SIZE_1M;
1394f032 620
5af4c2b3
AL		 621 /*
622 * We need to make sure all sections are properly 1M aligned
623 * However between Kernel Memory and the Kernel mtd section,
624 * depending on the rootfs size, there can be overlapping
625 * memory areas.
626 */
1394f032 627
5af4c2b3 628 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
1394f032 629#ifdef CONFIG_MTD_UCLINUX
5af4c2b3
AL		 630 if (i == SDRAM_RAM_MTD) {
631 if ((cplb_data[SDRAM_KERN].end + 1) >
632 cplb_data[SDRAM_RAM_MTD].start)
633 cplb_data[SDRAM_RAM_MTD].start =
634 (cplb_data[i].start &
635 (-2*SIZE_1M)) + SIZE_1M;
636 else
637 cplb_data[SDRAM_RAM_MTD].start =
638 (cplb_data[i].start &
639 (-2*SIZE_1M));
640 } else
1394f032 641#endif
5af4c2b3
AL		 642 printk(KERN_WARNING
643 "Unaligned Start of %s at 0x%X\n",
644 cplb_data[i].name, cplb_data[i].start);
645 }
1394f032 646
5af4c2b3
AL		 647 as = cplb_data[i].start % SIZE_4M;
648 ae = cplb_data[i].end % SIZE_4M;
1394f032 649
5af4c2b3
AL		 650 if (as)
651 a_start = cplb_data[i].start + (SIZE_4M - (as));
652 else
653 a_start = cplb_data[i].start;
1394f032 654
5af4c2b3 655 a_end = cplb_data[i].end - ae;
1394f032 656
5af4c2b3 657 for (j = INITIAL_T; j <= SWITCH_T; j++) {
1394f032 658
5af4c2b3
AL		 659 switch (j) {
660 case INITIAL_T:
661 if (cplb_data[i].attr & INITIAL_T) {
662 t_i = &cplb.init_i;
663 t_d = &cplb.init_d;
664 process = 1;
665 } else
666 process = 0;
667 break;
668 case SWITCH_T:
669 if (cplb_data[i].attr & SWITCH_T) {
670 t_i = &cplb.switch_i;
671 t_d = &cplb.switch_d;
672 process = 1;
673 } else
674 process = 0;
675 break;
676 default:
677 process = 0;
678 break;
1394f032
BW		 679 }
680
5af4c2b3
AL		 681 if (!process)
682 continue;
683 if (cplb_data[i].attr & I_CPLB)
684 __fill_code_cplbtab(t_i, i, a_start, a_end);
685
686 if (cplb_data[i].attr & D_CPLB)
687 __fill_data_cplbtab(t_d, i, a_start, a_end);
1394f032
BW		 688 }
689 }
690
691/* close tables */
692
693 close_cplbtab(&cplb.init_i);
694 close_cplbtab(&cplb.init_d);
695
696 cplb.init_i.tab[cplb.init_i.pos] = -1;
697 cplb.init_d.tab[cplb.init_d.pos] = -1;
698 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
699 cplb.switch_d.tab[cplb.switch_d.pos] = -1;
700
701}
702
703#endif
704
52a07812 705static u_long get_vco(void)
1394f032
BW		 706{
707 u_long msel;
708 u_long vco;
709
710 msel = (bfin_read_PLL_CTL() >> 9) & 0x3F;
711 if (0 == msel)
712 msel = 64;
713
714 vco = CONFIG_CLKIN_HZ;
715 vco >>= (1 & bfin_read_PLL_CTL()); /* DF bit */
716 vco = msel * vco;
717 return vco;
718}
719
720/*Get the Core clock*/
721u_long get_cclk(void)
722{
723 u_long csel, ssel;
724 if (bfin_read_PLL_STAT() & 0x1)
725 return CONFIG_CLKIN_HZ;
726
727 ssel = bfin_read_PLL_DIV();
728 csel = ((ssel >> 4) & 0x03);
729 ssel &= 0xf;
730 if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
731 return get_vco() / ssel;
732 return get_vco() >> csel;
733}
734
735EXPORT_SYMBOL(get_cclk);
736
737/* Get the System clock */
738u_long get_sclk(void)
739{
740 u_long ssel;
741
742 if (bfin_read_PLL_STAT() & 0x1)
743 return CONFIG_CLKIN_HZ;
744
745 ssel = (bfin_read_PLL_DIV() & 0xf);
746 if (0 == ssel) {
747 printk(KERN_WARNING "Invalid System Clock\n");
748 ssel = 1;
749 }
750
751 return get_vco() / ssel;
752}
753
754EXPORT_SYMBOL(get_sclk);
755
756/*
757 * Get CPU information for use by the procfs.
758 */
759static int show_cpuinfo(struct seq_file *m, void *v)
760{
761 char *cpu, *mmu, *fpu, *name;
762 uint32_t revid;
763
764 u_long cclk = 0, sclk = 0;
765 u_int dcache_size = 0, dsup_banks = 0;
766
767 cpu = CPU;
768 mmu = "none";
769 fpu = "none";
770 revid = bfin_revid();
771 name = bfin_board_name;
772
773 cclk = get_cclk();
774 sclk = get_sclk();
775
776 seq_printf(m, "CPU:\t\tADSP-%s Rev. 0.%d\n"
777 "MMU:\t\t%s\n"
778 "FPU:\t\t%s\n"
779 "Core Clock:\t%9lu Hz\n"
780 "System Clock:\t%9lu Hz\n"
781 "BogoMips:\t%lu.%02lu\n"
782 "Calibration:\t%lu loops\n",
783 cpu, revid, mmu, fpu,
784 cclk,
785 sclk,
786 (loops_per_jiffy * HZ) / 500000,
787 ((loops_per_jiffy * HZ) / 5000) % 100,
788 (loops_per_jiffy * HZ));
789 seq_printf(m, "Board Name:\t%s\n", name);
790 seq_printf(m, "Board Memory:\t%ld MB\n", physical_mem_end >> 20);
791 seq_printf(m, "Kernel Memory:\t%ld MB\n", (unsigned long)_ramend >> 20);
792 if (bfin_read_IMEM_CONTROL() & (ENICPLB | IMC))
793 seq_printf(m, "I-CACHE:\tON\n");
794 else
795 seq_printf(m, "I-CACHE:\tOFF\n");
796 if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
797 seq_printf(m, "D-CACHE:\tON"
798#if defined CONFIG_BLKFIN_WB
799 " (write-back)"
800#elif defined CONFIG_BLKFIN_WT
801 " (write-through)"
802#endif
803 "\n");
804 else
805 seq_printf(m, "D-CACHE:\tOFF\n");
806
807
808 switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
809 case ACACHE_BSRAM:
810 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
811 dcache_size = 16;
812 dsup_banks = 1;
813 break;
814 case ACACHE_BCACHE:
815 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
816 dcache_size = 32;
817 dsup_banks = 2;
818 break;
819 case ASRAM_BSRAM:
820 seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
821 dcache_size = 0;
822 dsup_banks = 0;
823 break;
824 default:
825 break;
826 }
827
828
829 seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
830 seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
831 seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
832 BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
833 seq_printf(m,
834 "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
835 dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
836 BLKFIN_DLINES);
837#ifdef CONFIG_BLKFIN_CACHE_LOCK
838 switch (read_iloc()) {
839 case WAY0_L:
840 seq_printf(m, "Way0 Locked-Down\n");
841 break;
842 case WAY1_L:
843 seq_printf(m, "Way1 Locked-Down\n");
844 break;
845 case WAY01_L:
846 seq_printf(m, "Way0,Way1 Locked-Down\n");
847 break;
848 case WAY2_L:
849 seq_printf(m, "Way2 Locked-Down\n");
850 break;
851 case WAY02_L:
852 seq_printf(m, "Way0,Way2 Locked-Down\n");
853 break;
854 case WAY12_L:
855 seq_printf(m, "Way1,Way2 Locked-Down\n");
856 break;
857 case WAY012_L:
858 seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
859 break;
860 case WAY3_L:
861 seq_printf(m, "Way3 Locked-Down\n");
862 break;
863 case WAY03_L:
864 seq_printf(m, "Way0,Way3 Locked-Down\n");
865 break;
866 case WAY13_L:
867 seq_printf(m, "Way1,Way3 Locked-Down\n");
868 break;
869 case WAY013_L:
870 seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
871 break;
872 case WAY32_L:
873 seq_printf(m, "Way3,Way2 Locked-Down\n");
874 break;
875 case WAY320_L:
876 seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
877 break;
878 case WAY321_L:
879 seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
880 break;
881 case WAYALL_L:
882 seq_printf(m, "All Ways are locked\n");
883 break;
884 default:
885 seq_printf(m, "No Ways are locked\n");
886 }
887#endif
888 return 0;
889}
890
891static void *c_start(struct seq_file *m, loff_t *pos)
892{
893 return *pos < NR_CPUS ? ((void *)0x12345678) : NULL;
894}
895
896static void *c_next(struct seq_file *m, void *v, loff_t *pos)
897{
898 ++*pos;
899 return c_start(m, pos);
900}
901
902static void c_stop(struct seq_file *m, void *v)
903{
904}
905
906struct seq_operations cpuinfo_op = {
907 .start = c_start,
908 .next = c_next,
909 .stop = c_stop,
910 .show = show_cpuinfo,
911};
912
5e10b4a6 913void __init cmdline_init(const char *r0)
1394f032
BW		 914{
915 if (r0)
52a07812 916 strncpy(command_line, r0, COMMAND_LINE_SIZE);
1394f032 917}
Linux kernel - Deliverables
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