Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / blackfin / kernel / vmlinux.lds.S
CommitLineData
1394f032 1/*
96f1050d 2 * Copyright 2004-2009 Analog Devices Inc.
1394f032 3 *
96f1050d 4 * Licensed under the GPL-2 or later
1394f032
BW
5 */
6
1394f032
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7#include <asm-generic/vmlinux.lds.h>
8#include <asm/mem_map.h>
520473b0 9#include <asm/page.h>
0fa63ad7 10#include <asm/thread_info.h>
1394f032 11
1394f032
BW
12OUTPUT_FORMAT("elf32-bfin")
13ENTRY(__start)
14_jiffies = _jiffies_64;
15
1394f032
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16SECTIONS
17{
d86bfb16 18#ifdef CONFIG_RAMKERNEL
1394f032 19 . = CONFIG_BOOT_LOAD;
d86bfb16
BS
20#else
21 . = CONFIG_ROM_BASE;
22#endif
23
b7627acc
MF
24 /* Neither the text, ro_data or bss section need to be aligned
25 * So pack them back to back
26 */
1394f032
BW
27 .text :
28 {
de6a9520
MF
29 __text = .;
30 _text = .;
31 __stext = .;
7664709b 32 TEXT_TEXT
b8d0c778 33#ifndef CONFIG_SCHEDULE_L1
1394f032 34 SCHED_TEXT
b8d0c778 35#endif
de6a9520 36 LOCK_TEXT
1ee76d7e 37 IRQENTRY_TEXT
be7635e7 38 SOFTIRQENTRY_TEXT
27d875f2 39 KPROBES_TEXT
d86bfb16
BS
40#ifdef CONFIG_ROMKERNEL
41 __sinittext = .;
42 INIT_TEXT
43 __einittext = .;
44 EXIT_TEXT
45#endif
27d875f2 46 *(.text.*)
de6a9520
MF
47 *(.fixup)
48
bc6e0fa1
MF
49#if !L1_CODE_LENGTH
50 *(.l1.text)
51#endif
1394f032 52 __etext = .;
de6a9520
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53 }
54
d49e8e7e 55 EXCEPTION_TABLE(4)
6f985294
BS
56 NOTES
57
b7627acc
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58 /* Just in case the first read only is a 32-bit access */
59 RO_DATA(4)
d86bfb16 60 __rodata_end = .;
b7627acc 61
d86bfb16
BS
62#ifdef CONFIG_ROMKERNEL
63 . = CONFIG_BOOT_LOAD;
64 .bss : AT(__rodata_end)
65#else
b7627acc 66 .bss :
d86bfb16 67#endif
b7627acc
MF
68 {
69 . = ALIGN(4);
70 ___bss_start = .;
71 *(.bss .bss.*)
72 *(COMMON)
bc6e0fa1
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73#if !L1_DATA_A_LENGTH
74 *(.l1.bss)
75#endif
76#if !L1_DATA_B_LENGTH
77 *(.l1.bss.B)
78#endif
13752046 79 . = ALIGN(4);
b7627acc
MF
80 ___bss_stop = .;
81 }
de6a9520 82
d86bfb16
BS
83#if defined(CONFIG_ROMKERNEL)
84 .data : AT(LOADADDR(.bss) + SIZEOF(.bss))
85#else
de6a9520 86 .data :
d86bfb16 87#endif
de6a9520
MF
88 {
89 __sdata = .;
b7627acc 90 /* This gets done first, so the glob doesn't suck it in */
4a5e3513 91 CACHELINE_ALIGNED_DATA(32)
de6a9520 92
b85b82d9
SZ
93#if !L1_DATA_A_LENGTH
94 . = ALIGN(32);
95 *(.data_l1.cacheline_aligned)
bc6e0fa1
MF
96 *(.l1.data)
97#endif
98#if !L1_DATA_B_LENGTH
99 *(.l1.data.B)
b85b82d9 100#endif
07aa7be5 101#if !L2_LENGTH
262c3825
SZ
102 . = ALIGN(32);
103 *(.data_l2.cacheline_aligned)
104 *(.l2.data)
105#endif
b85b82d9 106
27d875f2 107 DATA_DATA
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108 CONSTRUCTORS
109
4a5e3513 110 INIT_TASK_DATA(THREAD_SIZE)
b7627acc 111
de6a9520
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112 __edata = .;
113 }
d86bfb16
BS
114 __data_lma = LOADADDR(.data);
115 __data_len = SIZEOF(.data);
1394f032 116
b7627acc
MF
117 /* The init section should be last, so when we free it, it goes into
118 * the general memory pool, and (hopefully) will decrease fragmentation
119 * a tiny bit. The init section has a _requirement_ that it be
120 * PAGE_SIZE aligned
121 */
122 . = ALIGN(PAGE_SIZE);
de6a9520 123 ___init_begin = .;
27d875f2 124
d86bfb16 125#ifdef CONFIG_RAMKERNEL
4a5e3513 126 INIT_TEXT_SECTION(PAGE_SIZE)
70f12567 127
0afc272c 128 /* We have to discard exit text and such at runtime, not link time, to
70f12567 129 * handle embedded cross-section references (alt instructions, bug
0afc272c
JZ
130 * table, eh_frame, etc...). We need all of our .text up front and
131 * .data after it for PCREL call issues.
70f12567
MF
132 */
133 .exit.text :
134 {
135 EXIT_TEXT
136 }
0afc272c
JZ
137
138 . = ALIGN(16);
139 INIT_DATA_SECTION(16)
0415b00d 140 PERCPU_SECTION(32)
0afc272c 141
70f12567
MF
142 .exit.data :
143 {
144 EXIT_DATA
145 }
146
4a5e3513 147 .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data))
d86bfb16 148#else
b76f9823 149 .init.data : AT(__data_lma + __data_len + 32)
d86bfb16
BS
150 {
151 __sinitdata = .;
152 INIT_DATA
153 INIT_SETUP(16)
154 INIT_CALLS
155 CON_INITCALL
156 SECURITY_INITCALL
157 INIT_RAM_FS
158
353470cc 159 . = ALIGN(PAGE_SIZE);
d86bfb16 160 ___per_cpu_load = .;
d6cb2e3a 161 PERCPU_INPUT(32)
d86bfb16
BS
162
163 EXIT_DATA
164 __einitdata = .;
165 }
166 __init_data_lma = LOADADDR(.init.data);
167 __init_data_len = SIZEOF(.init.data);
168 __init_data_end = .;
169
170 .text_l1 L1_CODE_START : AT(__init_data_lma + __init_data_len)
171#endif
1394f032
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172 {
173 . = ALIGN(4);
de6a9520 174 __stext_l1 = .;
c6345ab1 175 *(.l1.text.head)
bc6e0fa1 176 *(.l1.text)
b8d0c778
RG
177#ifdef CONFIG_SCHEDULE_L1
178 SCHED_TEXT
179#endif
1394f032 180 . = ALIGN(4);
de6a9520
MF
181 __etext_l1 = .;
182 }
5cd82a6d
MF
183 __text_l1_lma = LOADADDR(.text_l1);
184 __text_l1_len = SIZEOF(.text_l1);
185 ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!")
1394f032 186
5cd82a6d 187 .data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len)
1394f032
BW
188 {
189 . = ALIGN(4);
de6a9520 190 __sdata_l1 = .;
bc6e0fa1 191 *(.l1.data)
de6a9520 192 __edata_l1 = .;
1394f032 193
1394f032 194 . = ALIGN(32);
bc6e0fa1 195 *(.data_l1.cacheline_aligned)
1394f032 196
262c3825
SZ
197 . = ALIGN(4);
198 __sbss_l1 = .;
199 *(.l1.bss)
1394f032 200 . = ALIGN(4);
de6a9520
MF
201 __ebss_l1 = .;
202 }
5cd82a6d
MF
203 __data_l1_lma = LOADADDR(.data_l1);
204 __data_l1_len = SIZEOF(.data_l1);
205 ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!")
de6a9520 206
5cd82a6d 207 .data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len)
1394f032
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208 {
209 . = ALIGN(4);
210 __sdata_b_l1 = .;
bc6e0fa1 211 *(.l1.data.B)
1394f032
BW
212 __edata_b_l1 = .;
213
214 . = ALIGN(4);
215 __sbss_b_l1 = .;
bc6e0fa1 216 *(.l1.bss.B)
1394f032
BW
217 . = ALIGN(4);
218 __ebss_b_l1 = .;
de6a9520 219 }
5cd82a6d
MF
220 __data_b_l1_lma = LOADADDR(.data_b_l1);
221 __data_b_l1_len = SIZEOF(.data_b_l1);
222 ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!")
262c3825 223
5cd82a6d 224 .text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len)
262c3825
SZ
225 {
226 . = ALIGN(4);
227 __stext_l2 = .;
07aa7be5 228 *(.l2.text)
262c3825
SZ
229 . = ALIGN(4);
230 __etext_l2 = .;
231
232 . = ALIGN(4);
233 __sdata_l2 = .;
07aa7be5 234 *(.l2.data)
262c3825
SZ
235 __edata_l2 = .;
236
237 . = ALIGN(32);
238 *(.data_l2.cacheline_aligned)
239
240 . = ALIGN(4);
241 __sbss_l2 = .;
07aa7be5 242 *(.l2.bss)
262c3825
SZ
243 . = ALIGN(4);
244 __ebss_l2 = .;
245 }
5cd82a6d
MF
246 __l2_lma = LOADADDR(.text_data_l2);
247 __l2_len = SIZEOF(.text_data_l2);
248 ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!")
6f985294 249
36208059
MF
250 /* Force trailing alignment of our init section so that when we
251 * free our init memory, we don't leave behind a partial page.
252 */
d86bfb16 253#ifdef CONFIG_RAMKERNEL
5cd82a6d 254 . = __l2_lma + __l2_len;
d86bfb16
BS
255#else
256 . = __init_data_end;
257#endif
36208059
MF
258 . = ALIGN(PAGE_SIZE);
259 ___init_end = .;
260
b7627acc 261 __end =.;
de6a9520 262
c11b5776
MF
263 STABS_DEBUG
264
265 DWARF_DEBUG
266
023bf6f1 267 DISCARDS
1394f032 268}
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