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Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux...
[deliverable/linux.git] / arch / blackfin / mach-bf518 / boards / ezbrd.c
CommitLineData
2f6f4bcd
BW		 1/*
2 * File: arch/blackfin/mach-bf518/boards/ezbrd.c
3 * Based on: arch/blackfin/mach-bf527/boards/ezbrd.c
4 * Author: Bryan Wu <cooloney@kernel.org>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2008 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/mtd/physmap.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38
39#include <linux/i2c.h>
40#include <linux/irq.h>
41#include <linux/interrupt.h>
42#include <asm/dma.h>
43#include <asm/bfin5xx_spi.h>
44#include <asm/reboot.h>
45#include <asm/portmux.h>
46#include <asm/dpmc.h>
501674a5 47#include <asm/bfin_sdh.h>
2f6f4bcd 48#include <linux/spi/ad7877.h>
65319628 49#include <net/dsa.h>
2f6f4bcd
BW		 50
51/*
52 * Name the Board for the /proc/cpuinfo
53 */
fe85cad2 54const char bfin_board_name[] = "ADI BF518F-EZBRD";
2f6f4bcd
BW		 55
56/*
57 * Driver needs to know address, irq and flag pin.
58 */
59
60#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
61static struct mtd_partition ezbrd_partitions[] = {
62 {
63 .name = "bootloader(nor)",
64 .size = 0x40000,
65 .offset = 0,
66 }, {
67 .name = "linux kernel(nor)",
68 .size = 0x1C0000,
69 .offset = MTDPART_OFS_APPEND,
70 }, {
71 .name = "file system(nor)",
72 .size = MTDPART_SIZ_FULL,
73 .offset = MTDPART_OFS_APPEND,
74 }
75};
76
77static struct physmap_flash_data ezbrd_flash_data = {
78 .width = 2,
79 .parts = ezbrd_partitions,
80 .nr_parts = ARRAY_SIZE(ezbrd_partitions),
81};
82
83static struct resource ezbrd_flash_resource = {
84 .start = 0x20000000,
ee0263cc
GY		 85#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
86 .end = 0x202fffff,
87#else
2f6f4bcd 88 .end = 0x203fffff,
ee0263cc 89#endif
2f6f4bcd
BW		 90 .flags = IORESOURCE_MEM,
91};
92
93static struct platform_device ezbrd_flash_device = {
94 .name = "physmap-flash",
95 .id = 0,
96 .dev = {
97 .platform_data = &ezbrd_flash_data,
98 },
99 .num_resources = 1,
100 .resource = &ezbrd_flash_resource,
101};
102#endif
103
104#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
105static struct platform_device rtc_device = {
106 .name = "rtc-bfin",
107 .id = -1,
108};
109#endif
110
111#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 112static struct platform_device bfin_mii_bus = {
113 .name = "bfin_mii_bus",
114};
115
2f6f4bcd
BW		 116static struct platform_device bfin_mac_device = {
117 .name = "bfin_mac",
65319628
GY		 118 .dev.platform_data = &bfin_mii_bus,
119};
65319628
GY		 120
121#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
2780cd64 122static struct dsa_chip_data ksz8893m_switch_chip_data = {
65319628 123 .mii_bus = &bfin_mii_bus.dev,
2780cd64
MF		 124 .port_names = {
125 NULL,
126 "eth%d",
127 "eth%d",
128 "cpu",
129 },
130};
131static struct dsa_platform_data ksz8893m_switch_data = {
132 .nr_chips = 1,
65319628 133 .netdev = &bfin_mac_device.dev,
2780cd64 134 .chip = &ksz8893m_switch_chip_data,
65319628
GY		 135};
136
137static struct platform_device ksz8893m_switch_device = {
138 .name = "dsa",
139 .id = 0,
140 .num_resources = 0,
141 .dev.platform_data = &ksz8893m_switch_data,
2f6f4bcd
BW		 142};
143#endif
c19577e3 144#endif
2f6f4bcd
BW		 145
146#if defined(CONFIG_MTD_M25P80) \
147 || defined(CONFIG_MTD_M25P80_MODULE)
148static struct mtd_partition bfin_spi_flash_partitions[] = {
149 {
150 .name = "bootloader(spi)",
151 .size = 0x00040000,
152 .offset = 0,
153 .mask_flags = MTD_CAP_ROM
154 }, {
155 .name = "linux kernel(spi)",
156 .size = MTDPART_SIZ_FULL,
157 .offset = MTDPART_OFS_APPEND,
158 }
159};
160
161static struct flash_platform_data bfin_spi_flash_data = {
162 .name = "m25p80",
163 .parts = bfin_spi_flash_partitions,
164 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
165 .type = "m25p16",
166};
167
168/* SPI flash chip (m25p64) */
169static struct bfin5xx_spi_chip spi_flash_chip_info = {
170 .enable_dma = 0, /* use dma transfer with this chip*/
171 .bits_per_word = 8,
172};
173#endif
174
a261eec0
MF		 175#if defined(CONFIG_BFIN_SPI_ADC) \
176 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
2f6f4bcd
BW		 177/* SPI ADC chip */
178static struct bfin5xx_spi_chip spi_adc_chip_info = {
179 .enable_dma = 1, /* use dma transfer with this chip*/
180 .bits_per_word = 16,
181};
182#endif
183
c19577e3 184#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 185#if defined(CONFIG_NET_DSA_KSZ8893M) \
186 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
187/* SPI SWITCH CHIP */
188static struct bfin5xx_spi_chip spi_switch_info = {
189 .enable_dma = 0,
190 .bits_per_word = 8,
191};
192#endif
c19577e3 193#endif
65319628 194
f3f704d3
MH		 195#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
196static struct bfin5xx_spi_chip mmc_spi_chip_info = {
197 .enable_dma = 0,
2f6f4bcd
BW		 198 .bits_per_word = 8,
199};
200#endif
201
2f6f4bcd
BW		 202#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
203static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
204 .enable_dma = 0,
205 .bits_per_word = 16,
206};
207
208static const struct ad7877_platform_data bfin_ad7877_ts_info = {
209 .model = 7877,
210 .vref_delay_usecs = 50, /* internal, no capacitor */
211 .x_plate_ohms = 419,
212 .y_plate_ohms = 486,
213 .pressure_max = 1000,
214 .pressure_min = 0,
215 .stopacq_polarity = 1,
216 .first_conversion_delay = 3,
217 .acquisition_time = 1,
218 .averaging = 1,
219 .pen_down_acc_interval = 1,
220};
221#endif
222
223#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
224 && defined(CONFIG_SND_SOC_WM8731_SPI)
225static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
226 .enable_dma = 0,
227 .bits_per_word = 16,
228};
229#endif
230
231#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
232static struct bfin5xx_spi_chip spidev_chip_info = {
233 .enable_dma = 0,
234 .bits_per_word = 8,
235};
236#endif
237
238static struct spi_board_info bfin_spi_board_info[] __initdata = {
239#if defined(CONFIG_MTD_M25P80) \
240 || defined(CONFIG_MTD_M25P80_MODULE)
241 {
242 /* the modalias must be the same as spi device driver name */
243 .modalias = "m25p80", /* Name of spi_driver for this device */
244 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
245 .bus_num = 0, /* Framework bus number */
a427293f 246 .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */
2f6f4bcd
BW		 247 .platform_data = &bfin_spi_flash_data,
248 .controller_data = &spi_flash_chip_info,
249 .mode = SPI_MODE_3,
250 },
251#endif
252
a261eec0
MF		 253#if defined(CONFIG_BFIN_SPI_ADC) \
254 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
2f6f4bcd
BW		 255 {
256 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
257 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
258 .bus_num = 0, /* Framework bus number */
259 .chip_select = 1, /* Framework chip select. */
260 .platform_data = NULL, /* No spi_driver specific config */
261 .controller_data = &spi_adc_chip_info,
262 },
263#endif
264
c19577e3 265#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 266#if defined(CONFIG_NET_DSA_KSZ8893M) \
267 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
268 {
269 .modalias = "ksz8893m",
270 .max_speed_hz = 5000000,
271 .bus_num = 0,
272 .chip_select = 1,
273 .platform_data = NULL,
274 .controller_data = &spi_switch_info,
275 .mode = SPI_MODE_3,
276 },
277#endif
c19577e3 278#endif
65319628 279
f3f704d3 280#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
2f6f4bcd 281 {
f3f704d3 282 .modalias = "mmc_spi",
2f6f4bcd
BW		 283 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
284 .bus_num = 0,
f3f704d3
MH		 285 .chip_select = 5,
286 .controller_data = &mmc_spi_chip_info,
2f6f4bcd
BW		 287 .mode = SPI_MODE_3,
288 },
289#endif
2f6f4bcd
BW		 290#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
291 {
292 .modalias = "ad7877",
293 .platform_data = &bfin_ad7877_ts_info,
294 .irq = IRQ_PF8,
295 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
296 .bus_num = 0,
297 .chip_select = 2,
298 .controller_data = &spi_ad7877_chip_info,
299 },
300#endif
301#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
302 && defined(CONFIG_SND_SOC_WM8731_SPI)
303 {
304 .modalias = "wm8731",
305 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
306 .bus_num = 0,
307 .chip_select = 5,
308 .controller_data = &spi_wm8731_chip_info,
309 .mode = SPI_MODE_0,
310 },
311#endif
312#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
313 {
314 .modalias = "spidev",
315 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
316 .bus_num = 0,
317 .chip_select = 1,
318 .controller_data = &spidev_chip_info,
319 },
320#endif
321#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
322 {
323 .modalias = "bfin-lq035q1-spi",
324 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
325 .bus_num = 0,
326 .chip_select = 1,
327 .controller_data = &lq035q1_spi_chip_info,
328 .mode = SPI_CPHA | SPI_CPOL,
329 },
330#endif
331};
332
333/* SPI controller data */
334#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
335/* SPI (0) */
336static struct bfin5xx_spi_master bfin_spi0_info = {
337 .num_chipselect = 5,
338 .enable_dma = 1, /* master has the ability to do dma transfer */
339 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
340};
341
342static struct resource bfin_spi0_resource[] = {
343 [0] = {
344 .start = SPI0_REGBASE,
345 .end = SPI0_REGBASE + 0xFF,
346 .flags = IORESOURCE_MEM,
347 },
348 [1] = {
349 .start = CH_SPI0,
350 .end = CH_SPI0,
53122693
YL		 351 .flags = IORESOURCE_DMA,
352 },
353 [2] = {
354 .start = IRQ_SPI0,
355 .end = IRQ_SPI0,
2f6f4bcd
BW		 356 .flags = IORESOURCE_IRQ,
357 },
358};
359
360static struct platform_device bfin_spi0_device = {
361 .name = "bfin-spi",
362 .id = 0, /* Bus number */
363 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
364 .resource = bfin_spi0_resource,
365 .dev = {
366 .platform_data = &bfin_spi0_info, /* Passed to driver */
367 },
368};
369
370/* SPI (1) */
371static struct bfin5xx_spi_master bfin_spi1_info = {
372 .num_chipselect = 5,
373 .enable_dma = 1, /* master has the ability to do dma transfer */
374 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
375};
376
377static struct resource bfin_spi1_resource[] = {
378 [0] = {
379 .start = SPI1_REGBASE,
380 .end = SPI1_REGBASE + 0xFF,
381 .flags = IORESOURCE_MEM,
382 },
383 [1] = {
384 .start = CH_SPI1,
385 .end = CH_SPI1,
53122693
YL		 386 .flags = IORESOURCE_DMA,
387 },
388 [2] = {
389 .start = IRQ_SPI1,
390 .end = IRQ_SPI1,
2f6f4bcd
BW		 391 .flags = IORESOURCE_IRQ,
392 },
393};
394
395static struct platform_device bfin_spi1_device = {
396 .name = "bfin-spi",
397 .id = 1, /* Bus number */
398 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
399 .resource = bfin_spi1_resource,
400 .dev = {
401 .platform_data = &bfin_spi1_info, /* Passed to driver */
402 },
403};
404#endif /* spi master and devices */
405
406#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
407static struct resource bfin_uart_resources[] = {
408#ifdef CONFIG_SERIAL_BFIN_UART0
409 {
410 .start = 0xFFC00400,
411 .end = 0xFFC004FF,
412 .flags = IORESOURCE_MEM,
413 },
414#endif
415#ifdef CONFIG_SERIAL_BFIN_UART1
416 {
417 .start = 0xFFC02000,
418 .end = 0xFFC020FF,
419 .flags = IORESOURCE_MEM,
420 },
421#endif
422};
423
424static struct platform_device bfin_uart_device = {
425 .name = "bfin-uart",
426 .id = 1,
427 .num_resources = ARRAY_SIZE(bfin_uart_resources),
428 .resource = bfin_uart_resources,
429};
430#endif
431
432#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
2f6f4bcd 433#ifdef CONFIG_BFIN_SIR0
42bd8bcb 434static struct resource bfin_sir0_resources[] = {
2f6f4bcd
BW		 435 {
436 .start = 0xFFC00400,
437 .end = 0xFFC004FF,
438 .flags = IORESOURCE_MEM,
439 },
42bd8bcb
GY		 440 {
441 .start = IRQ_UART0_RX,
442 .end = IRQ_UART0_RX+1,
443 .flags = IORESOURCE_IRQ,
444 },
445 {
446 .start = CH_UART0_RX,
447 .end = CH_UART0_RX+1,
448 .flags = IORESOURCE_DMA,
449 },
450};
451
452static struct platform_device bfin_sir0_device = {
453 .name = "bfin_sir",
454 .id = 0,
455 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
456 .resource = bfin_sir0_resources,
457};
2f6f4bcd
BW		 458#endif
459#ifdef CONFIG_BFIN_SIR1
42bd8bcb 460static struct resource bfin_sir1_resources[] = {
2f6f4bcd
BW		 461 {
462 .start = 0xFFC02000,
463 .end = 0xFFC020FF,
464 .flags = IORESOURCE_MEM,
465 },
42bd8bcb
GY		 466 {
467 .start = IRQ_UART1_RX,
468 .end = IRQ_UART1_RX+1,
469 .flags = IORESOURCE_IRQ,
470 },
471 {
472 .start = CH_UART1_RX,
473 .end = CH_UART1_RX+1,
474 .flags = IORESOURCE_DMA,
475 },
2f6f4bcd
BW		 476};
477
42bd8bcb 478static struct platform_device bfin_sir1_device = {
2f6f4bcd 479 .name = "bfin_sir",
42bd8bcb
GY		 480 .id = 1,
481 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
482 .resource = bfin_sir1_resources,
2f6f4bcd
BW		 483};
484#endif
42bd8bcb 485#endif
2f6f4bcd
BW		 486
487#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
488static struct resource bfin_twi0_resource[] = {
489 [0] = {
490 .start = TWI0_REGBASE,
491 .end = TWI0_REGBASE,
492 .flags = IORESOURCE_MEM,
493 },
494 [1] = {
495 .start = IRQ_TWI,
496 .end = IRQ_TWI,
497 .flags = IORESOURCE_IRQ,
498 },
499};
500
501static struct platform_device i2c_bfin_twi_device = {
502 .name = "i2c-bfin-twi",
503 .id = 0,
504 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
505 .resource = bfin_twi0_resource,
506};
507#endif
508
2f6f4bcd 509static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
ebd58333 510#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
2f6f4bcd
BW		 511 {
512 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
513 },
514#endif
204844eb 515#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
2f6f4bcd
BW		 516 {
517 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
518 .irq = IRQ_PF8,
519 },
520#endif
521};
2f6f4bcd
BW		 522
523#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
524static struct platform_device bfin_sport0_uart_device = {
525 .name = "bfin-sport-uart",
526 .id = 0,
527};
528
529static struct platform_device bfin_sport1_uart_device = {
530 .name = "bfin-sport-uart",
531 .id = 1,
532};
533#endif
534
535#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
536#include <linux/input.h>
537#include <linux/gpio_keys.h>
538
539static struct gpio_keys_button bfin_gpio_keys_table[] = {
540 {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
541 {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
542};
543
544static struct gpio_keys_platform_data bfin_gpio_keys_data = {
545 .buttons = bfin_gpio_keys_table,
546 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
547};
548
549static struct platform_device bfin_device_gpiokeys = {
550 .name = "gpio-keys",
551 .dev = {
552 .platform_data = &bfin_gpio_keys_data,
553 },
554};
555#endif
556
501674a5
CC		 557#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
558
559static struct bfin_sd_host bfin_sdh_data = {
560 .dma_chan = CH_RSI,
561 .irq_int0 = IRQ_RSI_INT0,
562 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
563};
564
565static struct platform_device bf51x_sdh_device = {
566 .name = "bfin-sdh",
567 .id = 0,
568 .dev = {
569 .platform_data = &bfin_sdh_data,
570 },
571};
572#endif
573
2f6f4bcd
BW		 574static struct resource bfin_gpios_resources = {
575 .start = 0,
576 .end = MAX_BLACKFIN_GPIOS - 1,
577 .flags = IORESOURCE_IRQ,
578};
579
580static struct platform_device bfin_gpios_device = {
581 .name = "simple-gpio",
582 .id = -1,
583 .num_resources = 1,
584 .resource = &bfin_gpios_resources,
585};
586
587static const unsigned int cclk_vlev_datasheet[] =
588{
589 VRPAIR(VLEV_100, 400000000),
590 VRPAIR(VLEV_105, 426000000),
591 VRPAIR(VLEV_110, 500000000),
592 VRPAIR(VLEV_115, 533000000),
593 VRPAIR(VLEV_120, 600000000),
594};
595
596static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
597 .tuple_tab = cclk_vlev_datasheet,
598 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
599 .vr_settling_time = 25 /* us */,
600};
601
602static struct platform_device bfin_dpmc = {
603 .name = "bfin dpmc",
604 .dev = {
605 .platform_data = &bfin_dmpc_vreg_data,
606 },
607};
608
609static struct platform_device *stamp_devices[] __initdata = {
610
611 &bfin_dpmc,
612
613#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
614 &rtc_device,
615#endif
616
617#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 618 &bfin_mii_bus,
2f6f4bcd 619 &bfin_mac_device,
65319628
GY		 620#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
621 &ksz8893m_switch_device,
622#endif
c19577e3 623#endif
65319628 624
2f6f4bcd
BW		 625#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
626 &bfin_spi0_device,
627 &bfin_spi1_device,
628#endif
629
630#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
631 &bfin_uart_device,
632#endif
633
634#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 635#ifdef CONFIG_BFIN_SIR0
636 &bfin_sir0_device,
637#endif
638#ifdef CONFIG_BFIN_SIR1
639 &bfin_sir1_device,
640#endif
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BW		 641#endif
642
643#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
644 &i2c_bfin_twi_device,
645#endif
646
647#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
648 &bfin_sport0_uart_device,
649 &bfin_sport1_uart_device,
650#endif
651
652#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
653 &bfin_device_gpiokeys,
654#endif
655
501674a5
CC		 656#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
657 &bf51x_sdh_device,
658#endif
659
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BW		 660#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
661 &ezbrd_flash_device,
662#endif
663
664 &bfin_gpios_device,
665};
666
667static int __init ezbrd_init(void)
668{
669 printk(KERN_INFO "%s(): registering device resources\n", __func__);
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BW		 670 i2c_register_board_info(0, bfin_i2c_board_info,
671 ARRAY_SIZE(bfin_i2c_board_info));
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BW		 672 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
673 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
ee0263cc
GY		 674 /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */
675 peripheral_request(P_AMS2, "ParaFlash");
676#if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE)
677 peripheral_request(P_AMS3, "ParaFlash");
678#endif
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BW		 679 return 0;
680}
681
682arch_initcall(ezbrd_init);
683
684void native_machine_restart(char *cmd)
685{
686 /* workaround reboot hang when booting from SPI */
687 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 688 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
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BW		 689}
690
691void bfin_get_ether_addr(char *addr)
692{
693 /* the MAC is stored in OTP memory page 0xDF */
694 u32 ret;
695 u64 otp_mac;
696 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
697
698 ret = otp_read(0xDF, 0x00, &otp_mac);
699 if (!(ret & 0x1)) {
700 char *otp_mac_p = (char *)&otp_mac;
701 for (ret = 0; ret < 6; ++ret)
702 addr[ret] = otp_mac_p[5 - ret];
703 }
704}
705EXPORT_SYMBOL(bfin_get_ether_addr);
Linux kernel - Deliverables
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