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2f6f4bcd BW |
1 | /* |
2 | * File: arch/blackfin/mach-bf518/boards/ezbrd.c | |
3 | * Based on: arch/blackfin/mach-bf527/boards/ezbrd.c | |
4 | * Author: Bryan Wu <cooloney@kernel.org> | |
5 | * | |
6 | * Created: | |
7 | * Description: | |
8 | * | |
9 | * Modified: | |
10 | * Copyright 2005 National ICT Australia (NICTA) | |
11 | * Copyright 2004-2008 Analog Devices Inc. | |
12 | * | |
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, see the file COPYING, or write | |
27 | * to the Free Software Foundation, Inc., | |
28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
29 | */ | |
30 | ||
31 | #include <linux/device.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/mtd/mtd.h> | |
34 | #include <linux/mtd/partitions.h> | |
35 | #include <linux/mtd/physmap.h> | |
36 | #include <linux/spi/spi.h> | |
37 | #include <linux/spi/flash.h> | |
38 | ||
39 | #include <linux/i2c.h> | |
40 | #include <linux/irq.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <asm/dma.h> | |
43 | #include <asm/bfin5xx_spi.h> | |
44 | #include <asm/reboot.h> | |
45 | #include <asm/portmux.h> | |
46 | #include <asm/dpmc.h> | |
501674a5 | 47 | #include <asm/bfin_sdh.h> |
2f6f4bcd | 48 | #include <linux/spi/ad7877.h> |
65319628 | 49 | #include <net/dsa.h> |
2f6f4bcd BW |
50 | |
51 | /* | |
52 | * Name the Board for the /proc/cpuinfo | |
53 | */ | |
fe85cad2 | 54 | const char bfin_board_name[] = "ADI BF518F-EZBRD"; |
2f6f4bcd BW |
55 | |
56 | /* | |
57 | * Driver needs to know address, irq and flag pin. | |
58 | */ | |
59 | ||
60 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | |
61 | static struct mtd_partition ezbrd_partitions[] = { | |
62 | { | |
63 | .name = "bootloader(nor)", | |
64 | .size = 0x40000, | |
65 | .offset = 0, | |
66 | }, { | |
67 | .name = "linux kernel(nor)", | |
68 | .size = 0x1C0000, | |
69 | .offset = MTDPART_OFS_APPEND, | |
70 | }, { | |
71 | .name = "file system(nor)", | |
72 | .size = MTDPART_SIZ_FULL, | |
73 | .offset = MTDPART_OFS_APPEND, | |
74 | } | |
75 | }; | |
76 | ||
77 | static struct physmap_flash_data ezbrd_flash_data = { | |
78 | .width = 2, | |
79 | .parts = ezbrd_partitions, | |
80 | .nr_parts = ARRAY_SIZE(ezbrd_partitions), | |
81 | }; | |
82 | ||
83 | static struct resource ezbrd_flash_resource = { | |
84 | .start = 0x20000000, | |
ee0263cc GY |
85 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
86 | .end = 0x202fffff, | |
87 | #else | |
2f6f4bcd | 88 | .end = 0x203fffff, |
ee0263cc | 89 | #endif |
2f6f4bcd BW |
90 | .flags = IORESOURCE_MEM, |
91 | }; | |
92 | ||
93 | static struct platform_device ezbrd_flash_device = { | |
94 | .name = "physmap-flash", | |
95 | .id = 0, | |
96 | .dev = { | |
97 | .platform_data = &ezbrd_flash_data, | |
98 | }, | |
99 | .num_resources = 1, | |
100 | .resource = &ezbrd_flash_resource, | |
101 | }; | |
102 | #endif | |
103 | ||
104 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | |
105 | static struct platform_device rtc_device = { | |
106 | .name = "rtc-bfin", | |
107 | .id = -1, | |
108 | }; | |
109 | #endif | |
110 | ||
111 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | |
65319628 GY |
112 | static struct platform_device bfin_mii_bus = { |
113 | .name = "bfin_mii_bus", | |
114 | }; | |
115 | ||
2f6f4bcd BW |
116 | static struct platform_device bfin_mac_device = { |
117 | .name = "bfin_mac", | |
65319628 GY |
118 | .dev.platform_data = &bfin_mii_bus, |
119 | }; | |
65319628 GY |
120 | |
121 | #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) | |
2780cd64 | 122 | static struct dsa_chip_data ksz8893m_switch_chip_data = { |
65319628 | 123 | .mii_bus = &bfin_mii_bus.dev, |
2780cd64 MF |
124 | .port_names = { |
125 | NULL, | |
126 | "eth%d", | |
127 | "eth%d", | |
128 | "cpu", | |
129 | }, | |
130 | }; | |
131 | static struct dsa_platform_data ksz8893m_switch_data = { | |
132 | .nr_chips = 1, | |
65319628 | 133 | .netdev = &bfin_mac_device.dev, |
2780cd64 | 134 | .chip = &ksz8893m_switch_chip_data, |
65319628 GY |
135 | }; |
136 | ||
137 | static struct platform_device ksz8893m_switch_device = { | |
138 | .name = "dsa", | |
139 | .id = 0, | |
140 | .num_resources = 0, | |
141 | .dev.platform_data = &ksz8893m_switch_data, | |
2f6f4bcd BW |
142 | }; |
143 | #endif | |
c19577e3 | 144 | #endif |
2f6f4bcd BW |
145 | |
146 | #if defined(CONFIG_MTD_M25P80) \ | |
147 | || defined(CONFIG_MTD_M25P80_MODULE) | |
148 | static struct mtd_partition bfin_spi_flash_partitions[] = { | |
149 | { | |
150 | .name = "bootloader(spi)", | |
151 | .size = 0x00040000, | |
152 | .offset = 0, | |
153 | .mask_flags = MTD_CAP_ROM | |
154 | }, { | |
155 | .name = "linux kernel(spi)", | |
156 | .size = MTDPART_SIZ_FULL, | |
157 | .offset = MTDPART_OFS_APPEND, | |
158 | } | |
159 | }; | |
160 | ||
161 | static struct flash_platform_data bfin_spi_flash_data = { | |
162 | .name = "m25p80", | |
163 | .parts = bfin_spi_flash_partitions, | |
164 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | |
165 | .type = "m25p16", | |
166 | }; | |
167 | ||
168 | /* SPI flash chip (m25p64) */ | |
169 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | |
170 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
171 | .bits_per_word = 8, | |
172 | }; | |
173 | #endif | |
174 | ||
a261eec0 MF |
175 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
176 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) | |
2f6f4bcd BW |
177 | /* SPI ADC chip */ |
178 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | |
179 | .enable_dma = 1, /* use dma transfer with this chip*/ | |
180 | .bits_per_word = 16, | |
181 | }; | |
182 | #endif | |
183 | ||
c19577e3 | 184 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
65319628 GY |
185 | #if defined(CONFIG_NET_DSA_KSZ8893M) \ |
186 | || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) | |
187 | /* SPI SWITCH CHIP */ | |
188 | static struct bfin5xx_spi_chip spi_switch_info = { | |
189 | .enable_dma = 0, | |
190 | .bits_per_word = 8, | |
191 | }; | |
192 | #endif | |
c19577e3 | 193 | #endif |
65319628 | 194 | |
f3f704d3 MH |
195 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
196 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | |
197 | .enable_dma = 0, | |
2f6f4bcd BW |
198 | .bits_per_word = 8, |
199 | }; | |
200 | #endif | |
201 | ||
202 | #if defined(CONFIG_PBX) | |
203 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | |
204 | .ctl_reg = 0x4, /* send zero */ | |
205 | .enable_dma = 0, | |
206 | .bits_per_word = 8, | |
207 | .cs_change_per_word = 1, | |
208 | }; | |
209 | #endif | |
210 | ||
211 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | |
212 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { | |
213 | .enable_dma = 0, | |
214 | .bits_per_word = 16, | |
215 | }; | |
216 | ||
217 | static const struct ad7877_platform_data bfin_ad7877_ts_info = { | |
218 | .model = 7877, | |
219 | .vref_delay_usecs = 50, /* internal, no capacitor */ | |
220 | .x_plate_ohms = 419, | |
221 | .y_plate_ohms = 486, | |
222 | .pressure_max = 1000, | |
223 | .pressure_min = 0, | |
224 | .stopacq_polarity = 1, | |
225 | .first_conversion_delay = 3, | |
226 | .acquisition_time = 1, | |
227 | .averaging = 1, | |
228 | .pen_down_acc_interval = 1, | |
229 | }; | |
230 | #endif | |
231 | ||
232 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ | |
233 | && defined(CONFIG_SND_SOC_WM8731_SPI) | |
234 | static struct bfin5xx_spi_chip spi_wm8731_chip_info = { | |
235 | .enable_dma = 0, | |
236 | .bits_per_word = 16, | |
237 | }; | |
238 | #endif | |
239 | ||
240 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | |
241 | static struct bfin5xx_spi_chip spidev_chip_info = { | |
242 | .enable_dma = 0, | |
243 | .bits_per_word = 8, | |
244 | }; | |
245 | #endif | |
246 | ||
247 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | |
248 | #if defined(CONFIG_MTD_M25P80) \ | |
249 | || defined(CONFIG_MTD_M25P80_MODULE) | |
250 | { | |
251 | /* the modalias must be the same as spi device driver name */ | |
252 | .modalias = "m25p80", /* Name of spi_driver for this device */ | |
253 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | |
254 | .bus_num = 0, /* Framework bus number */ | |
a427293f | 255 | .chip_select = 2, /* On BF518F-EZBRD it's SPI0_SSEL2 */ |
2f6f4bcd BW |
256 | .platform_data = &bfin_spi_flash_data, |
257 | .controller_data = &spi_flash_chip_info, | |
258 | .mode = SPI_MODE_3, | |
259 | }, | |
260 | #endif | |
261 | ||
a261eec0 MF |
262 | #if defined(CONFIG_BFIN_SPI_ADC) \ |
263 | || defined(CONFIG_BFIN_SPI_ADC_MODULE) | |
2f6f4bcd BW |
264 | { |
265 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | |
266 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | |
267 | .bus_num = 0, /* Framework bus number */ | |
268 | .chip_select = 1, /* Framework chip select. */ | |
269 | .platform_data = NULL, /* No spi_driver specific config */ | |
270 | .controller_data = &spi_adc_chip_info, | |
271 | }, | |
272 | #endif | |
273 | ||
c19577e3 | 274 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
65319628 GY |
275 | #if defined(CONFIG_NET_DSA_KSZ8893M) \ |
276 | || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) | |
277 | { | |
278 | .modalias = "ksz8893m", | |
279 | .max_speed_hz = 5000000, | |
280 | .bus_num = 0, | |
281 | .chip_select = 1, | |
282 | .platform_data = NULL, | |
283 | .controller_data = &spi_switch_info, | |
284 | .mode = SPI_MODE_3, | |
285 | }, | |
286 | #endif | |
c19577e3 | 287 | #endif |
65319628 | 288 | |
f3f704d3 | 289 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
2f6f4bcd | 290 | { |
f3f704d3 | 291 | .modalias = "mmc_spi", |
2f6f4bcd BW |
292 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
293 | .bus_num = 0, | |
f3f704d3 MH |
294 | .chip_select = 5, |
295 | .controller_data = &mmc_spi_chip_info, | |
2f6f4bcd BW |
296 | .mode = SPI_MODE_3, |
297 | }, | |
298 | #endif | |
299 | #if defined(CONFIG_PBX) | |
300 | { | |
301 | .modalias = "fxs-spi", | |
302 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | |
303 | .bus_num = 0, | |
304 | .chip_select = 8 - CONFIG_J11_JUMPER, | |
305 | .controller_data = &spi_si3xxx_chip_info, | |
306 | .mode = SPI_MODE_3, | |
307 | }, | |
308 | { | |
309 | .modalias = "fxo-spi", | |
310 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | |
311 | .bus_num = 0, | |
312 | .chip_select = 8 - CONFIG_J19_JUMPER, | |
313 | .controller_data = &spi_si3xxx_chip_info, | |
314 | .mode = SPI_MODE_3, | |
315 | }, | |
316 | #endif | |
317 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | |
318 | { | |
319 | .modalias = "ad7877", | |
320 | .platform_data = &bfin_ad7877_ts_info, | |
321 | .irq = IRQ_PF8, | |
322 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | |
323 | .bus_num = 0, | |
324 | .chip_select = 2, | |
325 | .controller_data = &spi_ad7877_chip_info, | |
326 | }, | |
327 | #endif | |
328 | #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \ | |
329 | && defined(CONFIG_SND_SOC_WM8731_SPI) | |
330 | { | |
331 | .modalias = "wm8731", | |
332 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
333 | .bus_num = 0, | |
334 | .chip_select = 5, | |
335 | .controller_data = &spi_wm8731_chip_info, | |
336 | .mode = SPI_MODE_0, | |
337 | }, | |
338 | #endif | |
339 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | |
340 | { | |
341 | .modalias = "spidev", | |
342 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
343 | .bus_num = 0, | |
344 | .chip_select = 1, | |
345 | .controller_data = &spidev_chip_info, | |
346 | }, | |
347 | #endif | |
348 | #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE) | |
349 | { | |
350 | .modalias = "bfin-lq035q1-spi", | |
351 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | |
352 | .bus_num = 0, | |
353 | .chip_select = 1, | |
354 | .controller_data = &lq035q1_spi_chip_info, | |
355 | .mode = SPI_CPHA | SPI_CPOL, | |
356 | }, | |
357 | #endif | |
358 | }; | |
359 | ||
360 | /* SPI controller data */ | |
361 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
362 | /* SPI (0) */ | |
363 | static struct bfin5xx_spi_master bfin_spi0_info = { | |
364 | .num_chipselect = 5, | |
365 | .enable_dma = 1, /* master has the ability to do dma transfer */ | |
366 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | |
367 | }; | |
368 | ||
369 | static struct resource bfin_spi0_resource[] = { | |
370 | [0] = { | |
371 | .start = SPI0_REGBASE, | |
372 | .end = SPI0_REGBASE + 0xFF, | |
373 | .flags = IORESOURCE_MEM, | |
374 | }, | |
375 | [1] = { | |
376 | .start = CH_SPI0, | |
377 | .end = CH_SPI0, | |
53122693 YL |
378 | .flags = IORESOURCE_DMA, |
379 | }, | |
380 | [2] = { | |
381 | .start = IRQ_SPI0, | |
382 | .end = IRQ_SPI0, | |
2f6f4bcd BW |
383 | .flags = IORESOURCE_IRQ, |
384 | }, | |
385 | }; | |
386 | ||
387 | static struct platform_device bfin_spi0_device = { | |
388 | .name = "bfin-spi", | |
389 | .id = 0, /* Bus number */ | |
390 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
391 | .resource = bfin_spi0_resource, | |
392 | .dev = { | |
393 | .platform_data = &bfin_spi0_info, /* Passed to driver */ | |
394 | }, | |
395 | }; | |
396 | ||
397 | /* SPI (1) */ | |
398 | static struct bfin5xx_spi_master bfin_spi1_info = { | |
399 | .num_chipselect = 5, | |
400 | .enable_dma = 1, /* master has the ability to do dma transfer */ | |
401 | .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | |
402 | }; | |
403 | ||
404 | static struct resource bfin_spi1_resource[] = { | |
405 | [0] = { | |
406 | .start = SPI1_REGBASE, | |
407 | .end = SPI1_REGBASE + 0xFF, | |
408 | .flags = IORESOURCE_MEM, | |
409 | }, | |
410 | [1] = { | |
411 | .start = CH_SPI1, | |
412 | .end = CH_SPI1, | |
53122693 YL |
413 | .flags = IORESOURCE_DMA, |
414 | }, | |
415 | [2] = { | |
416 | .start = IRQ_SPI1, | |
417 | .end = IRQ_SPI1, | |
2f6f4bcd BW |
418 | .flags = IORESOURCE_IRQ, |
419 | }, | |
420 | }; | |
421 | ||
422 | static struct platform_device bfin_spi1_device = { | |
423 | .name = "bfin-spi", | |
424 | .id = 1, /* Bus number */ | |
425 | .num_resources = ARRAY_SIZE(bfin_spi1_resource), | |
426 | .resource = bfin_spi1_resource, | |
427 | .dev = { | |
428 | .platform_data = &bfin_spi1_info, /* Passed to driver */ | |
429 | }, | |
430 | }; | |
431 | #endif /* spi master and devices */ | |
432 | ||
433 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
434 | static struct resource bfin_uart_resources[] = { | |
435 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
436 | { | |
437 | .start = 0xFFC00400, | |
438 | .end = 0xFFC004FF, | |
439 | .flags = IORESOURCE_MEM, | |
440 | }, | |
441 | #endif | |
442 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
443 | { | |
444 | .start = 0xFFC02000, | |
445 | .end = 0xFFC020FF, | |
446 | .flags = IORESOURCE_MEM, | |
447 | }, | |
448 | #endif | |
449 | }; | |
450 | ||
451 | static struct platform_device bfin_uart_device = { | |
452 | .name = "bfin-uart", | |
453 | .id = 1, | |
454 | .num_resources = ARRAY_SIZE(bfin_uart_resources), | |
455 | .resource = bfin_uart_resources, | |
456 | }; | |
457 | #endif | |
458 | ||
459 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | |
2f6f4bcd | 460 | #ifdef CONFIG_BFIN_SIR0 |
42bd8bcb | 461 | static struct resource bfin_sir0_resources[] = { |
2f6f4bcd BW |
462 | { |
463 | .start = 0xFFC00400, | |
464 | .end = 0xFFC004FF, | |
465 | .flags = IORESOURCE_MEM, | |
466 | }, | |
42bd8bcb GY |
467 | { |
468 | .start = IRQ_UART0_RX, | |
469 | .end = IRQ_UART0_RX+1, | |
470 | .flags = IORESOURCE_IRQ, | |
471 | }, | |
472 | { | |
473 | .start = CH_UART0_RX, | |
474 | .end = CH_UART0_RX+1, | |
475 | .flags = IORESOURCE_DMA, | |
476 | }, | |
477 | }; | |
478 | ||
479 | static struct platform_device bfin_sir0_device = { | |
480 | .name = "bfin_sir", | |
481 | .id = 0, | |
482 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | |
483 | .resource = bfin_sir0_resources, | |
484 | }; | |
2f6f4bcd BW |
485 | #endif |
486 | #ifdef CONFIG_BFIN_SIR1 | |
42bd8bcb | 487 | static struct resource bfin_sir1_resources[] = { |
2f6f4bcd BW |
488 | { |
489 | .start = 0xFFC02000, | |
490 | .end = 0xFFC020FF, | |
491 | .flags = IORESOURCE_MEM, | |
492 | }, | |
42bd8bcb GY |
493 | { |
494 | .start = IRQ_UART1_RX, | |
495 | .end = IRQ_UART1_RX+1, | |
496 | .flags = IORESOURCE_IRQ, | |
497 | }, | |
498 | { | |
499 | .start = CH_UART1_RX, | |
500 | .end = CH_UART1_RX+1, | |
501 | .flags = IORESOURCE_DMA, | |
502 | }, | |
2f6f4bcd BW |
503 | }; |
504 | ||
42bd8bcb | 505 | static struct platform_device bfin_sir1_device = { |
2f6f4bcd | 506 | .name = "bfin_sir", |
42bd8bcb GY |
507 | .id = 1, |
508 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | |
509 | .resource = bfin_sir1_resources, | |
2f6f4bcd BW |
510 | }; |
511 | #endif | |
42bd8bcb | 512 | #endif |
2f6f4bcd BW |
513 | |
514 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | |
515 | static struct resource bfin_twi0_resource[] = { | |
516 | [0] = { | |
517 | .start = TWI0_REGBASE, | |
518 | .end = TWI0_REGBASE, | |
519 | .flags = IORESOURCE_MEM, | |
520 | }, | |
521 | [1] = { | |
522 | .start = IRQ_TWI, | |
523 | .end = IRQ_TWI, | |
524 | .flags = IORESOURCE_IRQ, | |
525 | }, | |
526 | }; | |
527 | ||
528 | static struct platform_device i2c_bfin_twi_device = { | |
529 | .name = "i2c-bfin-twi", | |
530 | .id = 0, | |
531 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), | |
532 | .resource = bfin_twi0_resource, | |
533 | }; | |
534 | #endif | |
535 | ||
2f6f4bcd | 536 | static struct i2c_board_info __initdata bfin_i2c_board_info[] = { |
a261eec0 | 537 | #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE) |
2f6f4bcd BW |
538 | { |
539 | I2C_BOARD_INFO("pcf8574_lcd", 0x22), | |
540 | }, | |
541 | #endif | |
542 | #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE) | |
543 | { | |
544 | I2C_BOARD_INFO("pcf8574_keypad", 0x27), | |
545 | .irq = IRQ_PF8, | |
546 | }, | |
547 | #endif | |
548 | }; | |
2f6f4bcd BW |
549 | |
550 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | |
551 | static struct platform_device bfin_sport0_uart_device = { | |
552 | .name = "bfin-sport-uart", | |
553 | .id = 0, | |
554 | }; | |
555 | ||
556 | static struct platform_device bfin_sport1_uart_device = { | |
557 | .name = "bfin-sport-uart", | |
558 | .id = 1, | |
559 | }; | |
560 | #endif | |
561 | ||
562 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | |
563 | #include <linux/input.h> | |
564 | #include <linux/gpio_keys.h> | |
565 | ||
566 | static struct gpio_keys_button bfin_gpio_keys_table[] = { | |
567 | {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"}, | |
568 | {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"}, | |
569 | }; | |
570 | ||
571 | static struct gpio_keys_platform_data bfin_gpio_keys_data = { | |
572 | .buttons = bfin_gpio_keys_table, | |
573 | .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), | |
574 | }; | |
575 | ||
576 | static struct platform_device bfin_device_gpiokeys = { | |
577 | .name = "gpio-keys", | |
578 | .dev = { | |
579 | .platform_data = &bfin_gpio_keys_data, | |
580 | }, | |
581 | }; | |
582 | #endif | |
583 | ||
501674a5 CC |
584 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) |
585 | ||
586 | static struct bfin_sd_host bfin_sdh_data = { | |
587 | .dma_chan = CH_RSI, | |
588 | .irq_int0 = IRQ_RSI_INT0, | |
589 | .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0}, | |
590 | }; | |
591 | ||
592 | static struct platform_device bf51x_sdh_device = { | |
593 | .name = "bfin-sdh", | |
594 | .id = 0, | |
595 | .dev = { | |
596 | .platform_data = &bfin_sdh_data, | |
597 | }, | |
598 | }; | |
599 | #endif | |
600 | ||
2f6f4bcd BW |
601 | static struct resource bfin_gpios_resources = { |
602 | .start = 0, | |
603 | .end = MAX_BLACKFIN_GPIOS - 1, | |
604 | .flags = IORESOURCE_IRQ, | |
605 | }; | |
606 | ||
607 | static struct platform_device bfin_gpios_device = { | |
608 | .name = "simple-gpio", | |
609 | .id = -1, | |
610 | .num_resources = 1, | |
611 | .resource = &bfin_gpios_resources, | |
612 | }; | |
613 | ||
614 | static const unsigned int cclk_vlev_datasheet[] = | |
615 | { | |
616 | VRPAIR(VLEV_100, 400000000), | |
617 | VRPAIR(VLEV_105, 426000000), | |
618 | VRPAIR(VLEV_110, 500000000), | |
619 | VRPAIR(VLEV_115, 533000000), | |
620 | VRPAIR(VLEV_120, 600000000), | |
621 | }; | |
622 | ||
623 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | |
624 | .tuple_tab = cclk_vlev_datasheet, | |
625 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | |
626 | .vr_settling_time = 25 /* us */, | |
627 | }; | |
628 | ||
629 | static struct platform_device bfin_dpmc = { | |
630 | .name = "bfin dpmc", | |
631 | .dev = { | |
632 | .platform_data = &bfin_dmpc_vreg_data, | |
633 | }, | |
634 | }; | |
635 | ||
636 | static struct platform_device *stamp_devices[] __initdata = { | |
637 | ||
638 | &bfin_dpmc, | |
639 | ||
640 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | |
641 | &rtc_device, | |
642 | #endif | |
643 | ||
644 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | |
65319628 | 645 | &bfin_mii_bus, |
2f6f4bcd | 646 | &bfin_mac_device, |
65319628 GY |
647 | #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) |
648 | &ksz8893m_switch_device, | |
649 | #endif | |
c19577e3 | 650 | #endif |
65319628 | 651 | |
2f6f4bcd BW |
652 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
653 | &bfin_spi0_device, | |
654 | &bfin_spi1_device, | |
655 | #endif | |
656 | ||
657 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
658 | &bfin_uart_device, | |
659 | #endif | |
660 | ||
661 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | |
42bd8bcb GY |
662 | #ifdef CONFIG_BFIN_SIR0 |
663 | &bfin_sir0_device, | |
664 | #endif | |
665 | #ifdef CONFIG_BFIN_SIR1 | |
666 | &bfin_sir1_device, | |
667 | #endif | |
2f6f4bcd BW |
668 | #endif |
669 | ||
670 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | |
671 | &i2c_bfin_twi_device, | |
672 | #endif | |
673 | ||
674 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | |
675 | &bfin_sport0_uart_device, | |
676 | &bfin_sport1_uart_device, | |
677 | #endif | |
678 | ||
679 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | |
680 | &bfin_device_gpiokeys, | |
681 | #endif | |
682 | ||
501674a5 CC |
683 | #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE) |
684 | &bf51x_sdh_device, | |
685 | #endif | |
686 | ||
2f6f4bcd BW |
687 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) |
688 | &ezbrd_flash_device, | |
689 | #endif | |
690 | ||
691 | &bfin_gpios_device, | |
692 | }; | |
693 | ||
694 | static int __init ezbrd_init(void) | |
695 | { | |
696 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | |
2f6f4bcd BW |
697 | i2c_register_board_info(0, bfin_i2c_board_info, |
698 | ARRAY_SIZE(bfin_i2c_board_info)); | |
2f6f4bcd BW |
699 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); |
700 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | |
ee0263cc GY |
701 | /* setup BF518-EZBRD GPIO pin PG11 to AMS2, PG15 to AMS3. */ |
702 | peripheral_request(P_AMS2, "ParaFlash"); | |
703 | #if !defined(CONFIG_SPI_BFIN) && !defined(CONFIG_SPI_BFIN_MODULE) | |
704 | peripheral_request(P_AMS3, "ParaFlash"); | |
705 | #endif | |
2f6f4bcd BW |
706 | return 0; |
707 | } | |
708 | ||
709 | arch_initcall(ezbrd_init); | |
710 | ||
711 | void native_machine_restart(char *cmd) | |
712 | { | |
713 | /* workaround reboot hang when booting from SPI */ | |
714 | if ((bfin_read_SYSCR() & 0x7) == 0x3) | |
b52dae31 | 715 | bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); |
2f6f4bcd BW |
716 | } |
717 | ||
718 | void bfin_get_ether_addr(char *addr) | |
719 | { | |
720 | /* the MAC is stored in OTP memory page 0xDF */ | |
721 | u32 ret; | |
722 | u64 otp_mac; | |
723 | u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A; | |
724 | ||
725 | ret = otp_read(0xDF, 0x00, &otp_mac); | |
726 | if (!(ret & 0x1)) { | |
727 | char *otp_mac_p = (char *)&otp_mac; | |
728 | for (ret = 0; ret < 6; ++ret) | |
729 | addr[ret] = otp_mac_p[5 - ret]; | |
730 | } | |
731 | } | |
732 | EXPORT_SYMBOL(bfin_get_ether_addr); |