Commit | Line | Data |
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2f6f4bcd | 1 | /* |
af5d7fc7 MF |
2 | * DO NOT EDIT THIS FILE |
3 | * This file is under version control at | |
4 | * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ | |
5 | * and can be replaced with that version at any time | |
6 | * DO NOT EDIT THIS FILE | |
2f6f4bcd | 7 | * |
93f1742c | 8 | * Copyright 2004-2011 Analog Devices Inc. |
af5d7fc7 MF |
9 | * Licensed under the ADI BSD license. |
10 | * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd | |
2f6f4bcd BW |
11 | */ |
12 | ||
a413647b | 13 | /* This file should be up to date with: |
979365ba | 14 | * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List |
2f6f4bcd BW |
15 | */ |
16 | ||
a413647b MF |
17 | #if __SILICON_REVISION__ < 0 |
18 | # error will not work on BF518 silicon version | |
19 | #endif | |
20 | ||
2f6f4bcd BW |
21 | #ifndef _MACH_ANOMALY_H_ |
22 | #define _MACH_ANOMALY_H_ | |
23 | ||
a200ad22 | 24 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
2f6f4bcd | 25 | #define ANOMALY_05000074 (1) |
dc7101bb MF |
26 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
27 | #define ANOMALY_05000119 (1) | |
2f6f4bcd BW |
28 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
29 | #define ANOMALY_05000122 (1) | |
30 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
31 | #define ANOMALY_05000245 (1) | |
c18e99cf MF |
32 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ |
33 | #define ANOMALY_05000254 (1) | |
2f6f4bcd BW |
34 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
35 | #define ANOMALY_05000265 (1) | |
36 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | |
37 | #define ANOMALY_05000310 (1) | |
38 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | |
39 | #define ANOMALY_05000366 (1) | |
40 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ | |
41 | #define ANOMALY_05000405 (1) | |
42 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ | |
43 | #define ANOMALY_05000408 (1) | |
44 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | |
45 | #define ANOMALY_05000416 (1) | |
46 | /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ | |
47 | #define ANOMALY_05000421 (1) | |
48 | /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ | |
49 | #define ANOMALY_05000422 (1) | |
50 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ | |
51 | #define ANOMALY_05000426 (1) | |
52 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ | |
a200ad22 | 53 | #define ANOMALY_05000430 (__SILICON_REVISION__ < 1) |
2f6f4bcd BW |
54 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ |
55 | #define ANOMALY_05000431 (1) | |
dc7101bb MF |
56 | /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ |
57 | #define ANOMALY_05000434 (1) | |
2f6f4bcd | 58 | /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ |
a200ad22 | 59 | #define ANOMALY_05000435 (__SILICON_REVISION__ < 1) |
2f6f4bcd | 60 | /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ |
a200ad22 | 61 | #define ANOMALY_05000438 (__SILICON_REVISION__ < 1) |
a413647b | 62 | /* Preboot Cannot be Used to Alter the PLL_DIV Register */ |
a200ad22 | 63 | #define ANOMALY_05000439 (__SILICON_REVISION__ < 1) |
2f6f4bcd | 64 | /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ |
a200ad22 | 65 | #define ANOMALY_05000440 (__SILICON_REVISION__ < 1) |
2f6f4bcd BW |
66 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
67 | #define ANOMALY_05000443 (1) | |
68 | /* Incorrect L1 Instruction Bank B Memory Map Location */ | |
a200ad22 | 69 | #define ANOMALY_05000444 (__SILICON_REVISION__ < 1) |
c18e99cf | 70 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ |
a200ad22 | 71 | #define ANOMALY_05000452 (__SILICON_REVISION__ < 1) |
c18e99cf | 72 | /* PWM_TRIPB Signal Not Available on PG10 */ |
a200ad22 | 73 | #define ANOMALY_05000453 (__SILICON_REVISION__ < 1) |
c18e99cf | 74 | /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ |
a200ad22 MF |
75 | #define ANOMALY_05000455 (__SILICON_REVISION__ < 1) |
76 | /* False Hardware Error when RETI Points to Invalid Memory */ | |
a413647b | 77 | #define ANOMALY_05000461 (1) |
a200ad22 | 78 | /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ |
979365ba | 79 | #define ANOMALY_05000462 (__SILICON_REVISION__ < 2) |
dc7101bb | 80 | /* Incorrect Default MSEL Value in PLL_CTL */ |
979365ba | 81 | #define ANOMALY_05000472 (__SILICON_REVISION__ < 2) |
dc7101bb | 82 | /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ |
af5d7fc7 MF |
83 | #define ANOMALY_05000473 (1) |
84 | /* TESTSET Instruction Cannot Be Interrupted */ | |
85 | #define ANOMALY_05000477 (1) | |
dc7101bb MF |
86 | /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ |
87 | #define ANOMALY_05000481 (1) | |
979365ba MF |
88 | /* PLL Latches Incorrect Settings During Reset */ |
89 | #define ANOMALY_05000482 (__SILICON_REVISION__ < 2) | |
90 | /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ | |
91 | #define ANOMALY_05000485 (__SILICON_REVISION__ < 2) | |
92 | /* SPI Master Boot Can Fail Under Certain Conditions */ | |
93 | #define ANOMALY_05000490 (1) | |
94 | /* Instruction Memory Stalls Can Cause IFLUSH to Fail */ | |
dc7101bb | 95 | #define ANOMALY_05000491 (1) |
979365ba MF |
96 | /* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ |
97 | #define ANOMALY_05000494 (1) | |
98 | /* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ | |
99 | #define ANOMALY_05000498 (1) | |
100 | /* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ | |
101 | #define ANOMALY_05000501 (1) | |
2f6f4bcd BW |
102 | |
103 | /* Anomalies that don't exist on this proc */ | |
a413647b | 104 | #define ANOMALY_05000099 (0) |
a413647b | 105 | #define ANOMALY_05000120 (0) |
2f6f4bcd | 106 | #define ANOMALY_05000125 (0) |
a413647b | 107 | #define ANOMALY_05000149 (0) |
2f6f4bcd | 108 | #define ANOMALY_05000158 (0) |
a413647b MF |
109 | #define ANOMALY_05000171 (0) |
110 | #define ANOMALY_05000179 (0) | |
a200ad22 | 111 | #define ANOMALY_05000182 (0) |
2f6f4bcd | 112 | #define ANOMALY_05000183 (0) |
976119bc | 113 | #define ANOMALY_05000189 (0) |
2f6f4bcd | 114 | #define ANOMALY_05000198 (0) |
a200ad22 | 115 | #define ANOMALY_05000202 (0) |
a413647b | 116 | #define ANOMALY_05000215 (0) |
dc7101bb | 117 | #define ANOMALY_05000219 (0) |
a413647b MF |
118 | #define ANOMALY_05000220 (0) |
119 | #define ANOMALY_05000227 (0) | |
2f6f4bcd | 120 | #define ANOMALY_05000230 (0) |
a413647b MF |
121 | #define ANOMALY_05000231 (0) |
122 | #define ANOMALY_05000233 (0) | |
a200ad22 | 123 | #define ANOMALY_05000234 (0) |
a413647b | 124 | #define ANOMALY_05000242 (0) |
2f6f4bcd | 125 | #define ANOMALY_05000244 (0) |
a413647b MF |
126 | #define ANOMALY_05000248 (0) |
127 | #define ANOMALY_05000250 (0) | |
a200ad22 | 128 | #define ANOMALY_05000257 (0) |
2f6f4bcd BW |
129 | #define ANOMALY_05000261 (0) |
130 | #define ANOMALY_05000263 (0) | |
131 | #define ANOMALY_05000266 (0) | |
132 | #define ANOMALY_05000273 (0) | |
a413647b | 133 | #define ANOMALY_05000274 (0) |
ee554be9 | 134 | #define ANOMALY_05000278 (0) |
a200ad22 MF |
135 | #define ANOMALY_05000281 (0) |
136 | #define ANOMALY_05000283 (0) | |
2f6f4bcd | 137 | #define ANOMALY_05000285 (0) |
a413647b MF |
138 | #define ANOMALY_05000287 (0) |
139 | #define ANOMALY_05000301 (0) | |
c18e99cf | 140 | #define ANOMALY_05000305 (0) |
2f6f4bcd BW |
141 | #define ANOMALY_05000307 (0) |
142 | #define ANOMALY_05000311 (0) | |
143 | #define ANOMALY_05000312 (0) | |
a200ad22 | 144 | #define ANOMALY_05000315 (0) |
2f6f4bcd BW |
145 | #define ANOMALY_05000323 (0) |
146 | #define ANOMALY_05000353 (0) | |
a200ad22 | 147 | #define ANOMALY_05000357 (0) |
a413647b | 148 | #define ANOMALY_05000362 (1) |
2f6f4bcd | 149 | #define ANOMALY_05000363 (0) |
976119bc | 150 | #define ANOMALY_05000364 (0) |
a200ad22 | 151 | #define ANOMALY_05000371 (0) |
ee554be9 | 152 | #define ANOMALY_05000380 (0) |
93f1742c | 153 | #define ANOMALY_05000383 (0) |
2f6f4bcd | 154 | #define ANOMALY_05000386 (0) |
a413647b MF |
155 | #define ANOMALY_05000389 (0) |
156 | #define ANOMALY_05000400 (0) | |
bd411b15 | 157 | #define ANOMALY_05000402 (0) |
6651ece9 MF |
158 | #define ANOMALY_05000412 (0) |
159 | #define ANOMALY_05000432 (0) | |
7dbc3f6e MF |
160 | #define ANOMALY_05000447 (0) |
161 | #define ANOMALY_05000448 (0) | |
a413647b MF |
162 | #define ANOMALY_05000456 (0) |
163 | #define ANOMALY_05000450 (0) | |
a200ad22 MF |
164 | #define ANOMALY_05000465 (0) |
165 | #define ANOMALY_05000467 (0) | |
af5d7fc7 MF |
166 | #define ANOMALY_05000474 (0) |
167 | #define ANOMALY_05000475 (0) | |
93f1742c | 168 | #define ANOMALY_05000480 (0) |
2f6f4bcd BW |
169 | |
170 | #endif |