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Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux...
[deliverable/linux.git] / arch / blackfin / mach-bf527 / boards / ezbrd.c
CommitLineData
8cc7117e
MH		 1/*
2 * File: arch/blackfin/mach-bf527/boards/ezbrd.c
3 * Based on: arch/blackfin/mach-bf537/boards/stamp.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2008 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/mtd/physmap.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38
39#include <linux/i2c.h>
40#include <linux/irq.h>
41#include <linux/interrupt.h>
42#include <linux/usb/musb.h>
43#include <asm/dma.h>
44#include <asm/bfin5xx_spi.h>
45#include <asm/reboot.h>
46#include <asm/nand.h>
47#include <asm/portmux.h>
48#include <asm/dpmc.h>
49#include <linux/spi/ad7877.h>
50
51/*
52 * Name the Board for the /proc/cpuinfo
53 */
fe85cad2 54const char bfin_board_name[] = "ADI BF526-EZBRD";
8cc7117e
MH		 55
56/*
57 * Driver needs to know address, irq and flag pin.
58 */
59
60#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
61static struct resource musb_resources[] = {
62 [0] = {
63 .start = 0xffc03800,
64 .end = 0xffc03cff,
65 .flags = IORESOURCE_MEM,
66 },
67 [1] = { /* general IRQ */
68 .start = IRQ_USB_INT0,
69 .end = IRQ_USB_INT0,
70 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
71 },
72 [2] = { /* DMA IRQ */
73 .start = IRQ_USB_DMA,
74 .end = IRQ_USB_DMA,
75 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
76 },
77};
78
79static struct musb_hdrc_config musb_config = {
80 .multipoint = 0,
81 .dyn_fifo = 0,
82 .soft_con = 1,
83 .dma = 1,
fea05dac
BW		 84 .num_eps = 8,
85 .dma_channels = 8,
8cc7117e
MH		 86 .gpio_vrsel = GPIO_PG13,
87};
88
89static struct musb_hdrc_platform_data musb_plat = {
90#if defined(CONFIG_USB_MUSB_OTG)
91 .mode = MUSB_OTG,
92#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
93 .mode = MUSB_HOST,
94#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
95 .mode = MUSB_PERIPHERAL,
96#endif
97 .config = &musb_config,
98};
99
100static u64 musb_dmamask = ~(u32)0;
101
102static struct platform_device musb_device = {
103 .name = "musb_hdrc",
104 .id = 0,
105 .dev = {
106 .dma_mask = &musb_dmamask,
107 .coherent_dma_mask = 0xffffffff,
108 .platform_data = &musb_plat,
109 },
110 .num_resources = ARRAY_SIZE(musb_resources),
111 .resource = musb_resources,
112};
113#endif
114
115#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
116static struct mtd_partition ezbrd_partitions[] = {
117 {
118 .name = "bootloader(nor)",
119 .size = 0x40000,
120 .offset = 0,
121 }, {
122 .name = "linux kernel(nor)",
123 .size = 0x1C0000,
124 .offset = MTDPART_OFS_APPEND,
125 }, {
126 .name = "file system(nor)",
127 .size = MTDPART_SIZ_FULL,
128 .offset = MTDPART_OFS_APPEND,
129 }
130};
131
132static struct physmap_flash_data ezbrd_flash_data = {
133 .width = 2,
134 .parts = ezbrd_partitions,
135 .nr_parts = ARRAY_SIZE(ezbrd_partitions),
136};
137
138static struct resource ezbrd_flash_resource = {
139 .start = 0x20000000,
140 .end = 0x203fffff,
141 .flags = IORESOURCE_MEM,
142};
143
144static struct platform_device ezbrd_flash_device = {
145 .name = "physmap-flash",
146 .id = 0,
147 .dev = {
148 .platform_data = &ezbrd_flash_data,
149 },
150 .num_resources = 1,
151 .resource = &ezbrd_flash_resource,
152};
153#endif
154
155#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
156static struct mtd_partition partition_info[] = {
157 {
158 .name = "linux kernel(nand)",
159 .offset = 0,
160 .size = 4 * 1024 * 1024,
161 },
162 {
163 .name = "file system(nand)",
164 .offset = MTDPART_OFS_APPEND,
165 .size = MTDPART_SIZ_FULL,
166 },
167};
168
169static struct bf5xx_nand_platform bf5xx_nand_platform = {
170 .page_size = NFC_PG_SIZE_256,
171 .data_width = NFC_NWIDTH_8,
172 .partitions = partition_info,
173 .nr_partitions = ARRAY_SIZE(partition_info),
174 .rd_dly = 3,
175 .wr_dly = 3,
176};
177
178static struct resource bf5xx_nand_resources[] = {
179 {
180 .start = NFC_CTL,
181 .end = NFC_DATA_RD + 2,
182 .flags = IORESOURCE_MEM,
183 },
184 {
185 .start = CH_NFC,
186 .end = CH_NFC,
187 .flags = IORESOURCE_IRQ,
188 },
189};
190
191static struct platform_device bf5xx_nand_device = {
192 .name = "bf5xx-nand",
193 .id = 0,
194 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
195 .resource = bf5xx_nand_resources,
196 .dev = {
197 .platform_data = &bf5xx_nand_platform,
198 },
199};
200#endif
201
202#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
203static struct platform_device rtc_device = {
204 .name = "rtc-bfin",
205 .id = -1,
206};
207#endif
208
209
210#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 211static struct platform_device bfin_mii_bus = {
212 .name = "bfin_mii_bus",
213};
214
8cc7117e
MH		 215static struct platform_device bfin_mac_device = {
216 .name = "bfin_mac",
65319628 217 .dev.platform_data = &bfin_mii_bus,
8cc7117e
MH		 218};
219#endif
220
221#if defined(CONFIG_MTD_M25P80) \
222 || defined(CONFIG_MTD_M25P80_MODULE)
223static struct mtd_partition bfin_spi_flash_partitions[] = {
224 {
225 .name = "bootloader(spi)",
226 .size = 0x00040000,
227 .offset = 0,
228 .mask_flags = MTD_CAP_ROM
229 }, {
230 .name = "linux kernel(spi)",
231 .size = MTDPART_SIZ_FULL,
232 .offset = MTDPART_OFS_APPEND,
233 }
234};
235
236static struct flash_platform_data bfin_spi_flash_data = {
237 .name = "m25p80",
238 .parts = bfin_spi_flash_partitions,
239 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
dc2c46bb 240 .type = "sst25wf040",
8cc7117e
MH		 241};
242
dc2c46bb 243/* SPI flash chip (sst25wf040) */
8cc7117e
MH		 244static struct bfin5xx_spi_chip spi_flash_chip_info = {
245 .enable_dma = 0, /* use dma transfer with this chip*/
246 .bits_per_word = 8,
247};
248#endif
249
a261eec0
MF		 250#if defined(CONFIG_BFIN_SPI_ADC) \
251 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
8cc7117e
MH		 252/* SPI ADC chip */
253static struct bfin5xx_spi_chip spi_adc_chip_info = {
254 .enable_dma = 1, /* use dma transfer with this chip*/
255 .bits_per_word = 16,
256};
257#endif
258
f3f704d3
MH		 259#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
260static struct bfin5xx_spi_chip mmc_spi_chip_info = {
261 .enable_dma = 0,
8cc7117e
MH		 262 .bits_per_word = 8,
263};
264#endif
265
8cc7117e
MH		 266#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
267static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
268 .enable_dma = 0,
269 .bits_per_word = 16,
270};
271
272static const struct ad7877_platform_data bfin_ad7877_ts_info = {
273 .model = 7877,
274 .vref_delay_usecs = 50, /* internal, no capacitor */
275 .x_plate_ohms = 419,
276 .y_plate_ohms = 486,
277 .pressure_max = 1000,
278 .pressure_min = 0,
279 .stopacq_polarity = 1,
280 .first_conversion_delay = 3,
281 .acquisition_time = 1,
282 .averaging = 1,
283 .pen_down_acc_interval = 1,
284};
285#endif
286
5105432a
MH		 287#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
288#include <linux/spi/ad7879.h>
289static const struct ad7879_platform_data bfin_ad7879_ts_info = {
290 .model = 7879, /* Model = AD7879 */
291 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
292 .pressure_max = 10000,
293 .pressure_min = 0,
294 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
295 .acquisition_time = 1, /* 4us acquisition time per sample */
296 .median = 2, /* do 8 measurements */
297 .averaging = 1, /* take the average of 4 middle samples */
298 .pen_down_acc_interval = 255, /* 9.4 ms */
299 .gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */
300 .gpio_default = 1, /* During initialization set GPIO = HIGH */
301};
302#endif
303
304#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
305static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
306 .enable_dma = 0,
307 .bits_per_word = 16,
308};
309#endif
310
8cc7117e
MH		 311#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
312 && defined(CONFIG_SND_SOC_WM8731_SPI)
313static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
314 .enable_dma = 0,
315 .bits_per_word = 16,
316};
317#endif
318
319#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
320static struct bfin5xx_spi_chip spidev_chip_info = {
321 .enable_dma = 0,
322 .bits_per_word = 8,
323};
324#endif
325
326#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
327static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
328 .enable_dma = 0,
329 .bits_per_word = 8,
330};
331#endif
332
333static struct spi_board_info bfin_spi_board_info[] __initdata = {
334#if defined(CONFIG_MTD_M25P80) \
335 || defined(CONFIG_MTD_M25P80_MODULE)
336 {
337 /* the modalias must be the same as spi device driver name */
338 .modalias = "m25p80", /* Name of spi_driver for this device */
339 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
340 .bus_num = 0, /* Framework bus number */
341 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
342 .platform_data = &bfin_spi_flash_data,
343 .controller_data = &spi_flash_chip_info,
344 .mode = SPI_MODE_3,
345 },
346#endif
347
a261eec0
MF		 348#if defined(CONFIG_BFIN_SPI_ADC) \
349 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
8cc7117e
MH		 350 {
351 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
352 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
353 .bus_num = 0, /* Framework bus number */
354 .chip_select = 1, /* Framework chip select. */
355 .platform_data = NULL, /* No spi_driver specific config */
356 .controller_data = &spi_adc_chip_info,
357 },
358#endif
359
f3f704d3 360#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
8cc7117e 361 {
f3f704d3 362 .modalias = "mmc_spi",
8cc7117e
MH		 363 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
364 .bus_num = 0,
f3f704d3
MH		 365 .chip_select = 5,
366 .controller_data = &mmc_spi_chip_info,
8cc7117e
MH		 367 .mode = SPI_MODE_3,
368 },
369#endif
8cc7117e
MH		 370#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
371 {
372 .modalias = "ad7877",
373 .platform_data = &bfin_ad7877_ts_info,
374 .irq = IRQ_PF8,
375 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
376 .bus_num = 0,
377 .chip_select = 2,
378 .controller_data = &spi_ad7877_chip_info,
379 },
380#endif
5105432a
MH		 381#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
382 {
383 .modalias = "ad7879",
384 .platform_data = &bfin_ad7879_ts_info,
385 .irq = IRQ_PG0,
386 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
387 .bus_num = 0,
388 .chip_select = 5,
389 .controller_data = &spi_ad7879_chip_info,
390 .mode = SPI_CPHA | SPI_CPOL,
391 },
392#endif
8cc7117e
MH		 393#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
394 && defined(CONFIG_SND_SOC_WM8731_SPI)
395 {
396 .modalias = "wm8731",
397 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
398 .bus_num = 0,
399 .chip_select = 5,
400 .controller_data = &spi_wm8731_chip_info,
401 .mode = SPI_MODE_0,
402 },
403#endif
404#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
405 {
406 .modalias = "spidev",
407 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
408 .bus_num = 0,
409 .chip_select = 1,
410 .controller_data = &spidev_chip_info,
411 },
412#endif
413#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
414 {
415 .modalias = "bfin-lq035q1-spi",
416 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
417 .bus_num = 0,
418 .chip_select = 1,
419 .controller_data = &lq035q1_spi_chip_info,
420 .mode = SPI_CPHA | SPI_CPOL,
421 },
422#endif
423};
424
425#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
426/* SPI controller data */
427static struct bfin5xx_spi_master bfin_spi0_info = {
428 .num_chipselect = 8,
429 .enable_dma = 1, /* master has the ability to do dma transfer */
430 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
431};
432
433/* SPI (0) */
434static struct resource bfin_spi0_resource[] = {
435 [0] = {
436 .start = SPI0_REGBASE,
437 .end = SPI0_REGBASE + 0xFF,
438 .flags = IORESOURCE_MEM,
439 },
440 [1] = {
441 .start = CH_SPI,
442 .end = CH_SPI,
53122693
YL		 443 .flags = IORESOURCE_DMA,
444 },
445 [2] = {
446 .start = IRQ_SPI,
447 .end = IRQ_SPI,
8cc7117e
MH		 448 .flags = IORESOURCE_IRQ,
449 },
450};
451
452static struct platform_device bfin_spi0_device = {
453 .name = "bfin-spi",
454 .id = 0, /* Bus number */
455 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
456 .resource = bfin_spi0_resource,
457 .dev = {
458 .platform_data = &bfin_spi0_info, /* Passed to driver */
459 },
460};
461#endif /* spi master and devices */
462
463#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
464static struct resource bfin_uart_resources[] = {
465#ifdef CONFIG_SERIAL_BFIN_UART0
466 {
467 .start = 0xFFC00400,
468 .end = 0xFFC004FF,
469 .flags = IORESOURCE_MEM,
470 },
471#endif
472#ifdef CONFIG_SERIAL_BFIN_UART1
473 {
474 .start = 0xFFC02000,
475 .end = 0xFFC020FF,
476 .flags = IORESOURCE_MEM,
477 },
478#endif
479};
480
481static struct platform_device bfin_uart_device = {
482 .name = "bfin-uart",
483 .id = 1,
484 .num_resources = ARRAY_SIZE(bfin_uart_resources),
485 .resource = bfin_uart_resources,
486};
487#endif
488
489#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
8cc7117e 490#ifdef CONFIG_BFIN_SIR0
42bd8bcb 491static struct resource bfin_sir0_resources[] = {
8cc7117e
MH		 492 {
493 .start = 0xFFC00400,
494 .end = 0xFFC004FF,
495 .flags = IORESOURCE_MEM,
496 },
42bd8bcb
GY		 497 {
498 .start = IRQ_UART0_RX,
499 .end = IRQ_UART0_RX+1,
500 .flags = IORESOURCE_IRQ,
501 },
502 {
503 .start = CH_UART0_RX,
504 .end = CH_UART0_RX+1,
505 .flags = IORESOURCE_DMA,
506 },
507};
508
509static struct platform_device bfin_sir0_device = {
510 .name = "bfin_sir",
511 .id = 0,
512 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
513 .resource = bfin_sir0_resources,
514};
8cc7117e
MH		 515#endif
516#ifdef CONFIG_BFIN_SIR1
42bd8bcb 517static struct resource bfin_sir1_resources[] = {
8cc7117e
MH		 518 {
519 .start = 0xFFC02000,
520 .end = 0xFFC020FF,
521 .flags = IORESOURCE_MEM,
522 },
42bd8bcb
GY		 523 {
524 .start = IRQ_UART1_RX,
525 .end = IRQ_UART1_RX+1,
526 .flags = IORESOURCE_IRQ,
527 },
528 {
529 .start = CH_UART1_RX,
530 .end = CH_UART1_RX+1,
531 .flags = IORESOURCE_DMA,
532 },
8cc7117e
MH		 533};
534
42bd8bcb 535static struct platform_device bfin_sir1_device = {
8cc7117e 536 .name = "bfin_sir",
42bd8bcb
GY		 537 .id = 1,
538 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
539 .resource = bfin_sir1_resources,
8cc7117e
MH		 540};
541#endif
42bd8bcb 542#endif
8cc7117e
MH		 543
544#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
545static struct resource bfin_twi0_resource[] = {
546 [0] = {
547 .start = TWI0_REGBASE,
548 .end = TWI0_REGBASE,
549 .flags = IORESOURCE_MEM,
550 },
551 [1] = {
552 .start = IRQ_TWI,
553 .end = IRQ_TWI,
554 .flags = IORESOURCE_IRQ,
555 },
556};
557
558static struct platform_device i2c_bfin_twi_device = {
559 .name = "i2c-bfin-twi",
560 .id = 0,
561 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
562 .resource = bfin_twi0_resource,
563};
564#endif
565
8cc7117e 566static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
ebd58333 567#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
8cc7117e
MH		 568 {
569 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
570 },
571#endif
204844eb 572#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
8cc7117e
MH		 573 {
574 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
575 .irq = IRQ_PF8,
576 },
577#endif
578};
8cc7117e
MH		 579
580#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
581static struct platform_device bfin_sport0_uart_device = {
582 .name = "bfin-sport-uart",
583 .id = 0,
584};
585
586static struct platform_device bfin_sport1_uart_device = {
587 .name = "bfin-sport-uart",
588 .id = 1,
589};
590#endif
591
592#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
593#include <linux/input.h>
594#include <linux/gpio_keys.h>
595
596static struct gpio_keys_button bfin_gpio_keys_table[] = {
597 {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
598 {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
599};
600
601static struct gpio_keys_platform_data bfin_gpio_keys_data = {
602 .buttons = bfin_gpio_keys_table,
603 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
604};
605
606static struct platform_device bfin_device_gpiokeys = {
607 .name = "gpio-keys",
608 .dev = {
609 .platform_data = &bfin_gpio_keys_data,
610 },
611};
612#endif
613
614static struct resource bfin_gpios_resources = {
615 .start = 0,
616 .end = MAX_BLACKFIN_GPIOS - 1,
617 .flags = IORESOURCE_IRQ,
618};
619
620static struct platform_device bfin_gpios_device = {
621 .name = "simple-gpio",
622 .id = -1,
623 .num_resources = 1,
624 .resource = &bfin_gpios_resources,
625};
626
627static const unsigned int cclk_vlev_datasheet[] =
628{
629 VRPAIR(VLEV_100, 400000000),
630 VRPAIR(VLEV_105, 426000000),
631 VRPAIR(VLEV_110, 500000000),
632 VRPAIR(VLEV_115, 533000000),
633 VRPAIR(VLEV_120, 600000000),
634};
635
636static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
637 .tuple_tab = cclk_vlev_datasheet,
638 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
639 .vr_settling_time = 25 /* us */,
640};
641
642static struct platform_device bfin_dpmc = {
643 .name = "bfin dpmc",
644 .dev = {
645 .platform_data = &bfin_dmpc_vreg_data,
646 },
647};
648
649#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
650#include <asm/bfin-lq035q1.h>
651
652static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
653 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
654 .use_bl = 1,
655 .gpio_bl = GPIO_PG12,
656};
657
658static struct resource bfin_lq035q1_resources[] = {
659 {
660 .start = IRQ_PPI_ERROR,
661 .end = IRQ_PPI_ERROR,
662 .flags = IORESOURCE_IRQ,
663 },
664};
665
666static struct platform_device bfin_lq035q1_device = {
667 .name = "bfin-lq035q1",
668 .id = -1,
669 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
670 .resource = bfin_lq035q1_resources,
671 .dev = {
672 .platform_data = &bfin_lq035q1_data,
673 },
674};
675#endif
676
677static struct platform_device *stamp_devices[] __initdata = {
678
679 &bfin_dpmc,
680
681#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
682 &bf5xx_nand_device,
683#endif
684
685#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
686 &rtc_device,
687#endif
688
689#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
690 &musb_device,
691#endif
692
693#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 694 &bfin_mii_bus,
8cc7117e
MH		 695 &bfin_mac_device,
696#endif
697
698#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
699 &bfin_spi0_device,
700#endif
701
702#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
703 &bfin_uart_device,
704#endif
705
706#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
707 &bfin_lq035q1_device,
708#endif
709
710#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 711#ifdef CONFIG_BFIN_SIR0
712 &bfin_sir0_device,
713#endif
714#ifdef CONFIG_BFIN_SIR1
715 &bfin_sir1_device,
716#endif
8cc7117e
MH		 717#endif
718
719#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
720 &i2c_bfin_twi_device,
721#endif
722
723#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
724 &bfin_sport0_uart_device,
725 &bfin_sport1_uart_device,
726#endif
727
728#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
729 &bfin_device_gpiokeys,
730#endif
731
732#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
733 &ezbrd_flash_device,
734#endif
735
736 &bfin_gpios_device,
737};
738
7f6678c5 739static int __init ezbrd_init(void)
8cc7117e
MH		 740{
741 printk(KERN_INFO "%s(): registering device resources\n", __func__);
8cc7117e
MH		 742 i2c_register_board_info(0, bfin_i2c_board_info,
743 ARRAY_SIZE(bfin_i2c_board_info));
8cc7117e
MH		 744 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
745 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
746 return 0;
747}
748
7f6678c5 749arch_initcall(ezbrd_init);
8cc7117e
MH		 750
751void native_machine_restart(char *cmd)
752{
753 /* workaround reboot hang when booting from SPI */
754 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 755 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
8cc7117e
MH		 756}
757
758void bfin_get_ether_addr(char *addr)
759{
760 /* the MAC is stored in OTP memory page 0xDF */
761 u32 ret;
762 u64 otp_mac;
763 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
764
765 ret = otp_read(0xDF, 0x00, &otp_mac);
766 if (!(ret & 0x1)) {
767 char *otp_mac_p = (char *)&otp_mac;
768 for (ret = 0; ret < 6; ++ret)
769 addr[ret] = otp_mac_p[5 - ret];
770 }
771}
772EXPORT_SYMBOL(bfin_get_ether_addr);
Linux kernel - Deliverables
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