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ab472a04 JH |
1 | /* |
2 | * File: arch/blackfin/mach-bf533/H8606.c | |
3 | * Based on: arch/blackfin/mach-bf533/stamp.c | |
4 | * Author: Javier Herrero <jherrero@hvsistemas.es> | |
5 | * | |
6 | * Created: 2007 | |
7 | * Description: Board Info File for the HV Sistemas H8606 board | |
8 | * | |
9 | * Modified: | |
10 | * Copyright 2005 National ICT Australia (NICTA) | |
11 | * Copyright 2004-2006 Analog Devices Inc | |
12 | * Copyright 2007 HV Sistemas S.L. | |
13 | * | |
14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, see the file COPYING, or write | |
28 | * to the Free Software Foundation, Inc., | |
29 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
30 | */ | |
31 | ||
32 | #include <linux/device.h> | |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/mtd/mtd.h> | |
35 | #include <linux/mtd/partitions.h> | |
36 | #include <linux/spi/spi.h> | |
37 | #include <linux/spi/flash.h> | |
38 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | |
39 | #include <linux/usb_isp1362.h> | |
40 | #endif | |
41 | #include <linux/pata_platform.h> | |
42 | #include <linux/irq.h> | |
43 | #include <asm/dma.h> | |
44 | #include <asm/bfin5xx_spi.h> | |
45 | #include <asm/reboot.h> | |
5d448dd5 | 46 | #include <asm/portmux.h> |
ab472a04 JH |
47 | |
48 | /* | |
49 | * Name the Board for the /proc/cpuinfo | |
50 | */ | |
51 | const char bfin_board_name[] = "HV Sistemas H8606"; | |
52 | ||
53 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_BFIN_MODULE) | |
54 | static struct platform_device rtc_device = { | |
55 | .name = "rtc-bfin", | |
56 | .id = -1, | |
57 | }; | |
58 | #endif | |
59 | ||
60 | /* | |
61 | * Driver needs to know address, irq and flag pin. | |
62 | */ | |
63 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | |
64 | static struct resource dm9000_resources[] = { | |
65 | [0] = { | |
66 | .start = 0x20300000, | |
67 | .end = 0x20300000 + 8, | |
68 | .flags = IORESOURCE_MEM, | |
69 | }, | |
70 | [1] = { | |
71 | .start = IRQ_PF10, | |
72 | .end = IRQ_PF10, | |
73 | .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), | |
74 | }, | |
75 | }; | |
76 | ||
77 | static struct platform_device dm9000_device = { | |
78 | .id = 0, | |
79 | .name = "dm9000", | |
80 | .resource = dm9000_resources, | |
81 | .num_resources = ARRAY_SIZE(dm9000_resources), | |
82 | }; | |
83 | #endif | |
84 | ||
85 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | |
86 | static struct resource smc91x_resources[] = { | |
87 | { | |
88 | .name = "smc91x-regs", | |
89 | .start = 0x20300300, | |
90 | .end = 0x20300300 + 16, | |
91 | .flags = IORESOURCE_MEM, | |
92 | }, { | |
93 | .start = IRQ_PROG_INTB, | |
94 | .end = IRQ_PROG_INTB, | |
95 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
96 | }, { | |
ab472a04 JH |
97 | .start = IRQ_PF7, |
98 | .end = IRQ_PF7, | |
99 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
100 | }, | |
101 | }; | |
102 | ||
103 | static struct platform_device smc91x_device = { | |
104 | .name = "smc91x", | |
105 | .id = 0, | |
106 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
107 | .resource = smc91x_resources, | |
108 | }; | |
109 | #endif | |
110 | ||
111 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | |
112 | static struct resource net2272_bfin_resources[] = { | |
113 | { | |
114 | .start = 0x20300000, | |
115 | .end = 0x20300000 + 0x100, | |
116 | .flags = IORESOURCE_MEM, | |
117 | }, { | |
118 | .start = IRQ_PF10, | |
119 | .end = IRQ_PF10, | |
120 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
121 | }, | |
122 | }; | |
123 | ||
124 | static struct platform_device net2272_bfin_device = { | |
125 | .name = "net2272", | |
126 | .id = -1, | |
127 | .num_resources = ARRAY_SIZE(net2272_bfin_resources), | |
128 | .resource = net2272_bfin_resources, | |
129 | }; | |
130 | #endif | |
131 | ||
132 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
133 | /* all SPI peripherals info goes here */ | |
134 | ||
135 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | |
136 | static struct mtd_partition bfin_spi_flash_partitions[] = { | |
137 | { | |
138 | .name = "bootloader", | |
139 | .size = 0x00060000, | |
140 | .offset = 0, | |
141 | .mask_flags = MTD_CAP_ROM | |
142 | }, { | |
143 | .name = "kernel", | |
144 | .size = 0x100000, | |
145 | .offset = 0x60000 | |
146 | }, { | |
147 | .name = "file system", | |
148 | .size = 0x6a0000, | |
149 | .offset = 0x00160000, | |
150 | } | |
151 | }; | |
152 | ||
153 | static struct flash_platform_data bfin_spi_flash_data = { | |
154 | .name = "m25p80", | |
155 | .parts = bfin_spi_flash_partitions, | |
156 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | |
157 | .type = "m25p64", | |
158 | }; | |
159 | ||
160 | /* SPI flash chip (m25p64) */ | |
161 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | |
162 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
163 | .bits_per_word = 8, | |
164 | }; | |
165 | #endif | |
166 | ||
167 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | |
168 | /* SPI ADC chip */ | |
169 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | |
170 | .ctl_reg = 0x1000, | |
171 | .enable_dma = 1, /* use dma transfer with this chip*/ | |
172 | .bits_per_word = 16, | |
173 | }; | |
174 | #endif | |
175 | ||
176 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | |
177 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |
178 | .ctl_reg = 0x1000, | |
179 | .enable_dma = 0, | |
180 | .bits_per_word = 16, | |
181 | }; | |
182 | #endif | |
183 | ||
184 | #if defined(CONFIG_PBX) | |
185 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | |
186 | .ctl_reg = 0x1c04, | |
187 | .enable_dma = 0, | |
188 | .bits_per_word = 8, | |
189 | .cs_change_per_word = 1, | |
190 | }; | |
191 | #endif | |
192 | ||
193 | /* Notice: for blackfin, the speed_hz is the value of register | |
194 | * SPI_BAUD, not the real baudrate */ | |
195 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | |
196 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | |
197 | { | |
198 | /* the modalias must be the same as spi device driver name */ | |
199 | .modalias = "m25p80", /* Name of spi_driver for this device */ | |
200 | /* this value is the baudrate divisor */ | |
201 | .max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */ | |
202 | .bus_num = 0, /* Framework bus number */ | |
203 | .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/ | |
204 | .platform_data = &bfin_spi_flash_data, | |
205 | .controller_data = &spi_flash_chip_info, | |
206 | .mode = SPI_MODE_3, | |
207 | }, | |
208 | #endif | |
209 | ||
210 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | |
211 | { | |
212 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | |
213 | .max_speed_hz = 4, /* actual baudrate is SCLK/(2xspeed_hz) */ | |
214 | .bus_num = 1, /* Framework bus number */ | |
215 | .chip_select = 1, /* Framework chip select. */ | |
216 | .platform_data = NULL, /* No spi_driver specific config */ | |
217 | .controller_data = &spi_adc_chip_info, | |
218 | }, | |
219 | #endif | |
220 | ||
221 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | |
222 | { | |
223 | .modalias = "ad1836-spi", | |
224 | .max_speed_hz = 16, | |
225 | .bus_num = 1, | |
226 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | |
227 | .controller_data = &ad1836_spi_chip_info, | |
228 | }, | |
229 | #endif | |
230 | ||
231 | #if defined(CONFIG_PBX) | |
232 | { | |
233 | .modalias = "fxs-spi", | |
234 | .max_speed_hz = 4, | |
235 | .bus_num = 1, | |
236 | .chip_select = 3, | |
237 | .controller_data = &spi_si3xxx_chip_info, | |
238 | }, | |
239 | ||
240 | { | |
241 | .modalias = "fxo-spi", | |
242 | .max_speed_hz = 4, | |
243 | .bus_num = 1, | |
244 | .chip_select = 2, | |
245 | .controller_data = &spi_si3xxx_chip_info, | |
246 | }, | |
247 | #endif | |
248 | }; | |
249 | ||
250 | /* SPI (0) */ | |
251 | static struct resource bfin_spi0_resource[] = { | |
252 | [0] = { | |
253 | .start = SPI0_REGBASE, | |
254 | .end = SPI0_REGBASE + 0xFF, | |
255 | .flags = IORESOURCE_MEM, | |
256 | }, | |
257 | [1] = { | |
258 | .start = CH_SPI, | |
259 | .end = CH_SPI, | |
260 | .flags = IORESOURCE_IRQ, | |
261 | } | |
262 | }; | |
263 | ||
264 | ||
265 | /* SPI controller data */ | |
266 | static struct bfin5xx_spi_master bfin_spi0_info = { | |
267 | .num_chipselect = 8, | |
268 | .enable_dma = 1, /* master has the ability to do dma transfer */ | |
5d448dd5 | 269 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
ab472a04 JH |
270 | }; |
271 | ||
272 | static struct platform_device bfin_spi0_device = { | |
273 | .name = "bfin-spi", | |
274 | .id = 0, /* Bus number */ | |
275 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
276 | .resource = bfin_spi0_resource, | |
277 | .dev = { | |
278 | .platform_data = &bfin_spi0_info, /* Passed to driver */ | |
279 | }, | |
280 | }; | |
281 | #endif /* spi master and devices */ | |
282 | ||
283 | #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) | |
284 | static struct platform_device bfin_fb_device = { | |
285 | .name = "bf537-fb", | |
286 | }; | |
287 | #endif | |
288 | ||
289 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
290 | static struct resource bfin_uart_resources[] = { | |
291 | { | |
292 | .start = 0xFFC00400, | |
293 | .end = 0xFFC004FF, | |
294 | .flags = IORESOURCE_MEM, | |
295 | }, | |
296 | }; | |
297 | ||
298 | static struct platform_device bfin_uart_device = { | |
299 | .name = "bfin-uart", | |
300 | .id = 1, | |
301 | .num_resources = ARRAY_SIZE(bfin_uart_resources), | |
302 | .resource = bfin_uart_resources, | |
303 | }; | |
304 | #endif | |
305 | ||
306 | static struct platform_device *stamp_devices[] __initdata = { | |
307 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | |
308 | &rtc_device, | |
309 | #endif | |
310 | ||
311 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | |
312 | &dm9000_device, | |
313 | #endif | |
314 | ||
315 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | |
316 | &smc91x_device, | |
317 | #endif | |
318 | ||
319 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | |
320 | &net2272_bfin_device, | |
321 | #endif | |
322 | ||
323 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
324 | &bfin_spi0_device, | |
325 | #endif | |
326 | ||
327 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
328 | &bfin_uart_device, | |
329 | #endif | |
330 | }; | |
331 | ||
332 | static int __init H8606_init(void) | |
333 | { | |
334 | printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n"); | |
335 | printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); | |
336 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); | |
337 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
338 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | |
339 | #endif | |
340 | return 0; | |
341 | } | |
342 | ||
0feea17f | 343 | arch_initcall(H8606_init); |