[Blackfin] arch: remove unused/incorrect definition
[deliverable/linux.git] / arch / blackfin / mach-bf533 / boards / H8606.c
CommitLineData
ab472a04
JH
1/*
2 * File: arch/blackfin/mach-bf533/H8606.c
3 * Based on: arch/blackfin/mach-bf533/stamp.c
4 * Author: Javier Herrero <jherrero@hvsistemas.es>
5 *
6 * Created: 2007
7 * Description: Board Info File for the HV Sistemas H8606 board
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc
12 * Copyright 2007 HV Sistemas S.L.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see the file COPYING, or write
28 * to the Free Software Foundation, Inc.,
29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 */
31
32#include <linux/device.h>
33#include <linux/platform_device.h>
34#include <linux/mtd/mtd.h>
35#include <linux/mtd/partitions.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 39#include <linux/usb/isp1362.h>
ab472a04 40#endif
0a87e3e9 41#include <linux/ata_platform.h>
ab472a04 42#include <linux/irq.h>
fb96c56d 43
ab472a04
JH
44#include <asm/dma.h>
45#include <asm/bfin5xx_spi.h>
46#include <asm/reboot.h>
5d448dd5 47#include <asm/portmux.h>
ab472a04
JH
48
49/*
50 * Name the Board for the /proc/cpuinfo
51 */
52const char bfin_board_name[] = "HV Sistemas H8606";
53
09db9487 54#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
ab472a04
JH
55static struct platform_device rtc_device = {
56 .name = "rtc-bfin",
57 .id = -1,
58};
59#endif
60
61/*
62* Driver needs to know address, irq and flag pin.
63 */
64 #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
65static struct resource dm9000_resources[] = {
66 [0] = {
67 .start = 0x20300000,
68 .end = 0x20300000 + 8,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = IRQ_PF10,
73 .end = IRQ_PF10,
74 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
75 },
76};
77
78static struct platform_device dm9000_device = {
79 .id = 0,
80 .name = "dm9000",
81 .resource = dm9000_resources,
82 .num_resources = ARRAY_SIZE(dm9000_resources),
83};
84#endif
85
86#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
87static struct resource smc91x_resources[] = {
88 {
89 .name = "smc91x-regs",
90 .start = 0x20300300,
91 .end = 0x20300300 + 16,
92 .flags = IORESOURCE_MEM,
93 }, {
94 .start = IRQ_PROG_INTB,
95 .end = IRQ_PROG_INTB,
96 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
97 }, {
ab472a04
JH
98 .start = IRQ_PF7,
99 .end = IRQ_PF7,
100 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
101 },
102};
103
104static struct platform_device smc91x_device = {
105 .name = "smc91x",
106 .id = 0,
107 .num_resources = ARRAY_SIZE(smc91x_resources),
108 .resource = smc91x_resources,
109};
110#endif
111
112#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
113static struct resource net2272_bfin_resources[] = {
114 {
115 .start = 0x20300000,
116 .end = 0x20300000 + 0x100,
117 .flags = IORESOURCE_MEM,
118 }, {
119 .start = IRQ_PF10,
120 .end = IRQ_PF10,
121 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
122 },
123};
124
125static struct platform_device net2272_bfin_device = {
126 .name = "net2272",
127 .id = -1,
128 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
129 .resource = net2272_bfin_resources,
130};
131#endif
132
133#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
134/* all SPI peripherals info goes here */
135
136#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
137static struct mtd_partition bfin_spi_flash_partitions[] = {
138 {
139 .name = "bootloader",
140 .size = 0x00060000,
141 .offset = 0,
142 .mask_flags = MTD_CAP_ROM
143 }, {
144 .name = "kernel",
145 .size = 0x100000,
146 .offset = 0x60000
147 }, {
148 .name = "file system",
149 .size = 0x6a0000,
150 .offset = 0x00160000,
151 }
152};
153
154static struct flash_platform_data bfin_spi_flash_data = {
155 .name = "m25p80",
156 .parts = bfin_spi_flash_partitions,
157 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
158 .type = "m25p64",
159};
160
161/* SPI flash chip (m25p64) */
162static struct bfin5xx_spi_chip spi_flash_chip_info = {
163 .enable_dma = 0, /* use dma transfer with this chip*/
164 .bits_per_word = 8,
165};
166#endif
167
168#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
169/* SPI ADC chip */
170static struct bfin5xx_spi_chip spi_adc_chip_info = {
171 .ctl_reg = 0x1000,
172 .enable_dma = 1, /* use dma transfer with this chip*/
173 .bits_per_word = 16,
174};
175#endif
176
177#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
178static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
179 .ctl_reg = 0x1000,
180 .enable_dma = 0,
181 .bits_per_word = 16,
182};
183#endif
184
185#if defined(CONFIG_PBX)
186static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
187 .ctl_reg = 0x1c04,
188 .enable_dma = 0,
189 .bits_per_word = 8,
190 .cs_change_per_word = 1,
191};
192#endif
193
194/* Notice: for blackfin, the speed_hz is the value of register
195 * SPI_BAUD, not the real baudrate */
196static struct spi_board_info bfin_spi_board_info[] __initdata = {
197#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
198 {
199 /* the modalias must be the same as spi device driver name */
200 .modalias = "m25p80", /* Name of spi_driver for this device */
201 /* this value is the baudrate divisor */
202 .max_speed_hz = 50000000, /* actual baudrate is SCLK/(2xspeed_hz) */
203 .bus_num = 0, /* Framework bus number */
204 .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
205 .platform_data = &bfin_spi_flash_data,
206 .controller_data = &spi_flash_chip_info,
207 .mode = SPI_MODE_3,
208 },
209#endif
210
211#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
212 {
213 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
214 .max_speed_hz = 4, /* actual baudrate is SCLK/(2xspeed_hz) */
215 .bus_num = 1, /* Framework bus number */
216 .chip_select = 1, /* Framework chip select. */
217 .platform_data = NULL, /* No spi_driver specific config */
218 .controller_data = &spi_adc_chip_info,
219 },
220#endif
221
222#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
223 {
224 .modalias = "ad1836-spi",
225 .max_speed_hz = 16,
226 .bus_num = 1,
227 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
228 .controller_data = &ad1836_spi_chip_info,
229 },
230#endif
231
232#if defined(CONFIG_PBX)
233 {
234 .modalias = "fxs-spi",
235 .max_speed_hz = 4,
236 .bus_num = 1,
237 .chip_select = 3,
238 .controller_data = &spi_si3xxx_chip_info,
239 },
240
241 {
242 .modalias = "fxo-spi",
243 .max_speed_hz = 4,
244 .bus_num = 1,
245 .chip_select = 2,
246 .controller_data = &spi_si3xxx_chip_info,
247 },
248#endif
249};
250
251/* SPI (0) */
252static struct resource bfin_spi0_resource[] = {
253 [0] = {
254 .start = SPI0_REGBASE,
255 .end = SPI0_REGBASE + 0xFF,
256 .flags = IORESOURCE_MEM,
257 },
258 [1] = {
259 .start = CH_SPI,
260 .end = CH_SPI,
261 .flags = IORESOURCE_IRQ,
262 }
263};
264
265
266/* SPI controller data */
267static struct bfin5xx_spi_master bfin_spi0_info = {
268 .num_chipselect = 8,
269 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 270 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
ab472a04
JH
271};
272
273static struct platform_device bfin_spi0_device = {
274 .name = "bfin-spi",
275 .id = 0, /* Bus number */
276 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
277 .resource = bfin_spi0_resource,
278 .dev = {
279 .platform_data = &bfin_spi0_info, /* Passed to driver */
280 },
281};
282#endif /* spi master and devices */
283
284#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
285static struct platform_device bfin_fb_device = {
286 .name = "bf537-fb",
287};
288#endif
289
290#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
291static struct resource bfin_uart_resources[] = {
292 {
293 .start = 0xFFC00400,
294 .end = 0xFFC004FF,
295 .flags = IORESOURCE_MEM,
296 },
297};
298
299static struct platform_device bfin_uart_device = {
300 .name = "bfin-uart",
301 .id = 1,
302 .num_resources = ARRAY_SIZE(bfin_uart_resources),
303 .resource = bfin_uart_resources,
304};
305#endif
306
fb96c56d
JH
307#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
308
309#include <linux/serial_8250.h>
310#include <linux/serial.h>
311
312/*
313 * Configuration for two 16550 UARTS in FPGA at addresses 0x20200000 and 0x202000010.
314 * running at half system clock, both with interrupt output or-ed to PF8. Change to
315 * suit different FPGA configuration, or to suit real 16550 UARTS connected to the bus
316 */
317
318static struct plat_serial8250_port serial8250_platform_data [] = {
319 {
320 .membase = 0x20200000,
321 .mapbase = 0x20200000,
322 .irq = IRQ_PF8,
323 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
324 .iotype = UPIO_MEM,
325 .regshift = 1,
326 .uartclk = 66666667,
327 }, {
328 .membase = 0x20200010,
329 .mapbase = 0x20200010,
330 .irq = IRQ_PF8,
331 .flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
332 .iotype = UPIO_MEM,
333 .regshift = 1,
334 .uartclk = 66666667,
335 }, {
336 }
337};
338
339static struct platform_device serial8250_device = {
340 .id = PLAT8250_DEV_PLATFORM,
341 .name = "serial8250",
342 .dev = {
343 .platform_data = serial8250_platform_data,
344 },
345};
346
347#endif
348
7a5f8191
JH
349#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
350
351/*
352 * Configuration for one OpenCores keyboard controller in FPGA at address 0x20200030,
353 * interrupt output wired to PF9. Change to suit different FPGA configuration
354 */
355
356static struct resource opencores_kbd_resources[] = {
357 [0] = {
358 .start = 0x20200030,
359 .end = 0x20300030 + 2,
360 .flags = IORESOURCE_MEM,
361 },
362 [1] = {
363 .start = IRQ_PF9,
364 .end = IRQ_PF9,
365 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
366 },
367};
368
369static struct platform_device opencores_kbd_device = {
370 .id = -1,
371 .name = "opencores-kbd",
372 .resource = opencores_kbd_resources,
373 .num_resources = ARRAY_SIZE(opencores_kbd_resources),
374};
375#endif
376
fb96c56d 377static struct platform_device *h8606_devices[] __initdata = {
ab472a04
JH
378#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
379 &rtc_device,
380#endif
381
382#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
383 &dm9000_device,
384#endif
385
386#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
387 &smc91x_device,
388#endif
389
390#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
391 &net2272_bfin_device,
392#endif
393
394#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
395 &bfin_spi0_device,
396#endif
397
398#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
399 &bfin_uart_device,
400#endif
fb96c56d
JH
401
402#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
403 &serial8250_device,
404#endif
7a5f8191
JH
405
406#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
407 &opencores_kbd_device,
408#endif
ab472a04
JH
409};
410
411static int __init H8606_init(void)
412{
413 printk(KERN_INFO "HV Sistemas H8606 board support by http://www.hvsistemas.com\n");
414 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
fb96c56d 415 platform_add_devices(h8606_devices, ARRAY_SIZE(h8606_devices));
ab472a04
JH
416#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
417 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
418#endif
419 return 0;
420}
421
0feea17f 422arch_initcall(H8606_init);
This page took 0.091055 seconds and 5 git commands to generate.