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Blackfin: boards: clean up redundant/dead spi resources
[deliverable/linux.git] / arch / blackfin / mach-bf533 / boards / cm_bf533.c
CommitLineData
1394f032 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
1394f032 6 *
96f1050d 7 * Licensed under the GPL-2 or later.
1394f032
BW		 8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
9c21453e 14#include <linux/mtd/physmap.h>
1394f032
BW		 15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
9c21453e 17#include <linux/spi/mmc_spi.h>
b964c592 18#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 19#include <linux/usb/isp1362.h>
b964c592 20#endif
1f83b8f1 21#include <linux/irq.h>
c6c4d7bb 22#include <asm/dma.h>
1394f032 23#include <asm/bfin5xx_spi.h>
5d448dd5 24#include <asm/portmux.h>
14b03204 25#include <asm/dpmc.h>
1394f032
BW		 26
27/*
28 * Name the Board for the /proc/cpuinfo
29 */
066954a3 30const char bfin_board_name[] = "Bluetechnix CM BF533";
1394f032
BW		 31
32#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
33/* all SPI peripherals info goes here */
a15c2dcf 34#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
1394f032
BW		 35static struct mtd_partition bfin_spi_flash_partitions[] = {
36 {
aa582977 37 .name = "bootloader(spi)",
1394f032
BW		 38 .size = 0x00020000,
39 .offset = 0,
40 .mask_flags = MTD_CAP_ROM
1f83b8f1 41 }, {
aa582977 42 .name = "linux kernel(spi)",
1394f032
BW		 43 .size = 0xe0000,
44 .offset = 0x20000
1f83b8f1 45 }, {
aa582977 46 .name = "file system(spi)",
1394f032
BW		 47 .size = 0x700000,
48 .offset = 0x00100000,
49 }
50};
51
52static struct flash_platform_data bfin_spi_flash_data = {
53 .name = "m25p80",
54 .parts = bfin_spi_flash_partitions,
55 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
56 .type = "m25p64",
57};
58
59/* SPI flash chip (m25p64) */
60static struct bfin5xx_spi_chip spi_flash_chip_info = {
61 .enable_dma = 0, /* use dma transfer with this chip*/
1394f032
BW		 62};
63#endif
64
f3f704d3
MH		 65#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
66static struct bfin5xx_spi_chip mmc_spi_chip_info = {
67 .enable_dma = 0,
a15c2dcf
MH		 68};
69#endif
70
1394f032 71static struct spi_board_info bfin_spi_board_info[] __initdata = {
a15c2dcf 72#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
1394f032
BW		 73 {
74 /* the modalias must be the same as spi device driver name */
75 .modalias = "m25p80", /* Name of spi_driver for this device */
76 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 77 .bus_num = 0, /* Framework bus number */
1394f032
BW		 78 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
79 .platform_data = &bfin_spi_flash_data,
80 .controller_data = &spi_flash_chip_info,
81 .mode = SPI_MODE_3,
a15c2dcf
MH		 82 },
83#endif
84
7ba80063 85#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
1394f032 86 {
7ba80063 87 .modalias = "ad183x",
1394f032 88 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 89 .bus_num = 0,
7ba80063 90 .chip_select = 4,
1394f032
BW		 91 },
92#endif
a15c2dcf 93
f3f704d3 94#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
a15c2dcf 95 {
f3f704d3 96 .modalias = "mmc_spi",
9c21453e 97 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
a15c2dcf 98 .bus_num = 0,
9c21453e 99 .chip_select = 1,
f3f704d3 100 .controller_data = &mmc_spi_chip_info,
a15c2dcf
MH		 101 .mode = SPI_MODE_3,
102 },
103#endif
1394f032
BW		 104};
105
c6c4d7bb
BW		 106/* SPI (0) */
107static struct resource bfin_spi0_resource[] = {
108 [0] = {
109 .start = SPI0_REGBASE,
110 .end = SPI0_REGBASE + 0xFF,
111 .flags = IORESOURCE_MEM,
112 },
113 [1] = {
114 .start = CH_SPI,
115 .end = CH_SPI,
53122693
YL		 116 .flags = IORESOURCE_DMA,
117 },
118 [2] = {
119 .start = IRQ_SPI,
120 .end = IRQ_SPI,
c6c4d7bb
BW		 121 .flags = IORESOURCE_IRQ,
122 }
123};
124
1394f032 125/* SPI controller data */
c6c4d7bb 126static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032
BW		 127 .num_chipselect = 8,
128 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 129 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW		 130};
131
c6c4d7bb
BW		 132static struct platform_device bfin_spi0_device = {
133 .name = "bfin-spi",
134 .id = 0, /* Bus number */
135 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
136 .resource = bfin_spi0_resource,
1394f032 137 .dev = {
c6c4d7bb 138 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW		 139 },
140};
141#endif /* spi master and devices */
142
143#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
144static struct platform_device rtc_device = {
145 .name = "rtc-bfin",
146 .id = -1,
147};
148#endif
149
150#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 151#include <linux/smc91x.h>
152
153static struct smc91x_platdata smc91x_info = {
154 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
155 .leda = RPC_LED_100_10,
156 .ledb = RPC_LED_TX_RX,
157};
158
1394f032
BW		 159static struct resource smc91x_resources[] = {
160 {
161 .start = 0x20200300,
162 .end = 0x20200300 + 16,
163 .flags = IORESOURCE_MEM,
1f83b8f1 164 }, {
1394f032
BW		 165 .start = IRQ_PF0,
166 .end = IRQ_PF0,
167 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
168 },
169};
170static struct platform_device smc91x_device = {
171 .name = "smc91x",
172 .id = 0,
173 .num_resources = ARRAY_SIZE(smc91x_resources),
174 .resource = smc91x_resources,
61f09b5a
MH		 175 .dev = {
176 .platform_data = &smc91x_info,
177 },
1394f032
BW		 178};
179#endif
180
9c21453e
HK		 181#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
182#include <linux/smsc911x.h>
183
184static struct resource smsc911x_resources[] = {
185 {
186 .name = "smsc911x-memory",
187 .start = 0x20308000,
188 .end = 0x20308000 + 0xFF,
189 .flags = IORESOURCE_MEM,
190 }, {
191 .start = IRQ_PF8,
192 .end = IRQ_PF8,
193 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
194 },
195};
196
197static struct smsc911x_platform_config smsc911x_config = {
198 .flags = SMSC911X_USE_16BIT,
199 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
200 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
201 .phy_interface = PHY_INTERFACE_MODE_MII,
202};
203
204static struct platform_device smsc911x_device = {
205 .name = "smsc911x",
206 .id = 0,
207 .num_resources = ARRAY_SIZE(smsc911x_resources),
208 .resource = smsc911x_resources,
209 .dev = {
210 .platform_data = &smsc911x_config,
211 },
212};
213#endif
214
1394f032 215#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 216#ifdef CONFIG_SERIAL_BFIN_UART0
217static struct resource bfin_uart0_resources[] = {
1394f032 218 {
6bd1fbea
SZ		 219 .start = BFIN_UART_THR,
220 .end = BFIN_UART_GCTL+2,
1394f032
BW		 221 .flags = IORESOURCE_MEM,
222 },
6bd1fbea
SZ		 223 {
224 .start = IRQ_UART0_RX,
225 .end = IRQ_UART0_RX + 1,
226 .flags = IORESOURCE_IRQ,
227 },
228 {
229 .start = IRQ_UART0_ERROR,
230 .end = IRQ_UART0_ERROR,
231 .flags = IORESOURCE_IRQ,
232 },
233 {
234 .start = CH_UART0_TX,
235 .end = CH_UART0_TX,
236 .flags = IORESOURCE_DMA,
237 },
238 {
239 .start = CH_UART0_RX,
240 .end = CH_UART0_RX,
241 .flags = IORESOURCE_DMA,
242 },
243};
244
a8b19886 245static unsigned short bfin_uart0_peripherals[] = {
6bd1fbea 246 P_UART0_TX, P_UART0_RX, 0
1394f032
BW		 247};
248
6bd1fbea 249static struct platform_device bfin_uart0_device = {
1394f032 250 .name = "bfin-uart",
6bd1fbea
SZ		 251 .id = 0,
252 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
253 .resource = bfin_uart0_resources,
254 .dev = {
255 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
256 },
1394f032
BW		 257};
258#endif
6bd1fbea 259#endif
1394f032 260
5be36d22 261#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 262#ifdef CONFIG_BFIN_SIR0
42bd8bcb 263static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 264 {
265 .start = 0xFFC00400,
266 .end = 0xFFC004FF,
267 .flags = IORESOURCE_MEM,
268 },
42bd8bcb
GY		 269 {
270 .start = IRQ_UART0_RX,
271 .end = IRQ_UART0_RX+1,
272 .flags = IORESOURCE_IRQ,
273 },
274 {
275 .start = CH_UART0_RX,
276 .end = CH_UART0_RX+1,
277 .flags = IORESOURCE_DMA,
278 },
5be36d22
GY		 279};
280
42bd8bcb 281static struct platform_device bfin_sir0_device = {
5be36d22
GY		 282 .name = "bfin_sir",
283 .id = 0,
42bd8bcb
GY		 284 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
285 .resource = bfin_sir0_resources,
5be36d22
GY		 286};
287#endif
42bd8bcb 288#endif
5be36d22 289
1394f032 290#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 291#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
292static struct resource bfin_sport0_uart_resources[] = {
293 {
294 .start = SPORT0_TCR1,
295 .end = SPORT0_MRCS3+4,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .start = IRQ_SPORT0_RX,
300 .end = IRQ_SPORT0_RX+1,
301 .flags = IORESOURCE_IRQ,
302 },
303 {
304 .start = IRQ_SPORT0_ERROR,
305 .end = IRQ_SPORT0_ERROR,
306 .flags = IORESOURCE_IRQ,
307 },
308};
309
a8b19886 310static unsigned short bfin_sport0_peripherals[] = {
df5de261 311 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
e54b6730 312 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
df5de261
SZ		 313};
314
1394f032
BW		 315static struct platform_device bfin_sport0_uart_device = {
316 .name = "bfin-sport-uart",
317 .id = 0,
df5de261
SZ		 318 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
319 .resource = bfin_sport0_uart_resources,
320 .dev = {
321 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
322 },
323};
324#endif
325#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
326static struct resource bfin_sport1_uart_resources[] = {
327 {
328 .start = SPORT1_TCR1,
329 .end = SPORT1_MRCS3+4,
330 .flags = IORESOURCE_MEM,
331 },
332 {
333 .start = IRQ_SPORT1_RX,
334 .end = IRQ_SPORT1_RX+1,
335 .flags = IORESOURCE_IRQ,
336 },
337 {
338 .start = IRQ_SPORT1_ERROR,
339 .end = IRQ_SPORT1_ERROR,
340 .flags = IORESOURCE_IRQ,
341 },
342};
343
a8b19886 344static unsigned short bfin_sport1_peripherals[] = {
df5de261 345 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
e54b6730 346 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
1394f032
BW		 347};
348
349static struct platform_device bfin_sport1_uart_device = {
350 .name = "bfin-sport-uart",
351 .id = 1,
df5de261
SZ		 352 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
353 .resource = bfin_sport1_uart_resources,
354 .dev = {
355 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
356 },
1394f032
BW		 357};
358#endif
df5de261 359#endif
1394f032
BW		 360
361#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
362static struct resource isp1362_hcd_resources[] = {
363 {
364 .start = 0x20308000,
365 .end = 0x20308000,
366 .flags = IORESOURCE_MEM,
1f83b8f1 367 }, {
1394f032
BW		 368 .start = 0x20308004,
369 .end = 0x20308004,
370 .flags = IORESOURCE_MEM,
1f83b8f1 371 }, {
1394f032
BW		 372 .start = IRQ_PF4,
373 .end = IRQ_PF4,
9e75894c 374 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
1394f032
BW		 375 },
376};
377
378static struct isp1362_platform_data isp1362_priv = {
379 .sel15Kres = 1,
380 .clknotstop = 0,
381 .oc_enable = 0,
382 .int_act_high = 0,
383 .int_edge_triggered = 0,
384 .remote_wakeup_connected = 0,
385 .no_power_switching = 1,
386 .power_switching_mode = 0,
387};
388
389static struct platform_device isp1362_hcd_device = {
390 .name = "isp1362-hcd",
391 .id = 0,
392 .dev = {
393 .platform_data = &isp1362_priv,
394 },
395 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
396 .resource = isp1362_hcd_resources,
397};
398#endif
399
9c21453e
HK		 400
401#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
402static struct resource net2272_bfin_resources[] = {
403 {
404 .start = 0x20300000,
405 .end = 0x20300000 + 0x100,
406 .flags = IORESOURCE_MEM,
407 }, {
408 .start = IRQ_PF6,
409 .end = IRQ_PF6,
410 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
411 },
412};
413
414static struct platform_device net2272_bfin_device = {
415 .name = "net2272",
416 .id = -1,
417 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
418 .resource = net2272_bfin_resources,
419};
420#endif
421
422
423
424#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
425static struct mtd_partition para_partitions[] = {
426 {
427 .name = "bootloader(nor)",
428 .size = 0x40000,
429 .offset = 0,
430 }, {
431 .name = "linux+rootfs(nor)",
432 .size = MTDPART_SIZ_FULL,
433 .offset = MTDPART_OFS_APPEND,
434 },
435};
436
437static struct physmap_flash_data para_flash_data = {
438 .width = 2,
439 .parts = para_partitions,
440 .nr_parts = ARRAY_SIZE(para_partitions),
441};
442
443static struct resource para_flash_resource = {
444 .start = 0x20000000,
445 .end = 0x201fffff,
446 .flags = IORESOURCE_MEM,
447};
448
449static struct platform_device para_flash_device = {
450 .name = "physmap-flash",
451 .id = 0,
452 .dev = {
453 .platform_data = &para_flash_data,
454 },
455 .num_resources = 1,
456 .resource = &para_flash_resource,
457};
458#endif
459
460
461
14b03204
MH		 462static const unsigned int cclk_vlev_datasheet[] =
463{
464 VRPAIR(VLEV_085, 250000000),
465 VRPAIR(VLEV_090, 376000000),
466 VRPAIR(VLEV_095, 426000000),
467 VRPAIR(VLEV_100, 426000000),
468 VRPAIR(VLEV_105, 476000000),
469 VRPAIR(VLEV_110, 476000000),
470 VRPAIR(VLEV_115, 476000000),
471 VRPAIR(VLEV_120, 600000000),
472 VRPAIR(VLEV_125, 600000000),
473 VRPAIR(VLEV_130, 600000000),
474};
475
476static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
477 .tuple_tab = cclk_vlev_datasheet,
478 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
479 .vr_settling_time = 25 /* us */,
480};
481
482static struct platform_device bfin_dpmc = {
483 .name = "bfin dpmc",
484 .dev = {
485 .platform_data = &bfin_dmpc_vreg_data,
486 },
487};
488
1394f032 489static struct platform_device *cm_bf533_devices[] __initdata = {
14b03204
MH		 490
491 &bfin_dpmc,
492
1394f032 493#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 494#ifdef CONFIG_SERIAL_BFIN_UART0
495 &bfin_uart0_device,
496#endif
1394f032
BW		 497#endif
498
5be36d22 499#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 500#ifdef CONFIG_BFIN_SIR0
501 &bfin_sir0_device,
502#endif
5be36d22
GY		 503#endif
504
1394f032 505#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 506#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1394f032 507 &bfin_sport0_uart_device,
df5de261
SZ		 508#endif
509#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1394f032
BW		 510 &bfin_sport1_uart_device,
511#endif
df5de261 512#endif
1394f032
BW		 513
514#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
515 &rtc_device,
516#endif
517
518#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
519 &isp1362_hcd_device,
520#endif
521
522#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
523 &smc91x_device,
524#endif
525
9c21453e
HK		 526#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
527 &smsc911x_device,
528#endif
529
530#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
531 &net2272_bfin_device,
532#endif
533
1394f032 534#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb
BW		 535 &bfin_spi0_device,
536#endif
c97618d3 537
9c21453e
HK		 538#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
539 &para_flash_device,
540#endif
1394f032
BW		 541};
542
543static int __init cm_bf533_init(void)
544{
b85d858b 545 printk(KERN_INFO "%s(): registering device resources\n", __func__);
1394f032
BW		 546 platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
547#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
548 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
549#endif
550 return 0;
551}
552
553arch_initcall(cm_bf533_init);
c13ce9fd
SZ		 554
555static struct platform_device *cm_bf533_early_devices[] __initdata = {
556#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
557#ifdef CONFIG_SERIAL_BFIN_UART0
558 &bfin_uart0_device,
559#endif
560#endif
561
562#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
563#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
564 &bfin_sport0_uart_device,
565#endif
566#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
567 &bfin_sport1_uart_device,
568#endif
569#endif
570};
571
572void __init native_machine_early_platform_add_devices(void)
573{
574 printk(KERN_INFO "register early platform devices\n");
575 early_platform_add_devices(cm_bf533_early_devices,
576 ARRAY_SIZE(cm_bf533_early_devices));
577}
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