[deliverable/linux.git] / arch / blackfin / mach-bf533 / boards / cm_bf533.c

/*
 * File:         arch/blackfin/mach-bf533/boards/cm_bf533.c
 * Based on:     arch/blackfin/mach-bf533/boards/ezkit.c
 * Author:       Aidan Williams <aidan@nicta.com.au> Copyright 2005
 *
 * Created:      2005
 * Description:  Board description file
 *
 * Modified:
 *               Copyright 2004-2006 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/usb_isp1362.h>
#include <linux/pata_platform.h>
#include <linux/irq.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>

/*
 * Name the Board for the /proc/cpuinfo
 */
const char bfin_board_name[] = "Bluetechnix CM BF533";

#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* all SPI peripherals info goes here */
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
static struct mtd_partition bfin_spi_flash_partitions[] = {
	{
		.name = "bootloader",
		.size = 0x00020000,
		.offset = 0,
		.mask_flags = MTD_CAP_ROM
	}, {
		.name = "kernel",
		.size = 0xe0000,
		.offset = 0x20000
	}, {
		.name = "file system",
		.size = 0x700000,
		.offset = 0x00100000,
	}
};

static struct flash_platform_data bfin_spi_flash_data = {
	.name = "m25p80",
	.parts = bfin_spi_flash_partitions,
	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
	.type = "m25p64",
};

/* SPI flash chip (m25p64) */
static struct bfin5xx_spi_chip spi_flash_chip_info = {
	.enable_dma = 0,         /* use dma transfer with this chip*/
	.bits_per_word = 8,
};
#endif

/* SPI ADC chip */
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
static struct bfin5xx_spi_chip spi_adc_chip_info = {
	.enable_dma = 1,         /* use dma transfer with this chip*/
	.bits_per_word = 16,
};
#endif

#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
	.enable_dma = 0,
	.bits_per_word = 16,
};
#endif

#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
	.enable_dma = 1,
	.bits_per_word = 8,
};
#endif

static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
	{
		/* the modalias must be the same as spi device driver name */
		.modalias = "m25p80",       /* Name of spi_driver for this device */
		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,               /* Framework bus number */
		.chip_select = 1,           /* Framework chip select. On STAMP537 it is SPISSEL1*/
		.platform_data = &bfin_spi_flash_data,
		.controller_data = &spi_flash_chip_info,
		.mode = SPI_MODE_3,
	},
#endif

#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
	{
		.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
		.max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,               /* Framework bus number */
		.chip_select = 2,           /* Framework chip select. */
		.platform_data = NULL,      /* No spi_driver specific config */
		.controller_data = &spi_adc_chip_info,
	},
#endif

#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
	{
		.modalias = "ad1836-spi",
		.max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
		.controller_data = &ad1836_spi_chip_info,
	},
#endif

#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
	{
		.modalias = "spi_mmc_dummy",
		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = 0,
		.platform_data = NULL,
		.controller_data = &spi_mmc_chip_info,
		.mode = SPI_MODE_3,
	},
	{
		.modalias = "spi_mmc",
		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = CONFIG_SPI_MMC_CS_CHAN,
		.platform_data = NULL,
		.controller_data = &spi_mmc_chip_info,
		.mode = SPI_MODE_3,
	},
#endif
};

/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
	[0] = {
		.start = SPI0_REGBASE,
		.end   = SPI0_REGBASE + 0xFF,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = CH_SPI,
		.end   = CH_SPI,
		.flags = IORESOURCE_IRQ,
	}
};

/* SPI controller data */
static struct bfin5xx_spi_master bfin_spi0_info = {
	.num_chipselect = 8,
	.enable_dma = 1,  /* master has the ability to do dma transfer */
};

static struct platform_device bfin_spi0_device = {
	.name = "bfin-spi",
	.id = 0, /* Bus number */
	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
	.resource = bfin_spi0_resource,
	.dev = {
		.platform_data = &bfin_spi0_info, /* Passed to driver */
	},
};
#endif  /* spi master and devices */

#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
static struct platform_device rtc_device = {
	.name = "rtc-bfin",
	.id   = -1,
};
#endif

#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
static struct resource smc91x_resources[] = {
	{
		.start = 0x20200300,
		.end = 0x20200300 + 16,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IRQ_PF0,
		.end = IRQ_PF0,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};
static struct platform_device smc91x_device = {
	.name = "smc91x",
	.id = 0,
	.num_resources = ARRAY_SIZE(smc91x_resources),
	.resource = smc91x_resources,
};
#endif

#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
static struct resource bfin_uart_resources[] = {
	{
		.start = 0xFFC00400,
		.end = 0xFFC004FF,
		.flags = IORESOURCE_MEM,
	},
};

static struct platform_device bfin_uart_device = {
	.name = "bfin-uart",
	.id = 1,
	.num_resources = ARRAY_SIZE(bfin_uart_resources),
	.resource = bfin_uart_resources,
};
#endif

#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
static struct platform_device bfin_sport0_uart_device = {
	.name = "bfin-sport-uart",
	.id = 0,
};

static struct platform_device bfin_sport1_uart_device = {
	.name = "bfin-sport-uart",
	.id = 1,
};
#endif

#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
static struct resource isp1362_hcd_resources[] = {
	{
		.start = 0x20308000,
		.end = 0x20308000,
		.flags = IORESOURCE_MEM,
	}, {
		.start = 0x20308004,
		.end = 0x20308004,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IRQ_PF4,
		.end = IRQ_PF4,
		.flags = IORESOURCE_IRQ,
	},
};

static struct isp1362_platform_data isp1362_priv = {
	.sel15Kres = 1,
	.clknotstop = 0,
	.oc_enable = 0,
	.int_act_high = 0,
	.int_edge_triggered = 0,
	.remote_wakeup_connected = 0,
	.no_power_switching = 1,
	.power_switching_mode = 0,
};

static struct platform_device isp1362_hcd_device = {
	.name = "isp1362-hcd",
	.id = 0,
	.dev = {
		.platform_data = &isp1362_priv,
	},
	.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
	.resource = isp1362_hcd_resources,
};
#endif

#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
#define PATA_INT	38

static struct pata_platform_info bfin_pata_platform_data = {
	.ioport_shift = 2,
	.irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
};

static struct resource bfin_pata_resources[] = {
	{
		.start = 0x2030C000,
		.end = 0x2030C01F,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = 0x2030D018,
		.end = 0x2030D01B,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = PATA_INT,
		.end = PATA_INT,
		.flags = IORESOURCE_IRQ,
	},
};

static struct platform_device bfin_pata_device = {
	.name = "pata_platform",
	.id = -1,
	.num_resources = ARRAY_SIZE(bfin_pata_resources),
	.resource = bfin_pata_resources,
	.dev = {
		.platform_data = &bfin_pata_platform_data,
	}
};
#endif

static struct platform_device *cm_bf533_devices[] __initdata = {
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
	&bfin_uart_device,
#endif

#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
	&bfin_sport0_uart_device,
	&bfin_sport1_uart_device,
#endif

#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
	&rtc_device,
#endif

#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
	&isp1362_hcd_device,
#endif

#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
	&smc91x_device,
#endif

#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
	&bfin_spi0_device,
#endif

#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
	&bfin_pata_device,
#endif
};

static int __init cm_bf533_init(void)
{
	printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
	platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
#endif

#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
	irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
#endif
	return 0;
}

arch_initcall(cm_bf533_init);
Commit	Line	Data
1394f032 BW	1	/*
	2	* File: arch/blackfin/mach-bf533/boards/cm_bf533.c
	3	* Based on: arch/blackfin/mach-bf533/boards/ezkit.c
d2d50aa9	4	* Author: Aidan Williams <aidan@nicta.com.au> Copyright 2005
1394f032 BW	5	*
	6	* Created: 2005
	7	* Description: Board description file
	8	*
	9	* Modified:
	10	* Copyright 2004-2006 Analog Devices Inc.
	11	*
	12	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, see the file COPYING, or write
	26	* to the Free Software Foundation, Inc.,
	27	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	28	*/
	29
	30	#include <linux/device.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/mtd/mtd.h>
	33	#include <linux/mtd/partitions.h>
	34	#include <linux/spi/spi.h>
	35	#include <linux/spi/flash.h>
	36	#include <linux/usb_isp1362.h>
c6c4d7bb	37	#include <linux/pata_platform.h>
1f83b8f1	38	#include <linux/irq.h>
c6c4d7bb	39	#include <asm/dma.h>
1394f032 BW	40	#include <asm/bfin5xx_spi.h>
	41
	42	/*
	43	* Name the Board for the /proc/cpuinfo
	44	*/
066954a3	45	const char bfin_board_name[] = "Bluetechnix CM BF533";
1394f032 BW	46
	47	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
	48	/* all SPI peripherals info goes here */
a15c2dcf	49	#if defined(CONFIG_MTD_M25P80) \|\| defined(CONFIG_MTD_M25P80_MODULE)
1394f032 BW	50	static struct mtd_partition bfin_spi_flash_partitions[] = {
	51	{
	52	.name = "bootloader",
	53	.size = 0x00020000,
	54	.offset = 0,
	55	.mask_flags = MTD_CAP_ROM
1f83b8f1	56	}, {
1394f032 BW	57	.name = "kernel",
	58	.size = 0xe0000,
	59	.offset = 0x20000
1f83b8f1	60	}, {
1394f032 BW	61	.name = "file system",
	62	.size = 0x700000,
	63	.offset = 0x00100000,
	64	}
	65	};
	66
	67	static struct flash_platform_data bfin_spi_flash_data = {
	68	.name = "m25p80",
	69	.parts = bfin_spi_flash_partitions,
	70	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
	71	.type = "m25p64",
	72	};
	73
	74	/* SPI flash chip (m25p64) */
	75	static struct bfin5xx_spi_chip spi_flash_chip_info = {
	76	.enable_dma = 0, /* use dma transfer with this chip*/
	77	.bits_per_word = 8,
	78	};
a15c2dcf	79	#endif
1394f032 BW	80
1394f032 BW	81	/* SPI ADC chip */
a15c2dcf	82	#if defined(CONFIG_SPI_ADC_BF533) \|\| defined(CONFIG_SPI_ADC_BF533_MODULE)
1394f032 BW	83	static struct bfin5xx_spi_chip spi_adc_chip_info = {
	84	.enable_dma = 1, /* use dma transfer with this chip*/
	85	.bits_per_word = 16,
	86	};
a15c2dcf	87	#endif
1394f032 BW	88
	89	#if defined(CONFIG_SND_BLACKFIN_AD1836) \|\| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
	90	static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
	91	.enable_dma = 0,
	92	.bits_per_word = 16,
	93	};
	94	#endif
	95
a15c2dcf MH	96	#if defined(CONFIG_SPI_MMC) \|\| defined(CONFIG_SPI_MMC_MODULE)
	97	static struct bfin5xx_spi_chip spi_mmc_chip_info = {
	98	.enable_dma = 1,
	99	.bits_per_word = 8,
	100	};
	101	#endif
	102
1394f032	103	static struct spi_board_info bfin_spi_board_info[] __initdata = {
a15c2dcf	104	#if defined(CONFIG_MTD_M25P80) \|\| defined(CONFIG_MTD_M25P80_MODULE)
1394f032 BW	105	{
	106	/* the modalias must be the same as spi device driver name */
	107	.modalias = "m25p80", /* Name of spi_driver for this device */
	108	.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	109	.bus_num = 0, /* Framework bus number */
1394f032 BW	110	.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
	111	.platform_data = &bfin_spi_flash_data,
	112	.controller_data = &spi_flash_chip_info,
	113	.mode = SPI_MODE_3,
a15c2dcf MH	114	},
	115	#endif
	116
	117	#if defined(CONFIG_SPI_ADC_BF533) \|\| defined(CONFIG_SPI_ADC_BF533_MODULE)
	118	{
1394f032 BW	119	.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
1394f032 BW	120	.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	121	.bus_num = 0, /* Framework bus number */
1394f032 BW	122	.chip_select = 2, /* Framework chip select. */
	123	.platform_data = NULL, /* No spi_driver specific config */
	124	.controller_data = &spi_adc_chip_info,
	125	},
a15c2dcf MH	126	#endif
a15c2dcf MH	127
1394f032 BW	128	#if defined(CONFIG_SND_BLACKFIN_AD1836) \|\| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
	129	{
	130	.modalias = "ad1836-spi",
	131	.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	132	.bus_num = 0,
1394f032 BW	133	.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
	134	.controller_data = &ad1836_spi_chip_info,
	135	},
	136	#endif
a15c2dcf MH	137
	138	#if defined(CONFIG_SPI_MMC) \|\| defined(CONFIG_SPI_MMC_MODULE)
	139	{
	140	.modalias = "spi_mmc_dummy",
	141	.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
	142	.bus_num = 0,
	143	.chip_select = 0,
	144	.platform_data = NULL,
	145	.controller_data = &spi_mmc_chip_info,
	146	.mode = SPI_MODE_3,
	147	},
	148	{
	149	.modalias = "spi_mmc",
	150	.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
	151	.bus_num = 0,
	152	.chip_select = CONFIG_SPI_MMC_CS_CHAN,
	153	.platform_data = NULL,
	154	.controller_data = &spi_mmc_chip_info,
	155	.mode = SPI_MODE_3,
	156	},
	157	#endif
1394f032 BW	158	};
1394f032 BW	159
c6c4d7bb BW	160	/* SPI (0) */
	161	static struct resource bfin_spi0_resource[] = {
	162	[0] = {
	163	.start = SPI0_REGBASE,
	164	.end = SPI0_REGBASE + 0xFF,
	165	.flags = IORESOURCE_MEM,
	166	},
	167	[1] = {
	168	.start = CH_SPI,
	169	.end = CH_SPI,
	170	.flags = IORESOURCE_IRQ,
	171	}
	172	};
	173
1394f032	174	/* SPI controller data */
c6c4d7bb	175	static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032 BW	176	.num_chipselect = 8,
	177	.enable_dma = 1, /* master has the ability to do dma transfer */
	178	};
	179
c6c4d7bb BW	180	static struct platform_device bfin_spi0_device = {
	181	.name = "bfin-spi",
	182	.id = 0, /* Bus number */
	183	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
	184	.resource = bfin_spi0_resource,
1394f032	185	.dev = {
c6c4d7bb	186	.platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032 BW	187	},
	188	};
	189	#endif /* spi master and devices */
	190
	191	#if defined(CONFIG_RTC_DRV_BFIN) \|\| defined(CONFIG_RTC_DRV_BFIN_MODULE)
	192	static struct platform_device rtc_device = {
	193	.name = "rtc-bfin",
	194	.id = -1,
	195	};
	196	#endif
	197
	198	#if defined(CONFIG_SMC91X) \|\| defined(CONFIG_SMC91X_MODULE)
	199	static struct resource smc91x_resources[] = {
	200	{
	201	.start = 0x20200300,
	202	.end = 0x20200300 + 16,
	203	.flags = IORESOURCE_MEM,
1f83b8f1	204	}, {
1394f032 BW	205	.start = IRQ_PF0,
	206	.end = IRQ_PF0,
	207	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
	208	},
	209	};
	210	static struct platform_device smc91x_device = {
	211	.name = "smc91x",
	212	.id = 0,
	213	.num_resources = ARRAY_SIZE(smc91x_resources),
	214	.resource = smc91x_resources,
	215	};
	216	#endif
	217
	218	#if defined(CONFIG_SERIAL_BFIN) \|\| defined(CONFIG_SERIAL_BFIN_MODULE)
	219	static struct resource bfin_uart_resources[] = {
	220	{
	221	.start = 0xFFC00400,
	222	.end = 0xFFC004FF,
	223	.flags = IORESOURCE_MEM,
	224	},
	225	};
	226
	227	static struct platform_device bfin_uart_device = {
	228	.name = "bfin-uart",
	229	.id = 1,
	230	.num_resources = ARRAY_SIZE(bfin_uart_resources),
	231	.resource = bfin_uart_resources,
	232	};
	233	#endif
	234
	235	#if defined(CONFIG_SERIAL_BFIN_SPORT) \|\| defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
	236	static struct platform_device bfin_sport0_uart_device = {
	237	.name = "bfin-sport-uart",
	238	.id = 0,
	239	};
	240
	241	static struct platform_device bfin_sport1_uart_device = {
	242	.name = "bfin-sport-uart",
	243	.id = 1,
	244	};
	245	#endif
	246
	247	#if defined(CONFIG_USB_ISP1362_HCD) \|\| defined(CONFIG_USB_ISP1362_HCD_MODULE)
	248	static struct resource isp1362_hcd_resources[] = {
	249	{
	250	.start = 0x20308000,
	251	.end = 0x20308000,
	252	.flags = IORESOURCE_MEM,
1f83b8f1	253	}, {
1394f032 BW	254	.start = 0x20308004,
	255	.end = 0x20308004,
	256	.flags = IORESOURCE_MEM,
1f83b8f1	257	}, {
1394f032 BW	258	.start = IRQ_PF4,
	259	.end = IRQ_PF4,
	260	.flags = IORESOURCE_IRQ,
	261	},
	262	};
	263
	264	static struct isp1362_platform_data isp1362_priv = {
	265	.sel15Kres = 1,
	266	.clknotstop = 0,
	267	.oc_enable = 0,
	268	.int_act_high = 0,
	269	.int_edge_triggered = 0,
	270	.remote_wakeup_connected = 0,
	271	.no_power_switching = 1,
	272	.power_switching_mode = 0,
	273	};
	274
	275	static struct platform_device isp1362_hcd_device = {
	276	.name = "isp1362-hcd",
	277	.id = 0,
	278	.dev = {
	279	.platform_data = &isp1362_priv,
	280	},
	281	.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
	282	.resource = isp1362_hcd_resources,
	283	};
	284	#endif
	285
c6c4d7bb BW	286	#if defined(CONFIG_PATA_PLATFORM) \|\| defined(CONFIG_PATA_PLATFORM_MODULE)
	287	#define PATA_INT 38
	288
	289	static struct pata_platform_info bfin_pata_platform_data = {
	290	.ioport_shift = 2,
	291	.irq_type = IRQF_TRIGGER_HIGH \| IRQF_DISABLED,
	292	};
	293
	294	static struct resource bfin_pata_resources[] = {
	295	{
	296	.start = 0x2030C000,
	297	.end = 0x2030C01F,
	298	.flags = IORESOURCE_MEM,
	299	},
	300	{
	301	.start = 0x2030D018,
	302	.end = 0x2030D01B,
	303	.flags = IORESOURCE_MEM,
	304	},
	305	{
	306	.start = PATA_INT,
	307	.end = PATA_INT,
	308	.flags = IORESOURCE_IRQ,
	309	},
	310	};
	311
	312	static struct platform_device bfin_pata_device = {
	313	.name = "pata_platform",
	314	.id = -1,
	315	.num_resources = ARRAY_SIZE(bfin_pata_resources),
	316	.resource = bfin_pata_resources,
	317	.dev = {
	318	.platform_data = &bfin_pata_platform_data,
	319	}
	320	};
	321	#endif
	322
1394f032 BW	323	static struct platform_device *cm_bf533_devices[] __initdata = {
	324	#if defined(CONFIG_SERIAL_BFIN) \|\| defined(CONFIG_SERIAL_BFIN_MODULE)
	325	&bfin_uart_device,
	326	#endif
	327
	328	#if defined(CONFIG_SERIAL_BFIN_SPORT) \|\| defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
	329	&bfin_sport0_uart_device,
	330	&bfin_sport1_uart_device,
	331	#endif
	332
	333	#if defined(CONFIG_RTC_DRV_BFIN) \|\| defined(CONFIG_RTC_DRV_BFIN_MODULE)
	334	&rtc_device,
	335	#endif
	336
	337	#if defined(CONFIG_USB_ISP1362_HCD) \|\| defined(CONFIG_USB_ISP1362_HCD_MODULE)
	338	&isp1362_hcd_device,
	339	#endif
	340
	341	#if defined(CONFIG_SMC91X) \|\| defined(CONFIG_SMC91X_MODULE)
	342	&smc91x_device,
	343	#endif
	344
	345	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb BW	346	&bfin_spi0_device,
	347	#endif
	348
	349	#if defined(CONFIG_PATA_PLATFORM) \|\| defined(CONFIG_PATA_PLATFORM_MODULE)
	350	&bfin_pata_device,
1394f032 BW	351	#endif
	352	};
	353
	354	static int __init cm_bf533_init(void)
	355	{
	356	printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
	357	platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
	358	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
	359	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
	360	#endif
c6c4d7bb BW	361
	362	#if defined(CONFIG_PATA_PLATFORM) \|\| defined(CONFIG_PATA_PLATFORM_MODULE)
	363	irq_desc[PATA_INT].status \|= IRQ_NOAUTOEN;
	364	#endif
1394f032 BW	365	return 0;
	366	}
	367
	368	arch_initcall(cm_bf533_init);