[deliverable/linux.git] / arch / blackfin / mach-bf533 / boards / cm_bf533.c

/*
 * File:         arch/blackfin/mach-bf533/boards/cm_bf533.c
 * Based on:     arch/blackfin/mach-bf533/boards/ezkit.c
 * Author:       Aidan Williams <aidan@nicta.com.au> Copyright 2005
 *
 * Created:      2005
 * Description:  Board description file
 *
 * Modified:
 *               Copyright 2004-2006 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb/isp1362.h>
#endif
#include <linux/ata_platform.h>
#include <linux/irq.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>

/*
 * Name the Board for the /proc/cpuinfo
 */
const char bfin_board_name[] = "Bluetechnix CM BF533";

#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* all SPI peripherals info goes here */
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
static struct mtd_partition bfin_spi_flash_partitions[] = {
	{
		.name = "bootloader",
		.size = 0x00020000,
		.offset = 0,
		.mask_flags = MTD_CAP_ROM
	}, {
		.name = "kernel",
		.size = 0xe0000,
		.offset = 0x20000
	}, {
		.name = "file system",
		.size = 0x700000,
		.offset = 0x00100000,
	}
};

static struct flash_platform_data bfin_spi_flash_data = {
	.name = "m25p80",
	.parts = bfin_spi_flash_partitions,
	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
	.type = "m25p64",
};

/* SPI flash chip (m25p64) */
static struct bfin5xx_spi_chip spi_flash_chip_info = {
	.enable_dma = 0,         /* use dma transfer with this chip*/
	.bits_per_word = 8,
};
#endif

/* SPI ADC chip */
#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
static struct bfin5xx_spi_chip spi_adc_chip_info = {
	.enable_dma = 1,         /* use dma transfer with this chip*/
	.bits_per_word = 16,
};
#endif

#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
	.enable_dma = 0,
	.bits_per_word = 16,
};
#endif

#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
	.enable_dma = 1,
	.bits_per_word = 8,
};
#endif

static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
	{
		/* the modalias must be the same as spi device driver name */
		.modalias = "m25p80",       /* Name of spi_driver for this device */
		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,               /* Framework bus number */
		.chip_select = 1,           /* Framework chip select. On STAMP537 it is SPISSEL1*/
		.platform_data = &bfin_spi_flash_data,
		.controller_data = &spi_flash_chip_info,
		.mode = SPI_MODE_3,
	},
#endif

#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
	{
		.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
		.max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,               /* Framework bus number */
		.chip_select = 2,           /* Framework chip select. */
		.platform_data = NULL,      /* No spi_driver specific config */
		.controller_data = &spi_adc_chip_info,
	},
#endif

#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
	{
		.modalias = "ad1836-spi",
		.max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
		.controller_data = &ad1836_spi_chip_info,
	},
#endif

#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
	{
		.modalias = "spi_mmc_dummy",
		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = 0,
		.platform_data = NULL,
		.controller_data = &spi_mmc_chip_info,
		.mode = SPI_MODE_3,
	},
	{
		.modalias = "spi_mmc",
		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = CONFIG_SPI_MMC_CS_CHAN,
		.platform_data = NULL,
		.controller_data = &spi_mmc_chip_info,
		.mode = SPI_MODE_3,
	},
#endif
};

/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
	[0] = {
		.start = SPI0_REGBASE,
		.end   = SPI0_REGBASE + 0xFF,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = CH_SPI,
		.end   = CH_SPI,
		.flags = IORESOURCE_IRQ,
	}
};

/* SPI controller data */
static struct bfin5xx_spi_master bfin_spi0_info = {
	.num_chipselect = 8,
	.enable_dma = 1,  /* master has the ability to do dma transfer */
	.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};

static struct platform_device bfin_spi0_device = {
	.name = "bfin-spi",
	.id = 0, /* Bus number */
	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
	.resource = bfin_spi0_resource,
	.dev = {
		.platform_data = &bfin_spi0_info, /* Passed to driver */
	},
};
#endif  /* spi master and devices */

#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
static struct platform_device rtc_device = {
	.name = "rtc-bfin",
	.id   = -1,
};
#endif

#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
static struct resource smc91x_resources[] = {
	{
		.start = 0x20200300,
		.end = 0x20200300 + 16,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IRQ_PF0,
		.end = IRQ_PF0,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};
static struct platform_device smc91x_device = {
	.name = "smc91x",
	.id = 0,
	.num_resources = ARRAY_SIZE(smc91x_resources),
	.resource = smc91x_resources,
};
#endif

#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
static struct resource bfin_uart_resources[] = {
	{
		.start = 0xFFC00400,
		.end = 0xFFC004FF,
		.flags = IORESOURCE_MEM,
	},
};

static struct platform_device bfin_uart_device = {
	.name = "bfin-uart",
	.id = 1,
	.num_resources = ARRAY_SIZE(bfin_uart_resources),
	.resource = bfin_uart_resources,
};
#endif

#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
static struct resource bfin_sir_resources[] = {
#ifdef CONFIG_BFIN_SIR0
	{
		.start = 0xFFC00400,
		.end = 0xFFC004FF,
		.flags = IORESOURCE_MEM,
	},
#endif
};

static struct platform_device bfin_sir_device = {
	.name = "bfin_sir",
	.id = 0,
	.num_resources = ARRAY_SIZE(bfin_sir_resources),
	.resource = bfin_sir_resources,
};
#endif

#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
static struct platform_device bfin_sport0_uart_device = {
	.name = "bfin-sport-uart",
	.id = 0,
};

static struct platform_device bfin_sport1_uart_device = {
	.name = "bfin-sport-uart",
	.id = 1,
};
#endif

#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
static struct resource isp1362_hcd_resources[] = {
	{
		.start = 0x20308000,
		.end = 0x20308000,
		.flags = IORESOURCE_MEM,
	}, {
		.start = 0x20308004,
		.end = 0x20308004,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IRQ_PF4,
		.end = IRQ_PF4,
		.flags = IORESOURCE_IRQ,
	},
};

static struct isp1362_platform_data isp1362_priv = {
	.sel15Kres = 1,
	.clknotstop = 0,
	.oc_enable = 0,
	.int_act_high = 0,
	.int_edge_triggered = 0,
	.remote_wakeup_connected = 0,
	.no_power_switching = 1,
	.power_switching_mode = 0,
};

static struct platform_device isp1362_hcd_device = {
	.name = "isp1362-hcd",
	.id = 0,
	.dev = {
		.platform_data = &isp1362_priv,
	},
	.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
	.resource = isp1362_hcd_resources,
};
#endif

#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
#define PATA_INT	38

static struct pata_platform_info bfin_pata_platform_data = {
	.ioport_shift = 2,
	.irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
};

static struct resource bfin_pata_resources[] = {
	{
		.start = 0x2030C000,
		.end = 0x2030C01F,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = 0x2030D018,
		.end = 0x2030D01B,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = PATA_INT,
		.end = PATA_INT,
		.flags = IORESOURCE_IRQ,
	},
};

static struct platform_device bfin_pata_device = {
	.name = "pata_platform",
	.id = -1,
	.num_resources = ARRAY_SIZE(bfin_pata_resources),
	.resource = bfin_pata_resources,
	.dev = {
		.platform_data = &bfin_pata_platform_data,
	}
};
#endif

static const unsigned int cclk_vlev_datasheet[] =
{
	VRPAIR(VLEV_085, 250000000),
	VRPAIR(VLEV_090, 376000000),
	VRPAIR(VLEV_095, 426000000),
	VRPAIR(VLEV_100, 426000000),
	VRPAIR(VLEV_105, 476000000),
	VRPAIR(VLEV_110, 476000000),
	VRPAIR(VLEV_115, 476000000),
	VRPAIR(VLEV_120, 600000000),
	VRPAIR(VLEV_125, 600000000),
	VRPAIR(VLEV_130, 600000000),
};

static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
	.tuple_tab = cclk_vlev_datasheet,
	.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
	.vr_settling_time = 25 /* us */,
};

static struct platform_device bfin_dpmc = {
	.name = "bfin dpmc",
	.dev = {
		.platform_data = &bfin_dmpc_vreg_data,
	},
};

static struct platform_device *cm_bf533_devices[] __initdata = {

	&bfin_dpmc,

#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
	&bfin_uart_device,
#endif

#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
	&bfin_sir_device,
#endif

#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
	&bfin_sport0_uart_device,
	&bfin_sport1_uart_device,
#endif

#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
	&rtc_device,
#endif

#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
	&isp1362_hcd_device,
#endif

#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
	&smc91x_device,
#endif

#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
	&bfin_spi0_device,
#endif

#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
	&bfin_pata_device,
#endif
};

static int __init cm_bf533_init(void)
{
	printk(KERN_INFO "%s(): registering device resources\n", __func__);
	platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
#endif

#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
	irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
#endif
	return 0;
}

arch_initcall(cm_bf533_init);
Commit	Line	Data
1394f032 BW	1	/*
	2	* File: arch/blackfin/mach-bf533/boards/cm_bf533.c
	3	* Based on: arch/blackfin/mach-bf533/boards/ezkit.c
d2d50aa9	4	* Author: Aidan Williams <aidan@nicta.com.au> Copyright 2005
1394f032 BW	5	*
	6	* Created: 2005
	7	* Description: Board description file
	8	*
	9	* Modified:
	10	* Copyright 2004-2006 Analog Devices Inc.
	11	*
	12	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, see the file COPYING, or write
	26	* to the Free Software Foundation, Inc.,
	27	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	28	*/
	29
	30	#include <linux/device.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/mtd/mtd.h>
	33	#include <linux/mtd/partitions.h>
	34	#include <linux/spi/spi.h>
	35	#include <linux/spi/flash.h>
b964c592	36	#if defined(CONFIG_USB_ISP1362_HCD) \|\| defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5	37	#include <linux/usb/isp1362.h>
b964c592	38	#endif
0a87e3e9	39	#include <linux/ata_platform.h>
1f83b8f1	40	#include <linux/irq.h>
c6c4d7bb	41	#include <asm/dma.h>
1394f032	42	#include <asm/bfin5xx_spi.h>
5d448dd5	43	#include <asm/portmux.h>
14b03204	44	#include <asm/dpmc.h>
1394f032 BW	45
	46	/*
	47	* Name the Board for the /proc/cpuinfo
	48	*/
066954a3	49	const char bfin_board_name[] = "Bluetechnix CM BF533";
1394f032 BW	50
	51	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
	52	/* all SPI peripherals info goes here */
a15c2dcf	53	#if defined(CONFIG_MTD_M25P80) \|\| defined(CONFIG_MTD_M25P80_MODULE)
1394f032 BW	54	static struct mtd_partition bfin_spi_flash_partitions[] = {
	55	{
	56	.name = "bootloader",
	57	.size = 0x00020000,
	58	.offset = 0,
	59	.mask_flags = MTD_CAP_ROM
1f83b8f1	60	}, {
1394f032 BW	61	.name = "kernel",
	62	.size = 0xe0000,
	63	.offset = 0x20000
1f83b8f1	64	}, {
1394f032 BW	65	.name = "file system",
	66	.size = 0x700000,
	67	.offset = 0x00100000,
	68	}
	69	};
	70
	71	static struct flash_platform_data bfin_spi_flash_data = {
	72	.name = "m25p80",
	73	.parts = bfin_spi_flash_partitions,
	74	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
	75	.type = "m25p64",
	76	};
	77
	78	/* SPI flash chip (m25p64) */
	79	static struct bfin5xx_spi_chip spi_flash_chip_info = {
	80	.enable_dma = 0, /* use dma transfer with this chip*/
	81	.bits_per_word = 8,
	82	};
a15c2dcf	83	#endif
1394f032 BW	84
1394f032 BW	85	/* SPI ADC chip */
a15c2dcf	86	#if defined(CONFIG_SPI_ADC_BF533) \|\| defined(CONFIG_SPI_ADC_BF533_MODULE)
1394f032 BW	87	static struct bfin5xx_spi_chip spi_adc_chip_info = {
	88	.enable_dma = 1, /* use dma transfer with this chip*/
	89	.bits_per_word = 16,
	90	};
a15c2dcf	91	#endif
1394f032 BW	92
	93	#if defined(CONFIG_SND_BLACKFIN_AD1836) \|\| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
	94	static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
	95	.enable_dma = 0,
	96	.bits_per_word = 16,
	97	};
	98	#endif
	99
a15c2dcf MH	100	#if defined(CONFIG_SPI_MMC) \|\| defined(CONFIG_SPI_MMC_MODULE)
	101	static struct bfin5xx_spi_chip spi_mmc_chip_info = {
	102	.enable_dma = 1,
	103	.bits_per_word = 8,
	104	};
	105	#endif
	106
1394f032	107	static struct spi_board_info bfin_spi_board_info[] __initdata = {
a15c2dcf	108	#if defined(CONFIG_MTD_M25P80) \|\| defined(CONFIG_MTD_M25P80_MODULE)
1394f032 BW	109	{
	110	/* the modalias must be the same as spi device driver name */
	111	.modalias = "m25p80", /* Name of spi_driver for this device */
	112	.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	113	.bus_num = 0, /* Framework bus number */
1394f032 BW	114	.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
	115	.platform_data = &bfin_spi_flash_data,
	116	.controller_data = &spi_flash_chip_info,
	117	.mode = SPI_MODE_3,
a15c2dcf MH	118	},
	119	#endif
	120
	121	#if defined(CONFIG_SPI_ADC_BF533) \|\| defined(CONFIG_SPI_ADC_BF533_MODULE)
	122	{
1394f032 BW	123	.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
1394f032 BW	124	.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	125	.bus_num = 0, /* Framework bus number */
1394f032 BW	126	.chip_select = 2, /* Framework chip select. */
	127	.platform_data = NULL, /* No spi_driver specific config */
	128	.controller_data = &spi_adc_chip_info,
	129	},
a15c2dcf MH	130	#endif
a15c2dcf MH	131
1394f032 BW	132	#if defined(CONFIG_SND_BLACKFIN_AD1836) \|\| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
	133	{
	134	.modalias = "ad1836-spi",
	135	.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	136	.bus_num = 0,
1394f032 BW	137	.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
	138	.controller_data = &ad1836_spi_chip_info,
	139	},
	140	#endif
a15c2dcf MH	141
	142	#if defined(CONFIG_SPI_MMC) \|\| defined(CONFIG_SPI_MMC_MODULE)
	143	{
	144	.modalias = "spi_mmc_dummy",
	145	.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
	146	.bus_num = 0,
	147	.chip_select = 0,
	148	.platform_data = NULL,
	149	.controller_data = &spi_mmc_chip_info,
	150	.mode = SPI_MODE_3,
	151	},
	152	{
	153	.modalias = "spi_mmc",
	154	.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
	155	.bus_num = 0,
	156	.chip_select = CONFIG_SPI_MMC_CS_CHAN,
	157	.platform_data = NULL,
	158	.controller_data = &spi_mmc_chip_info,
	159	.mode = SPI_MODE_3,
	160	},
	161	#endif
1394f032 BW	162	};
1394f032 BW	163
c6c4d7bb BW	164	/* SPI (0) */
	165	static struct resource bfin_spi0_resource[] = {
	166	[0] = {
	167	.start = SPI0_REGBASE,
	168	.end = SPI0_REGBASE + 0xFF,
	169	.flags = IORESOURCE_MEM,
	170	},
	171	[1] = {
	172	.start = CH_SPI,
	173	.end = CH_SPI,
	174	.flags = IORESOURCE_IRQ,
	175	}
	176	};
	177
1394f032	178	/* SPI controller data */
c6c4d7bb	179	static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032 BW	180	.num_chipselect = 8,
1394f032 BW	181	.enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5	182	.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032 BW	183	};
1394f032 BW	184
c6c4d7bb BW	185	static struct platform_device bfin_spi0_device = {
	186	.name = "bfin-spi",
	187	.id = 0, /* Bus number */
	188	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
	189	.resource = bfin_spi0_resource,
1394f032	190	.dev = {
c6c4d7bb	191	.platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032 BW	192	},
	193	};
	194	#endif /* spi master and devices */
	195
	196	#if defined(CONFIG_RTC_DRV_BFIN) \|\| defined(CONFIG_RTC_DRV_BFIN_MODULE)
	197	static struct platform_device rtc_device = {
	198	.name = "rtc-bfin",
	199	.id = -1,
	200	};
	201	#endif
	202
	203	#if defined(CONFIG_SMC91X) \|\| defined(CONFIG_SMC91X_MODULE)
	204	static struct resource smc91x_resources[] = {
	205	{
	206	.start = 0x20200300,
	207	.end = 0x20200300 + 16,
	208	.flags = IORESOURCE_MEM,
1f83b8f1	209	}, {
1394f032 BW	210	.start = IRQ_PF0,
	211	.end = IRQ_PF0,
	212	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
	213	},
	214	};
	215	static struct platform_device smc91x_device = {
	216	.name = "smc91x",
	217	.id = 0,
	218	.num_resources = ARRAY_SIZE(smc91x_resources),
	219	.resource = smc91x_resources,
	220	};
	221	#endif
	222
	223	#if defined(CONFIG_SERIAL_BFIN) \|\| defined(CONFIG_SERIAL_BFIN_MODULE)
	224	static struct resource bfin_uart_resources[] = {
	225	{
	226	.start = 0xFFC00400,
	227	.end = 0xFFC004FF,
	228	.flags = IORESOURCE_MEM,
	229	},
	230	};
	231
	232	static struct platform_device bfin_uart_device = {
	233	.name = "bfin-uart",
	234	.id = 1,
	235	.num_resources = ARRAY_SIZE(bfin_uart_resources),
	236	.resource = bfin_uart_resources,
	237	};
	238	#endif
	239
5be36d22 GY	240	#if defined(CONFIG_BFIN_SIR) \|\| defined(CONFIG_BFIN_SIR_MODULE)
	241	static struct resource bfin_sir_resources[] = {
	242	#ifdef CONFIG_BFIN_SIR0
	243	{
	244	.start = 0xFFC00400,
	245	.end = 0xFFC004FF,
	246	.flags = IORESOURCE_MEM,
	247	},
	248	#endif
	249	};
	250
	251	static struct platform_device bfin_sir_device = {
	252	.name = "bfin_sir",
	253	.id = 0,
	254	.num_resources = ARRAY_SIZE(bfin_sir_resources),
	255	.resource = bfin_sir_resources,
	256	};
	257	#endif
	258
1394f032 BW	259	#if defined(CONFIG_SERIAL_BFIN_SPORT) \|\| defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
	260	static struct platform_device bfin_sport0_uart_device = {
	261	.name = "bfin-sport-uart",
	262	.id = 0,
	263	};
	264
	265	static struct platform_device bfin_sport1_uart_device = {
	266	.name = "bfin-sport-uart",
	267	.id = 1,
	268	};
	269	#endif
	270
	271	#if defined(CONFIG_USB_ISP1362_HCD) \|\| defined(CONFIG_USB_ISP1362_HCD_MODULE)
	272	static struct resource isp1362_hcd_resources[] = {
	273	{
	274	.start = 0x20308000,
	275	.end = 0x20308000,
	276	.flags = IORESOURCE_MEM,
1f83b8f1	277	}, {
1394f032 BW	278	.start = 0x20308004,
	279	.end = 0x20308004,
	280	.flags = IORESOURCE_MEM,
1f83b8f1	281	}, {
1394f032 BW	282	.start = IRQ_PF4,
	283	.end = IRQ_PF4,
	284	.flags = IORESOURCE_IRQ,
	285	},
	286	};
	287
	288	static struct isp1362_platform_data isp1362_priv = {
	289	.sel15Kres = 1,
	290	.clknotstop = 0,
	291	.oc_enable = 0,
	292	.int_act_high = 0,
	293	.int_edge_triggered = 0,
	294	.remote_wakeup_connected = 0,
	295	.no_power_switching = 1,
	296	.power_switching_mode = 0,
	297	};
	298
	299	static struct platform_device isp1362_hcd_device = {
	300	.name = "isp1362-hcd",
	301	.id = 0,
	302	.dev = {
	303	.platform_data = &isp1362_priv,
	304	},
	305	.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
	306	.resource = isp1362_hcd_resources,
	307	};
	308	#endif
	309
c6c4d7bb BW	310	#if defined(CONFIG_PATA_PLATFORM) \|\| defined(CONFIG_PATA_PLATFORM_MODULE)
	311	#define PATA_INT 38
	312
	313	static struct pata_platform_info bfin_pata_platform_data = {
	314	.ioport_shift = 2,
	315	.irq_type = IRQF_TRIGGER_HIGH \| IRQF_DISABLED,
	316	};
	317
	318	static struct resource bfin_pata_resources[] = {
	319	{
	320	.start = 0x2030C000,
	321	.end = 0x2030C01F,
	322	.flags = IORESOURCE_MEM,
	323	},
	324	{
	325	.start = 0x2030D018,
	326	.end = 0x2030D01B,
	327	.flags = IORESOURCE_MEM,
	328	},
	329	{
	330	.start = PATA_INT,
	331	.end = PATA_INT,
	332	.flags = IORESOURCE_IRQ,
	333	},
	334	};
	335
	336	static struct platform_device bfin_pata_device = {
	337	.name = "pata_platform",
	338	.id = -1,
	339	.num_resources = ARRAY_SIZE(bfin_pata_resources),
	340	.resource = bfin_pata_resources,
	341	.dev = {
	342	.platform_data = &bfin_pata_platform_data,
	343	}
	344	};
	345	#endif
	346
14b03204 MH	347	static const unsigned int cclk_vlev_datasheet[] =
	348	{
	349	VRPAIR(VLEV_085, 250000000),
	350	VRPAIR(VLEV_090, 376000000),
	351	VRPAIR(VLEV_095, 426000000),
	352	VRPAIR(VLEV_100, 426000000),
	353	VRPAIR(VLEV_105, 476000000),
	354	VRPAIR(VLEV_110, 476000000),
	355	VRPAIR(VLEV_115, 476000000),
	356	VRPAIR(VLEV_120, 600000000),
	357	VRPAIR(VLEV_125, 600000000),
	358	VRPAIR(VLEV_130, 600000000),
	359	};
	360
	361	static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
	362	.tuple_tab = cclk_vlev_datasheet,
	363	.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
	364	.vr_settling_time = 25 /* us */,
	365	};
	366
	367	static struct platform_device bfin_dpmc = {
	368	.name = "bfin dpmc",
	369	.dev = {
	370	.platform_data = &bfin_dmpc_vreg_data,
	371	},
	372	};
	373
1394f032	374	static struct platform_device *cm_bf533_devices[] __initdata = {
14b03204 MH	375
	376	&bfin_dpmc,
	377
1394f032 BW	378	#if defined(CONFIG_SERIAL_BFIN) \|\| defined(CONFIG_SERIAL_BFIN_MODULE)
	379	&bfin_uart_device,
	380	#endif
	381
5be36d22 GY	382	#if defined(CONFIG_BFIN_SIR) \|\| defined(CONFIG_BFIN_SIR_MODULE)
	383	&bfin_sir_device,
	384	#endif
	385
1394f032 BW	386	#if defined(CONFIG_SERIAL_BFIN_SPORT) \|\| defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
	387	&bfin_sport0_uart_device,
	388	&bfin_sport1_uart_device,
	389	#endif
	390
	391	#if defined(CONFIG_RTC_DRV_BFIN) \|\| defined(CONFIG_RTC_DRV_BFIN_MODULE)
	392	&rtc_device,
	393	#endif
	394
	395	#if defined(CONFIG_USB_ISP1362_HCD) \|\| defined(CONFIG_USB_ISP1362_HCD_MODULE)
	396	&isp1362_hcd_device,
	397	#endif
	398
	399	#if defined(CONFIG_SMC91X) \|\| defined(CONFIG_SMC91X_MODULE)
	400	&smc91x_device,
	401	#endif
	402
	403	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb BW	404	&bfin_spi0_device,
	405	#endif
	406
	407	#if defined(CONFIG_PATA_PLATFORM) \|\| defined(CONFIG_PATA_PLATFORM_MODULE)
	408	&bfin_pata_device,
1394f032 BW	409	#endif
	410	};
	411
	412	static int __init cm_bf533_init(void)
	413	{
b85d858b	414	printk(KERN_INFO "%s(): registering device resources\n", __func__);
1394f032 BW	415	platform_add_devices(cm_bf533_devices, ARRAY_SIZE(cm_bf533_devices));
	416	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
	417	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
	418	#endif
c6c4d7bb BW	419
	420	#if defined(CONFIG_PATA_PLATFORM) \|\| defined(CONFIG_PATA_PLATFORM_MODULE)
	421	irq_desc[PATA_INT].status \|= IRQ_NOAUTOEN;
	422	#endif
1394f032 BW	423	return 0;
	424	}
	425
	426	arch_initcall(cm_bf533_init);