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1394f032 | 1 | /* |
96f1050d | 2 | * Copyright 2005-2008 Analog Devices Inc. |
1394f032 | 3 | * |
96f1050d | 4 | * Licensed under the GPL-2 or later |
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5 | */ |
6 | ||
7 | #ifndef _CDEF_BF532_H | |
8 | #define _CDEF_BF532_H | |
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9 | |
10 | #include <asm/blackfin.h> | |
11 | ||
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12 | /*include all Core registers and bit definitions*/ |
13 | #include "defBF532.h" | |
14 | ||
15 | /*include core specific register pointer definitions*/ | |
639f6571 | 16 | #include <asm/cdef_LPBlackfin.h> |
1394f032 | 17 | |
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18 | /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ |
19 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | |
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20 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
21 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) | |
22 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | |
23 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) | |
24 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | |
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25 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
26 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) | |
27 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | |
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28 | |
29 | /* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ | |
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30 | #define bfin_read_SWRST() bfin_read16(SWRST) |
31 | #define bfin_write_SWRST(val) bfin_write16(SWRST,val) | |
32 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | |
33 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR,val) | |
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34 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) |
35 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) | |
36 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) | |
37 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1,val) | |
38 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) | |
39 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2,val) | |
40 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) | |
41 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3,val) | |
42 | #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) | |
43 | #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK,val) | |
44 | #define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) | |
45 | #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR,val) | |
46 | #define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) | |
47 | #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR,val) | |
48 | ||
49 | /* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ | |
50 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) | |
51 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL,val) | |
52 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) | |
53 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT,val) | |
54 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) | |
55 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT,val) | |
56 | ||
57 | /* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ | |
58 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) | |
59 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT,val) | |
60 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) | |
61 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL,val) | |
62 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) | |
63 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT,val) | |
64 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) | |
65 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT,val) | |
66 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) | |
67 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM,val) | |
68 | #define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) | |
69 | #define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST,val) | |
70 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) | |
71 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) | |
72 | ||
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73 | /* DMA Traffic controls */ |
74 | #define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) | |
75 | #define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) | |
76 | #define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) | |
77 | #define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) | |
78 | ||
79 | /* Alternate deprecated register names (below) provided for backwards code compatibility */ | |
80 | #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) | |
81 | #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) | |
82 | #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) | |
83 | #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) | |
84 | ||
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85 | /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ |
86 | #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) | |
87 | #define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val) | |
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88 | #define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) |
89 | #define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C,val) | |
90 | #define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) | |
91 | #define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S,val) | |
92 | #define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) | |
93 | #define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C,val) | |
94 | #define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) | |
95 | #define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S,val) | |
96 | #define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) | |
97 | #define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR,val) | |
98 | #define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) | |
99 | #define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE,val) | |
100 | #define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) | |
101 | #define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH,val) | |
102 | #define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) | |
103 | #define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN,val) | |
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104 | #define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) |
105 | #define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D,val) | |
106 | #define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) | |
107 | #define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T,val) | |
108 | #define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) | |
109 | #define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D,val) | |
110 | #define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) | |
111 | #define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) | |
112 | ||
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113 | /* DMA Controller */ |
114 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) | |
115 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) | |
116 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) | |
117 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR,val) | |
118 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) | |
119 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR,val) | |
120 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) | |
121 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT,val) | |
122 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) | |
123 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT,val) | |
124 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) | |
125 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY,val) | |
126 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) | |
127 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY,val) | |
128 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) | |
129 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR,val) | |
130 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) | |
131 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR,val) | |
132 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) | |
133 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT,val) | |
134 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) | |
135 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT,val) | |
136 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) | |
137 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS,val) | |
138 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) | |
139 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP,val) | |
140 | ||
141 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) | |
142 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG,val) | |
143 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) | |
144 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR,val) | |
145 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) | |
146 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR,val) | |
147 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) | |
148 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT,val) | |
149 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) | |
150 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT,val) | |
151 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) | |
152 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY,val) | |
153 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) | |
154 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY,val) | |
155 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) | |
156 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR,val) | |
157 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) | |
158 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR,val) | |
159 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) | |
160 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT,val) | |
161 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) | |
162 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT,val) | |
163 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) | |
164 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS,val) | |
165 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) | |
166 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP,val) | |
167 | ||
168 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) | |
169 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG,val) | |
170 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) | |
171 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR,val) | |
172 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) | |
173 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR,val) | |
174 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) | |
175 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT,val) | |
176 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) | |
177 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT,val) | |
178 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) | |
179 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY,val) | |
180 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) | |
181 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY,val) | |
182 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) | |
183 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR,val) | |
184 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) | |
185 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR,val) | |
186 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) | |
187 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT,val) | |
188 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) | |
189 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT,val) | |
190 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) | |
191 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS,val) | |
192 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) | |
193 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP,val) | |
194 | ||
195 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) | |
196 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG,val) | |
197 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) | |
198 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR,val) | |
199 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) | |
200 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR,val) | |
201 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) | |
202 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT,val) | |
203 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) | |
204 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT,val) | |
205 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) | |
206 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY,val) | |
207 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) | |
208 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY,val) | |
209 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) | |
210 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR,val) | |
211 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) | |
212 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR,val) | |
213 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) | |
214 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT,val) | |
215 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) | |
216 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT,val) | |
217 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) | |
218 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val) | |
219 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) | |
220 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP,val) | |
221 | ||
222 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) | |
223 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG,val) | |
224 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) | |
225 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR,val) | |
226 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) | |
227 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val) | |
228 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) | |
229 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT,val) | |
230 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) | |
231 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT,val) | |
232 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) | |
233 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY,val) | |
234 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) | |
235 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY,val) | |
236 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) | |
237 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR,val) | |
238 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) | |
239 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR,val) | |
240 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) | |
241 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT,val) | |
242 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) | |
243 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT,val) | |
244 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) | |
245 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS,val) | |
246 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) | |
247 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP,val) | |
248 | ||
249 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) | |
250 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val) | |
251 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) | |
252 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR,val) | |
253 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) | |
254 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR,val) | |
255 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) | |
256 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT,val) | |
257 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) | |
258 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val) | |
259 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) | |
260 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY,val) | |
261 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) | |
262 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY,val) | |
263 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) | |
264 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR,val) | |
265 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) | |
266 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR,val) | |
267 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) | |
268 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT,val) | |
269 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) | |
270 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT,val) | |
271 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) | |
272 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS,val) | |
273 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) | |
274 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP,val) | |
275 | ||
276 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) | |
277 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG,val) | |
278 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) | |
279 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR,val) | |
280 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) | |
281 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR,val) | |
282 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) | |
283 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT,val) | |
284 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) | |
285 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT,val) | |
286 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) | |
287 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY,val) | |
288 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) | |
289 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY,val) | |
290 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) | |
291 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR,val) | |
292 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) | |
293 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR,val) | |
294 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) | |
295 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT,val) | |
296 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) | |
297 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT,val) | |
298 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) | |
299 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS,val) | |
300 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) | |
301 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP,val) | |
302 | ||
303 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) | |
304 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG,val) | |
305 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) | |
306 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR,val) | |
307 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) | |
308 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR,val) | |
309 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) | |
310 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT,val) | |
311 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) | |
312 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT,val) | |
313 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) | |
314 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY,val) | |
315 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) | |
316 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY,val) | |
317 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) | |
318 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR,val) | |
319 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) | |
320 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR,val) | |
321 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) | |
322 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT,val) | |
323 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) | |
324 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT,val) | |
325 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) | |
326 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS,val) | |
327 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) | |
328 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP,val) | |
329 | ||
330 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) | |
331 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG,val) | |
332 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) | |
333 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val) | |
334 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) | |
335 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR,val) | |
336 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) | |
337 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT,val) | |
338 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) | |
339 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT,val) | |
340 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) | |
341 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY,val) | |
342 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) | |
343 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY,val) | |
344 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) | |
345 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val) | |
346 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) | |
347 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR,val) | |
348 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) | |
349 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val) | |
350 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) | |
351 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val) | |
352 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) | |
353 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS,val) | |
354 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) | |
355 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val) | |
356 | ||
357 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) | |
358 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG,val) | |
359 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) | |
360 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val) | |
361 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) | |
362 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR,val) | |
363 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) | |
364 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT,val) | |
365 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) | |
366 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT,val) | |
367 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) | |
368 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY,val) | |
369 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) | |
370 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY,val) | |
371 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) | |
372 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val) | |
373 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) | |
374 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR,val) | |
375 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) | |
376 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val) | |
377 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) | |
378 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val) | |
379 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) | |
380 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS,val) | |
381 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) | |
382 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val) | |
383 | ||
384 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) | |
385 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG,val) | |
386 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) | |
387 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val) | |
388 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) | |
389 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR,val) | |
390 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) | |
391 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT,val) | |
392 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) | |
393 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT,val) | |
394 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) | |
395 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY,val) | |
396 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) | |
397 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY,val) | |
398 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) | |
399 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val) | |
400 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) | |
401 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR,val) | |
402 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) | |
403 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val) | |
404 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) | |
405 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val) | |
406 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) | |
407 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS,val) | |
408 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) | |
409 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val) | |
410 | ||
411 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) | |
412 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG,val) | |
413 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) | |
414 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val) | |
415 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) | |
416 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR,val) | |
417 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) | |
418 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT,val) | |
419 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) | |
420 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT,val) | |
421 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) | |
422 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY,val) | |
423 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) | |
424 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY,val) | |
425 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) | |
426 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val) | |
427 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) | |
428 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR,val) | |
429 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) | |
430 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val) | |
431 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) | |
432 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val) | |
433 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) | |
434 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS,val) | |
435 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) | |
436 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val) | |
437 | ||
438 | /* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ | |
439 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) | |
440 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val) | |
441 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) | |
442 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val) | |
443 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) | |
444 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val) | |
445 | ||
446 | /* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ | |
447 | #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) | |
448 | #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val) | |
449 | #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) | |
450 | #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val) | |
451 | #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) | |
452 | #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) | |
453 | #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) | |
454 | #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL,val) | |
455 | ||
456 | /* UART Controller */ | |
457 | #define bfin_read_UART_THR() bfin_read16(UART_THR) | |
458 | #define bfin_write_UART_THR(val) bfin_write16(UART_THR,val) | |
459 | #define bfin_read_UART_RBR() bfin_read16(UART_RBR) | |
460 | #define bfin_write_UART_RBR(val) bfin_write16(UART_RBR,val) | |
461 | #define bfin_read_UART_DLL() bfin_read16(UART_DLL) | |
462 | #define bfin_write_UART_DLL(val) bfin_write16(UART_DLL,val) | |
463 | #define bfin_read_UART_IER() bfin_read16(UART_IER) | |
464 | #define bfin_write_UART_IER(val) bfin_write16(UART_IER,val) | |
465 | #define bfin_read_UART_DLH() bfin_read16(UART_DLH) | |
466 | #define bfin_write_UART_DLH(val) bfin_write16(UART_DLH,val) | |
467 | #define bfin_read_UART_IIR() bfin_read16(UART_IIR) | |
468 | #define bfin_write_UART_IIR(val) bfin_write16(UART_IIR,val) | |
469 | #define bfin_read_UART_LCR() bfin_read16(UART_LCR) | |
470 | #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR,val) | |
471 | #define bfin_read_UART_MCR() bfin_read16(UART_MCR) | |
472 | #define bfin_write_UART_MCR(val) bfin_write16(UART_MCR,val) | |
473 | #define bfin_read_UART_LSR() bfin_read16(UART_LSR) | |
474 | #define bfin_write_UART_LSR(val) bfin_write16(UART_LSR,val) | |
475 | /* | |
476 | #define UART_MSR | |
477 | */ | |
478 | #define bfin_read_UART_SCR() bfin_read16(UART_SCR) | |
479 | #define bfin_write_UART_SCR(val) bfin_write16(UART_SCR,val) | |
480 | #define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) | |
481 | #define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL,val) | |
482 | ||
483 | /* SPI Controller */ | |
484 | #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) | |
485 | #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL,val) | |
486 | #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) | |
487 | #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG,val) | |
488 | #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) | |
489 | #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT,val) | |
490 | #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) | |
491 | #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR,val) | |
492 | #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) | |
493 | #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR,val) | |
494 | #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) | |
495 | #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD,val) | |
496 | #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) | |
497 | #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW,val) | |
498 | ||
499 | /* TIMER 0, 1, 2 Registers */ | |
500 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) | |
501 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG,val) | |
502 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) | |
503 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER,val) | |
504 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) | |
505 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD,val) | |
506 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) | |
507 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH,val) | |
508 | ||
509 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) | |
510 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG,val) | |
511 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) | |
512 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER,val) | |
513 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) | |
514 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD,val) | |
515 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) | |
516 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH,val) | |
517 | ||
518 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) | |
519 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG,val) | |
520 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) | |
521 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER,val) | |
522 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) | |
523 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD,val) | |
524 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) | |
525 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH,val) | |
526 | ||
527 | #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) | |
528 | #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val) | |
529 | #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) | |
530 | #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE,val) | |
531 | #define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) | |
532 | #define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS,val) | |
533 | ||
534 | /* SPORT0 Controller */ | |
535 | #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) | |
536 | #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1,val) | |
537 | #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) | |
538 | #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val) | |
539 | #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) | |
540 | #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val) | |
541 | #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) | |
542 | #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV,val) | |
543 | #define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) | |
544 | #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX,val) | |
545 | #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) | |
546 | #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX,val) | |
547 | #define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX) | |
548 | #define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX,val) | |
549 | #define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX) | |
550 | #define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX,val) | |
551 | #define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX) | |
552 | #define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX,val) | |
553 | #define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX) | |
554 | #define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX,val) | |
555 | #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) | |
556 | #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1,val) | |
557 | #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) | |
558 | #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2,val) | |
559 | #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) | |
560 | #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV,val) | |
561 | #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) | |
562 | #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV,val) | |
563 | #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) | |
564 | #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT,val) | |
565 | #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) | |
566 | #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL,val) | |
567 | #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) | |
568 | #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val) | |
569 | #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) | |
570 | #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val) | |
571 | #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) | |
572 | #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val) | |
573 | #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) | |
574 | #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val) | |
575 | #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) | |
576 | #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val) | |
577 | #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) | |
578 | #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val) | |
579 | #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) | |
580 | #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val) | |
581 | #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) | |
582 | #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val) | |
583 | #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) | |
584 | #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val) | |
585 | #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) | |
586 | #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val) | |
587 | ||
588 | /* SPORT1 Controller */ | |
589 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) | |
590 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val) | |
591 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) | |
592 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val) | |
593 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) | |
594 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val) | |
595 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) | |
596 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val) | |
597 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) | |
598 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val) | |
599 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) | |
600 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val) | |
601 | #define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX) | |
602 | #define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val) | |
603 | #define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX) | |
604 | #define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val) | |
605 | #define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX) | |
606 | #define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val) | |
607 | #define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX) | |
608 | #define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val) | |
609 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) | |
610 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val) | |
611 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) | |
612 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val) | |
613 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) | |
614 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val) | |
615 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) | |
616 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val) | |
617 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) | |
618 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val) | |
619 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) | |
620 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val) | |
621 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) | |
622 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val) | |
623 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) | |
624 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val) | |
625 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) | |
626 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val) | |
627 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) | |
628 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val) | |
629 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) | |
630 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val) | |
631 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) | |
632 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val) | |
633 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) | |
634 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val) | |
635 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) | |
636 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val) | |
637 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) | |
638 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val) | |
639 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) | |
640 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val) | |
641 | ||
642 | /* Parallel Peripheral Interface (PPI) */ | |
643 | #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) | |
644 | #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL,val) | |
645 | #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) | |
646 | #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS,val) | |
647 | #define bfin_clear_PPI_STATUS() bfin_read_PPI_STATUS() | |
648 | #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) | |
649 | #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY,val) | |
650 | #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) | |
651 | #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT,val) | |
652 | #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) | |
653 | #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME,val) | |
654 | ||
53442e1c | 655 | /* These need to be last due to the cdef/linux inter-dependencies */ |
b6070576 | 656 | #include <asm/irq.h> |
53442e1c | 657 | |
b1271d31 MF |
658 | #if ANOMALY_05000311 |
659 | #define BFIN_WRITE_FIO_FLAG(name) \ | |
660 | static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \ | |
661 | { \ | |
662 | unsigned long flags; \ | |
6a01f230 | 663 | local_irq_save_hw(flags); \ |
b1271d31 MF |
664 | bfin_write16(FIO_FLAG_##name, val); \ |
665 | bfin_read_CHIPID(); \ | |
6a01f230 | 666 | local_irq_restore_hw(flags); \ |
b1271d31 MF |
667 | } |
668 | BFIN_WRITE_FIO_FLAG(D) | |
669 | BFIN_WRITE_FIO_FLAG(C) | |
670 | BFIN_WRITE_FIO_FLAG(S) | |
671 | BFIN_WRITE_FIO_FLAG(T) | |
672 | ||
673 | #define BFIN_READ_FIO_FLAG(name) \ | |
674 | static inline u16 bfin_read_FIO_FLAG_##name(void) \ | |
675 | { \ | |
676 | unsigned long flags; \ | |
677 | u16 ret; \ | |
6a01f230 | 678 | local_irq_save_hw(flags); \ |
b1271d31 MF |
679 | ret = bfin_read16(FIO_FLAG_##name); \ |
680 | bfin_read_CHIPID(); \ | |
6a01f230 | 681 | local_irq_restore_hw(flags); \ |
b1271d31 MF |
682 | return ret; \ |
683 | } | |
684 | BFIN_READ_FIO_FLAG(D) | |
685 | BFIN_READ_FIO_FLAG(C) | |
686 | BFIN_READ_FIO_FLAG(S) | |
687 | BFIN_READ_FIO_FLAG(T) | |
688 | ||
689 | #else | |
690 | #define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) | |
691 | #define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) | |
692 | #define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) | |
693 | #define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) | |
694 | #define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) | |
695 | #define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) | |
696 | #define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) | |
697 | #define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) | |
698 | #endif | |
699 | ||
1394f032 | 700 | #endif /* _CDEF_BF532_H */ |