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1394f032 BW |
1 | /* |
2 | * File: arch/blackfin/mach-bf537/boards/cm_bf537.c | |
3 | * Based on: arch/blackfin/mach-bf533/boards/ezkit.c | |
4 | * Author: Aidan Williams <aidan@nicta.com.au> | |
5 | * | |
6 | * Created: 2005 | |
7 | * Description: Board description file | |
8 | * | |
9 | * Modified: | |
10 | * Copyright 2005 National ICT Australia (NICTA) | |
11 | * Copyright 2004-2006 Analog Devices Inc. | |
12 | * | |
13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, see the file COPYING, or write | |
27 | * to the Free Software Foundation, Inc., | |
28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
29 | */ | |
30 | ||
31 | #include <linux/device.h> | |
43f73fef | 32 | #include <linux/etherdevice.h> |
1394f032 BW |
33 | #include <linux/platform_device.h> |
34 | #include <linux/mtd/mtd.h> | |
35 | #include <linux/mtd/partitions.h> | |
36 | #include <linux/spi/spi.h> | |
37 | #include <linux/spi/flash.h> | |
f02bcec5 | 38 | #include <linux/usb/isp1362.h> |
0a87e3e9 | 39 | #include <linux/ata_platform.h> |
1f83b8f1 | 40 | #include <linux/irq.h> |
c6c4d7bb | 41 | #include <asm/dma.h> |
1394f032 | 42 | #include <asm/bfin5xx_spi.h> |
5d448dd5 | 43 | #include <asm/portmux.h> |
1394f032 BW |
44 | |
45 | /* | |
46 | * Name the Board for the /proc/cpuinfo | |
47 | */ | |
066954a3 | 48 | const char bfin_board_name[] = "Bluetechnix CM BF537"; |
1394f032 BW |
49 | |
50 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
51 | /* all SPI peripherals info goes here */ | |
52 | ||
53 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | |
54 | static struct mtd_partition bfin_spi_flash_partitions[] = { | |
55 | { | |
56 | .name = "bootloader", | |
57 | .size = 0x00020000, | |
58 | .offset = 0, | |
59 | .mask_flags = MTD_CAP_ROM | |
1f83b8f1 | 60 | }, { |
1394f032 BW |
61 | .name = "kernel", |
62 | .size = 0xe0000, | |
63 | .offset = 0x20000 | |
1f83b8f1 | 64 | }, { |
1394f032 BW |
65 | .name = "file system", |
66 | .size = 0x700000, | |
67 | .offset = 0x00100000, | |
68 | } | |
69 | }; | |
70 | ||
71 | static struct flash_platform_data bfin_spi_flash_data = { | |
72 | .name = "m25p80", | |
73 | .parts = bfin_spi_flash_partitions, | |
74 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | |
75 | .type = "m25p64", | |
76 | }; | |
77 | ||
78 | /* SPI flash chip (m25p64) */ | |
79 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | |
80 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
81 | .bits_per_word = 8, | |
82 | }; | |
83 | #endif | |
84 | ||
85 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | |
86 | /* SPI ADC chip */ | |
87 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | |
88 | .enable_dma = 1, /* use dma transfer with this chip*/ | |
89 | .bits_per_word = 16, | |
90 | }; | |
91 | #endif | |
92 | ||
93 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | |
94 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |
95 | .enable_dma = 0, | |
96 | .bits_per_word = 16, | |
97 | }; | |
98 | #endif | |
99 | ||
100 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | |
101 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |
102 | .enable_dma = 0, | |
103 | .bits_per_word = 16, | |
104 | }; | |
105 | #endif | |
106 | ||
107 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | |
108 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | |
109 | .enable_dma = 1, | |
110 | .bits_per_word = 8, | |
111 | }; | |
112 | #endif | |
113 | ||
114 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | |
115 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | |
116 | { | |
117 | /* the modalias must be the same as spi device driver name */ | |
118 | .modalias = "m25p80", /* Name of spi_driver for this device */ | |
119 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 120 | .bus_num = 0, /* Framework bus number */ |
1394f032 BW |
121 | .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ |
122 | .platform_data = &bfin_spi_flash_data, | |
123 | .controller_data = &spi_flash_chip_info, | |
124 | .mode = SPI_MODE_3, | |
125 | }, | |
126 | #endif | |
127 | ||
128 | #if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE) | |
129 | { | |
130 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | |
131 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 132 | .bus_num = 0, /* Framework bus number */ |
1394f032 BW |
133 | .chip_select = 1, /* Framework chip select. */ |
134 | .platform_data = NULL, /* No spi_driver specific config */ | |
135 | .controller_data = &spi_adc_chip_info, | |
136 | }, | |
137 | #endif | |
138 | ||
139 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | |
140 | { | |
141 | .modalias = "ad1836-spi", | |
142 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 143 | .bus_num = 0, |
1394f032 BW |
144 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
145 | .controller_data = &ad1836_spi_chip_info, | |
146 | }, | |
147 | #endif | |
148 | ||
149 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | |
150 | { | |
151 | .modalias = "ad9960-spi", | |
152 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 153 | .bus_num = 0, |
1394f032 BW |
154 | .chip_select = 1, |
155 | .controller_data = &ad9960_spi_chip_info, | |
156 | }, | |
157 | #endif | |
158 | ||
159 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | |
160 | { | |
161 | .modalias = "spi_mmc_dummy", | |
162 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 163 | .bus_num = 0, |
1394f032 BW |
164 | .chip_select = 7, |
165 | .platform_data = NULL, | |
166 | .controller_data = &spi_mmc_chip_info, | |
167 | .mode = SPI_MODE_3, | |
168 | }, | |
169 | { | |
170 | .modalias = "spi_mmc", | |
171 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 172 | .bus_num = 0, |
1394f032 BW |
173 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, |
174 | .platform_data = NULL, | |
175 | .controller_data = &spi_mmc_chip_info, | |
176 | .mode = SPI_MODE_3, | |
177 | }, | |
178 | #endif | |
179 | }; | |
180 | ||
c6c4d7bb BW |
181 | /* SPI (0) */ |
182 | static struct resource bfin_spi0_resource[] = { | |
183 | [0] = { | |
184 | .start = SPI0_REGBASE, | |
185 | .end = SPI0_REGBASE + 0xFF, | |
186 | .flags = IORESOURCE_MEM, | |
187 | }, | |
188 | [1] = { | |
189 | .start = CH_SPI, | |
190 | .end = CH_SPI, | |
191 | .flags = IORESOURCE_IRQ, | |
192 | } | |
193 | }; | |
194 | ||
1394f032 | 195 | /* SPI controller data */ |
c6c4d7bb | 196 | static struct bfin5xx_spi_master bfin_spi0_info = { |
1394f032 BW |
197 | .num_chipselect = 8, |
198 | .enable_dma = 1, /* master has the ability to do dma transfer */ | |
5d448dd5 | 199 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
1394f032 BW |
200 | }; |
201 | ||
c6c4d7bb BW |
202 | static struct platform_device bfin_spi0_device = { |
203 | .name = "bfin-spi", | |
204 | .id = 0, /* Bus number */ | |
205 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
206 | .resource = bfin_spi0_resource, | |
1394f032 | 207 | .dev = { |
c6c4d7bb | 208 | .platform_data = &bfin_spi0_info, /* Passed to driver */ |
1394f032 BW |
209 | }, |
210 | }; | |
211 | #endif /* spi master and devices */ | |
212 | ||
213 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | |
214 | static struct platform_device rtc_device = { | |
215 | .name = "rtc-bfin", | |
216 | .id = -1, | |
217 | }; | |
218 | #endif | |
219 | ||
0d4a89bb MH |
220 | #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) |
221 | static struct platform_device hitachi_fb_device = { | |
222 | .name = "hitachi-tx09", | |
223 | }; | |
224 | #endif | |
225 | ||
1394f032 BW |
226 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
227 | static struct resource smc91x_resources[] = { | |
228 | { | |
229 | .start = 0x20200300, | |
230 | .end = 0x20200300 + 16, | |
231 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 232 | }, { |
1394f032 BW |
233 | .start = IRQ_PF14, |
234 | .end = IRQ_PF14, | |
235 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
236 | }, | |
237 | }; | |
238 | ||
239 | static struct platform_device smc91x_device = { | |
240 | .name = "smc91x", | |
241 | .id = 0, | |
242 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
243 | .resource = smc91x_resources, | |
244 | }; | |
245 | #endif | |
246 | ||
247 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | |
248 | static struct resource isp1362_hcd_resources[] = { | |
249 | { | |
250 | .start = 0x20308000, | |
251 | .end = 0x20308000, | |
252 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 253 | }, { |
1394f032 BW |
254 | .start = 0x20308004, |
255 | .end = 0x20308004, | |
256 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 257 | }, { |
1394f032 BW |
258 | .start = IRQ_PG15, |
259 | .end = IRQ_PG15, | |
260 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
261 | }, | |
262 | }; | |
263 | ||
264 | static struct isp1362_platform_data isp1362_priv = { | |
265 | .sel15Kres = 1, | |
266 | .clknotstop = 0, | |
267 | .oc_enable = 0, | |
268 | .int_act_high = 0, | |
269 | .int_edge_triggered = 0, | |
270 | .remote_wakeup_connected = 0, | |
271 | .no_power_switching = 1, | |
272 | .power_switching_mode = 0, | |
273 | }; | |
274 | ||
275 | static struct platform_device isp1362_hcd_device = { | |
276 | .name = "isp1362-hcd", | |
277 | .id = 0, | |
278 | .dev = { | |
279 | .platform_data = &isp1362_priv, | |
280 | }, | |
281 | .num_resources = ARRAY_SIZE(isp1362_hcd_resources), | |
282 | .resource = isp1362_hcd_resources, | |
283 | }; | |
284 | #endif | |
285 | ||
286 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | |
287 | static struct resource net2272_bfin_resources[] = { | |
288 | { | |
289 | .start = 0x20200000, | |
290 | .end = 0x20200000 + 0x100, | |
291 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 292 | }, { |
8ecc7368 MH |
293 | .start = IRQ_PH14, |
294 | .end = IRQ_PH14, | |
1394f032 BW |
295 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
296 | }, | |
297 | }; | |
298 | ||
299 | static struct platform_device net2272_bfin_device = { | |
300 | .name = "net2272", | |
301 | .id = -1, | |
302 | .num_resources = ARRAY_SIZE(net2272_bfin_resources), | |
303 | .resource = net2272_bfin_resources, | |
304 | }; | |
305 | #endif | |
306 | ||
307 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
308 | static struct resource bfin_uart_resources[] = { | |
309 | { | |
310 | .start = 0xFFC00400, | |
311 | .end = 0xFFC004FF, | |
312 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 313 | }, { |
1394f032 BW |
314 | .start = 0xFFC02000, |
315 | .end = 0xFFC020FF, | |
316 | .flags = IORESOURCE_MEM, | |
317 | }, | |
318 | }; | |
319 | ||
320 | static struct platform_device bfin_uart_device = { | |
321 | .name = "bfin-uart", | |
322 | .id = 1, | |
323 | .num_resources = ARRAY_SIZE(bfin_uart_resources), | |
324 | .resource = bfin_uart_resources, | |
325 | }; | |
326 | #endif | |
327 | ||
328 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | |
329 | static struct platform_device bfin_sport0_uart_device = { | |
330 | .name = "bfin-sport-uart", | |
331 | .id = 0, | |
332 | }; | |
333 | ||
334 | static struct platform_device bfin_sport1_uart_device = { | |
335 | .name = "bfin-sport-uart", | |
336 | .id = 1, | |
337 | }; | |
338 | #endif | |
339 | ||
340 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | |
341 | static struct platform_device bfin_mac_device = { | |
342 | .name = "bfin_mac", | |
343 | }; | |
344 | #endif | |
345 | ||
c6c4d7bb BW |
346 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) |
347 | #define PATA_INT 64 | |
348 | ||
349 | static struct pata_platform_info bfin_pata_platform_data = { | |
350 | .ioport_shift = 2, | |
351 | .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED, | |
352 | }; | |
353 | ||
354 | static struct resource bfin_pata_resources[] = { | |
355 | { | |
356 | .start = 0x2030C000, | |
357 | .end = 0x2030C01F, | |
358 | .flags = IORESOURCE_MEM, | |
359 | }, | |
360 | { | |
361 | .start = 0x2030D018, | |
362 | .end = 0x2030D01B, | |
363 | .flags = IORESOURCE_MEM, | |
364 | }, | |
365 | { | |
366 | .start = PATA_INT, | |
367 | .end = PATA_INT, | |
368 | .flags = IORESOURCE_IRQ, | |
369 | }, | |
370 | }; | |
371 | ||
372 | static struct platform_device bfin_pata_device = { | |
373 | .name = "pata_platform", | |
374 | .id = -1, | |
375 | .num_resources = ARRAY_SIZE(bfin_pata_resources), | |
376 | .resource = bfin_pata_resources, | |
377 | .dev = { | |
378 | .platform_data = &bfin_pata_platform_data, | |
379 | } | |
380 | }; | |
381 | #endif | |
382 | ||
1394f032 | 383 | static struct platform_device *cm_bf537_devices[] __initdata = { |
0d4a89bb MH |
384 | #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) |
385 | &hitachi_fb_device, | |
386 | #endif | |
387 | ||
1394f032 BW |
388 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) |
389 | &rtc_device, | |
390 | #endif | |
391 | ||
392 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
393 | &bfin_uart_device, | |
394 | #endif | |
395 | ||
396 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | |
397 | &bfin_sport0_uart_device, | |
398 | &bfin_sport1_uart_device, | |
399 | #endif | |
400 | ||
401 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | |
402 | &isp1362_hcd_device, | |
403 | #endif | |
404 | ||
405 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | |
406 | &smc91x_device, | |
407 | #endif | |
408 | ||
409 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | |
410 | &bfin_mac_device, | |
411 | #endif | |
412 | ||
413 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | |
414 | &net2272_bfin_device, | |
415 | #endif | |
416 | ||
417 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
c6c4d7bb BW |
418 | &bfin_spi0_device, |
419 | #endif | |
420 | ||
421 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | |
422 | &bfin_pata_device, | |
1394f032 BW |
423 | #endif |
424 | }; | |
425 | ||
426 | static int __init cm_bf537_init(void) | |
427 | { | |
428 | printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); | |
429 | platform_add_devices(cm_bf537_devices, ARRAY_SIZE(cm_bf537_devices)); | |
430 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
431 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | |
432 | #endif | |
c6c4d7bb BW |
433 | |
434 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | |
435 | irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; | |
436 | #endif | |
1394f032 BW |
437 | return 0; |
438 | } | |
439 | ||
440 | arch_initcall(cm_bf537_init); | |
137b1529 | 441 | |
9862cc52 | 442 | void bfin_get_ether_addr(char *addr) |
137b1529 MF |
443 | { |
444 | random_ether_addr(addr); | |
445 | printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); | |
446 | } | |
9862cc52 | 447 | EXPORT_SYMBOL(bfin_get_ether_addr); |