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Blackfin: boards: clean up redundant/dead spi resources
[deliverable/linux.git] / arch / blackfin / mach-bf537 / boards / cm_bf537u.c
CommitLineData
1394f032 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
1394f032 6 *
96f1050d 7 * Licensed under the GPL-2 or later.
1394f032
BW		 8 */
9
10#include <linux/device.h>
43f73fef 11#include <linux/etherdevice.h>
1394f032
BW		 12#include <linux/platform_device.h>
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h>
8ea89497 15#include <linux/mtd/physmap.h>
1394f032
BW		 16#include <linux/spi/spi.h>
17#include <linux/spi/flash.h>
b964c592 18#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5 19#include <linux/usb/isp1362.h>
b964c592 20#endif
0a87e3e9 21#include <linux/ata_platform.h>
1f83b8f1 22#include <linux/irq.h>
c6c4d7bb 23#include <asm/dma.h>
1394f032 24#include <asm/bfin5xx_spi.h>
5d448dd5 25#include <asm/portmux.h>
14b03204 26#include <asm/dpmc.h>
60584344 27#include <linux/spi/mmc_spi.h>
1394f032
BW		 28
29/*
30 * Name the Board for the /proc/cpuinfo
31 */
60584344 32const char bfin_board_name[] = "Bluetechnix CM BF537U";
1394f032
BW		 33
34#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
35/* all SPI peripherals info goes here */
36
37#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
38static struct mtd_partition bfin_spi_flash_partitions[] = {
39 {
aa582977 40 .name = "bootloader(spi)",
1394f032
BW		 41 .size = 0x00020000,
42 .offset = 0,
43 .mask_flags = MTD_CAP_ROM
1f83b8f1 44 }, {
aa582977 45 .name = "linux kernel(spi)",
1394f032
BW		 46 .size = 0xe0000,
47 .offset = 0x20000
1f83b8f1 48 }, {
aa582977 49 .name = "file system(spi)",
1394f032
BW		 50 .size = 0x700000,
51 .offset = 0x00100000,
52 }
53};
54
55static struct flash_platform_data bfin_spi_flash_data = {
56 .name = "m25p80",
57 .parts = bfin_spi_flash_partitions,
58 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
59 .type = "m25p64",
60};
61
62/* SPI flash chip (m25p64) */
63static struct bfin5xx_spi_chip spi_flash_chip_info = {
64 .enable_dma = 0, /* use dma transfer with this chip*/
1394f032
BW		 65};
66#endif
67
f3f704d3
MH		 68#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
69static struct bfin5xx_spi_chip mmc_spi_chip_info = {
70 .enable_dma = 0,
1394f032
BW		 71};
72#endif
73
74static struct spi_board_info bfin_spi_board_info[] __initdata = {
75#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
76 {
77 /* the modalias must be the same as spi device driver name */
78 .modalias = "m25p80", /* Name of spi_driver for this device */
79 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 80 .bus_num = 0, /* Framework bus number */
1394f032
BW		 81 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
82 .platform_data = &bfin_spi_flash_data,
83 .controller_data = &spi_flash_chip_info,
84 .mode = SPI_MODE_3,
85 },
86#endif
87
7ba80063 88#if defined(CONFIG_SND_BF5XX_SOC_AD183X) || defined(CONFIG_SND_BF5XX_SOC_AD183X_MODULE)
1394f032 89 {
7ba80063 90 .modalias = "ad183x",
1394f032 91 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 92 .bus_num = 0,
7ba80063 93 .chip_select = 4,
1394f032
BW		 94 },
95#endif
96
f3f704d3 97#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
1394f032 98 {
f3f704d3
MH		 99 .modalias = "mmc_spi",
100 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb 101 .bus_num = 0,
f3f704d3
MH		 102 .chip_select = 1,
103 .controller_data = &mmc_spi_chip_info,
1394f032
BW		 104 .mode = SPI_MODE_3,
105 },
106#endif
107};
108
c6c4d7bb
BW		 109/* SPI (0) */
110static struct resource bfin_spi0_resource[] = {
111 [0] = {
112 .start = SPI0_REGBASE,
113 .end = SPI0_REGBASE + 0xFF,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = CH_SPI,
118 .end = CH_SPI,
53122693
YL		 119 .flags = IORESOURCE_DMA,
120 },
121 [2] = {
122 .start = IRQ_SPI,
123 .end = IRQ_SPI,
c6c4d7bb 124 .flags = IORESOURCE_IRQ,
53122693 125 },
c6c4d7bb
BW		 126};
127
1394f032 128/* SPI controller data */
c6c4d7bb 129static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032
BW		 130 .num_chipselect = 8,
131 .enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5 132 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032
BW		 133};
134
c6c4d7bb
BW		 135static struct platform_device bfin_spi0_device = {
136 .name = "bfin-spi",
137 .id = 0, /* Bus number */
138 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
139 .resource = bfin_spi0_resource,
1394f032 140 .dev = {
c6c4d7bb 141 .platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032
BW		 142 },
143};
144#endif /* spi master and devices */
145
146#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
147static struct platform_device rtc_device = {
148 .name = "rtc-bfin",
149 .id = -1,
150};
151#endif
152
0d4a89bb
MH		 153#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
154static struct platform_device hitachi_fb_device = {
155 .name = "hitachi-tx09",
156};
157#endif
158
1394f032 159#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 160#include <linux/smc91x.h>
161
162static struct smc91x_platdata smc91x_info = {
163 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
164 .leda = RPC_LED_100_10,
165 .ledb = RPC_LED_TX_RX,
166};
167
1394f032
BW		 168static struct resource smc91x_resources[] = {
169 {
170 .start = 0x20200300,
171 .end = 0x20200300 + 16,
172 .flags = IORESOURCE_MEM,
1f83b8f1 173 }, {
1394f032
BW		 174 .start = IRQ_PF14,
175 .end = IRQ_PF14,
176 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
177 },
178};
179
180static struct platform_device smc91x_device = {
181 .name = "smc91x",
182 .id = 0,
183 .num_resources = ARRAY_SIZE(smc91x_resources),
184 .resource = smc91x_resources,
61f09b5a
MH		 185 .dev = {
186 .platform_data = &smc91x_info,
187 },
1394f032
BW		 188};
189#endif
190
191#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
192static struct resource isp1362_hcd_resources[] = {
193 {
194 .start = 0x20308000,
195 .end = 0x20308000,
196 .flags = IORESOURCE_MEM,
1f83b8f1 197 }, {
1394f032
BW		 198 .start = 0x20308004,
199 .end = 0x20308004,
200 .flags = IORESOURCE_MEM,
1f83b8f1 201 }, {
1394f032
BW		 202 .start = IRQ_PG15,
203 .end = IRQ_PG15,
9e75894c 204 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
1394f032
BW		 205 },
206};
207
208static struct isp1362_platform_data isp1362_priv = {
209 .sel15Kres = 1,
210 .clknotstop = 0,
211 .oc_enable = 0,
212 .int_act_high = 0,
213 .int_edge_triggered = 0,
214 .remote_wakeup_connected = 0,
215 .no_power_switching = 1,
216 .power_switching_mode = 0,
217};
218
219static struct platform_device isp1362_hcd_device = {
220 .name = "isp1362-hcd",
221 .id = 0,
222 .dev = {
223 .platform_data = &isp1362_priv,
224 },
225 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
226 .resource = isp1362_hcd_resources,
227};
228#endif
229
230#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
231static struct resource net2272_bfin_resources[] = {
232 {
233 .start = 0x20200000,
234 .end = 0x20200000 + 0x100,
235 .flags = IORESOURCE_MEM,
1f83b8f1 236 }, {
8ecc7368
MH		 237 .start = IRQ_PH14,
238 .end = IRQ_PH14,
1394f032
BW		 239 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
240 },
241};
242
243static struct platform_device net2272_bfin_device = {
244 .name = "net2272",
245 .id = -1,
246 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
247 .resource = net2272_bfin_resources,
248};
249#endif
250
8ea89497
MF		 251#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
252static struct mtd_partition cm_partitions[] = {
253 {
254 .name = "bootloader(nor)",
255 .size = 0x40000,
256 .offset = 0,
257 }, {
258 .name = "linux kernel(nor)",
60584344 259 .size = 0x100000,
8ea89497
MF		 260 .offset = MTDPART_OFS_APPEND,
261 }, {
262 .name = "file system(nor)",
263 .size = MTDPART_SIZ_FULL,
264 .offset = MTDPART_OFS_APPEND,
265 }
266};
267
268static struct physmap_flash_data cm_flash_data = {
269 .width = 2,
270 .parts = cm_partitions,
271 .nr_parts = ARRAY_SIZE(cm_partitions),
272};
273
60584344 274static unsigned cm_flash_gpios[] = { GPIO_PH0 };
8ea89497
MF		 275
276static struct resource cm_flash_resource[] = {
277 {
278 .name = "cfi_probe",
279 .start = 0x20000000,
280 .end = 0x201fffff,
281 .flags = IORESOURCE_MEM,
282 }, {
283 .start = (unsigned long)cm_flash_gpios,
284 .end = ARRAY_SIZE(cm_flash_gpios),
285 .flags = IORESOURCE_IRQ,
286 }
287};
288
289static struct platform_device cm_flash_device = {
290 .name = "gpio-addr-flash",
291 .id = 0,
292 .dev = {
293 .platform_data = &cm_flash_data,
294 },
295 .num_resources = ARRAY_SIZE(cm_flash_resource),
296 .resource = cm_flash_resource,
297};
298#endif
299
1394f032 300#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 301#ifdef CONFIG_SERIAL_BFIN_UART0
302static struct resource bfin_uart0_resources[] = {
1394f032 303 {
6bd1fbea
SZ		 304 .start = UART0_THR,
305 .end = UART0_GCTL+2,
1394f032 306 .flags = IORESOURCE_MEM,
6bd1fbea
SZ		 307 },
308 {
309 .start = IRQ_UART0_RX,
310 .end = IRQ_UART0_RX+1,
311 .flags = IORESOURCE_IRQ,
312 },
313 {
314 .start = IRQ_UART0_ERROR,
315 .end = IRQ_UART0_ERROR,
316 .flags = IORESOURCE_IRQ,
317 },
318 {
319 .start = CH_UART0_TX,
320 .end = CH_UART0_TX,
321 .flags = IORESOURCE_DMA,
322 },
323 {
324 .start = CH_UART0_RX,
325 .end = CH_UART0_RX,
326 .flags = IORESOURCE_DMA,
327 },
328};
329
a8b19886 330static unsigned short bfin_uart0_peripherals[] = {
6bd1fbea
SZ		 331 P_UART0_TX, P_UART0_RX, 0
332};
333
334static struct platform_device bfin_uart0_device = {
335 .name = "bfin-uart",
336 .id = 0,
337 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
338 .resource = bfin_uart0_resources,
339 .dev = {
340 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
341 },
342};
343#endif
344#ifdef CONFIG_SERIAL_BFIN_UART1
345static struct resource bfin_uart1_resources[] = {
346 {
347 .start = UART1_THR,
348 .end = UART1_GCTL+2,
1394f032
BW		 349 .flags = IORESOURCE_MEM,
350 },
6bd1fbea
SZ		 351 {
352 .start = IRQ_UART1_RX,
353 .end = IRQ_UART1_RX+1,
354 .flags = IORESOURCE_IRQ,
355 },
356 {
357 .start = IRQ_UART1_ERROR,
358 .end = IRQ_UART1_ERROR,
359 .flags = IORESOURCE_IRQ,
360 },
361 {
362 .start = CH_UART1_TX,
363 .end = CH_UART1_TX,
364 .flags = IORESOURCE_DMA,
365 },
366 {
367 .start = CH_UART1_RX,
368 .end = CH_UART1_RX,
369 .flags = IORESOURCE_DMA,
370 },
1394f032
BW		 371};
372
a8b19886 373static unsigned short bfin_uart1_peripherals[] = {
6bd1fbea
SZ		 374 P_UART1_TX, P_UART1_RX, 0
375};
376
377static struct platform_device bfin_uart1_device = {
1394f032
BW		 378 .name = "bfin-uart",
379 .id = 1,
6bd1fbea
SZ		 380 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
381 .resource = bfin_uart1_resources,
382 .dev = {
383 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
384 },
1394f032
BW		 385};
386#endif
6bd1fbea 387#endif
1394f032 388
5be36d22 389#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
5be36d22 390#ifdef CONFIG_BFIN_SIR0
42bd8bcb 391static struct resource bfin_sir0_resources[] = {
5be36d22
GY		 392 {
393 .start = 0xFFC00400,
394 .end = 0xFFC004FF,
395 .flags = IORESOURCE_MEM,
396 },
42bd8bcb
GY		 397 {
398 .start = IRQ_UART0_RX,
399 .end = IRQ_UART0_RX+1,
400 .flags = IORESOURCE_IRQ,
401 },
402 {
403 .start = CH_UART0_RX,
404 .end = CH_UART0_RX+1,
405 .flags = IORESOURCE_DMA,
406 },
407};
408static struct platform_device bfin_sir0_device = {
409 .name = "bfin_sir",
410 .id = 0,
411 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
412 .resource = bfin_sir0_resources,
413};
5be36d22
GY		 414#endif
415#ifdef CONFIG_BFIN_SIR1
42bd8bcb 416static struct resource bfin_sir1_resources[] = {
5be36d22
GY		 417 {
418 .start = 0xFFC02000,
419 .end = 0xFFC020FF,
420 .flags = IORESOURCE_MEM,
421 },
42bd8bcb
GY		 422 {
423 .start = IRQ_UART1_RX,
424 .end = IRQ_UART1_RX+1,
425 .flags = IORESOURCE_IRQ,
426 },
427 {
428 .start = CH_UART1_RX,
429 .end = CH_UART1_RX+1,
430 .flags = IORESOURCE_DMA,
431 },
5be36d22 432};
42bd8bcb 433static struct platform_device bfin_sir1_device = {
5be36d22 434 .name = "bfin_sir",
42bd8bcb
GY		 435 .id = 1,
436 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
437 .resource = bfin_sir1_resources,
5be36d22
GY		 438};
439#endif
42bd8bcb 440#endif
5be36d22 441
56ce835b
MF		 442#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
443static struct resource bfin_twi0_resource[] = {
444 [0] = {
445 .start = TWI0_REGBASE,
446 .end = TWI0_REGBASE,
447 .flags = IORESOURCE_MEM,
448 },
449 [1] = {
450 .start = IRQ_TWI,
451 .end = IRQ_TWI,
452 .flags = IORESOURCE_IRQ,
453 },
454};
455
456static struct platform_device i2c_bfin_twi_device = {
457 .name = "i2c-bfin-twi",
458 .id = 0,
459 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
460 .resource = bfin_twi0_resource,
461};
462#endif
463
1394f032 464#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 465#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
466static struct resource bfin_sport0_uart_resources[] = {
467 {
468 .start = SPORT0_TCR1,
469 .end = SPORT0_MRCS3+4,
470 .flags = IORESOURCE_MEM,
471 },
472 {
473 .start = IRQ_SPORT0_RX,
474 .end = IRQ_SPORT0_RX+1,
475 .flags = IORESOURCE_IRQ,
476 },
477 {
478 .start = IRQ_SPORT0_ERROR,
479 .end = IRQ_SPORT0_ERROR,
480 .flags = IORESOURCE_IRQ,
481 },
482};
483
a8b19886 484static unsigned short bfin_sport0_peripherals[] = {
df5de261 485 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
e54b6730 486 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
df5de261
SZ		 487};
488
1394f032
BW		 489static struct platform_device bfin_sport0_uart_device = {
490 .name = "bfin-sport-uart",
491 .id = 0,
df5de261
SZ		 492 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
493 .resource = bfin_sport0_uart_resources,
494 .dev = {
495 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
496 },
497};
498#endif
499#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
500static struct resource bfin_sport1_uart_resources[] = {
501 {
502 .start = SPORT1_TCR1,
503 .end = SPORT1_MRCS3+4,
504 .flags = IORESOURCE_MEM,
505 },
506 {
507 .start = IRQ_SPORT1_RX,
508 .end = IRQ_SPORT1_RX+1,
509 .flags = IORESOURCE_IRQ,
510 },
511 {
512 .start = IRQ_SPORT1_ERROR,
513 .end = IRQ_SPORT1_ERROR,
514 .flags = IORESOURCE_IRQ,
515 },
516};
517
a8b19886 518static unsigned short bfin_sport1_peripherals[] = {
df5de261 519 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
e54b6730 520 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
1394f032
BW		 521};
522
523static struct platform_device bfin_sport1_uart_device = {
524 .name = "bfin-sport-uart",
525 .id = 1,
df5de261
SZ		 526 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
527 .resource = bfin_sport1_uart_resources,
528 .dev = {
529 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
530 },
1394f032
BW		 531};
532#endif
df5de261 533#endif
1394f032
BW		 534
535#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
02460d08
SZ		 536#include <linux/bfin_mac.h>
537static const unsigned short bfin_mac_peripherals[] = P_MII0;
538
539static struct bfin_phydev_platform_data bfin_phydev_data[] = {
540 {
541 .addr = 1,
542 .irq = IRQ_MAC_PHYINT,
543 },
544};
545
546static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
547 .phydev_number = 1,
548 .phydev_data = bfin_phydev_data,
549 .phy_mode = PHY_INTERFACE_MODE_MII,
550 .mac_peripherals = bfin_mac_peripherals,
551};
552
65319628
GY		 553static struct platform_device bfin_mii_bus = {
554 .name = "bfin_mii_bus",
02460d08
SZ		 555 .dev = {
556 .platform_data = &bfin_mii_bus_data,
557 }
65319628
GY		 558};
559
1394f032
BW		 560static struct platform_device bfin_mac_device = {
561 .name = "bfin_mac",
02460d08
SZ		 562 .dev = {
563 .platform_data = &bfin_mii_bus,
564 }
1394f032
BW		 565};
566#endif
567
c6c4d7bb 568#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
fe5aeb93 569#define PATA_INT IRQ_PF14
c6c4d7bb
BW		 570
571static struct pata_platform_info bfin_pata_platform_data = {
572 .ioport_shift = 2,
573 .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
574};
575
576static struct resource bfin_pata_resources[] = {
577 {
578 .start = 0x2030C000,
579 .end = 0x2030C01F,
580 .flags = IORESOURCE_MEM,
581 },
582 {
583 .start = 0x2030D018,
584 .end = 0x2030D01B,
585 .flags = IORESOURCE_MEM,
586 },
587 {
588 .start = PATA_INT,
589 .end = PATA_INT,
590 .flags = IORESOURCE_IRQ,
591 },
592};
593
594static struct platform_device bfin_pata_device = {
595 .name = "pata_platform",
596 .id = -1,
597 .num_resources = ARRAY_SIZE(bfin_pata_resources),
598 .resource = bfin_pata_resources,
599 .dev = {
600 .platform_data = &bfin_pata_platform_data,
601 }
602};
603#endif
604
14b03204
MH		 605static const unsigned int cclk_vlev_datasheet[] =
606{
607 VRPAIR(VLEV_085, 250000000),
608 VRPAIR(VLEV_090, 376000000),
609 VRPAIR(VLEV_095, 426000000),
610 VRPAIR(VLEV_100, 426000000),
611 VRPAIR(VLEV_105, 476000000),
612 VRPAIR(VLEV_110, 476000000),
613 VRPAIR(VLEV_115, 476000000),
614 VRPAIR(VLEV_120, 500000000),
615 VRPAIR(VLEV_125, 533000000),
616 VRPAIR(VLEV_130, 600000000),
617};
618
619static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
620 .tuple_tab = cclk_vlev_datasheet,
621 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
622 .vr_settling_time = 25 /* us */,
623};
624
625static struct platform_device bfin_dpmc = {
626 .name = "bfin dpmc",
627 .dev = {
628 .platform_data = &bfin_dmpc_vreg_data,
629 },
630};
631
60584344 632static struct platform_device *cm_bf537u_devices[] __initdata = {
14b03204
MH		 633
634 &bfin_dpmc,
635
0d4a89bb
MH		 636#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
637 &hitachi_fb_device,
638#endif
639
1394f032
BW		 640#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
641 &rtc_device,
642#endif
643
644#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 645#ifdef CONFIG_SERIAL_BFIN_UART0
646 &bfin_uart0_device,
647#endif
648#ifdef CONFIG_SERIAL_BFIN_UART1
649 &bfin_uart1_device,
650#endif
1394f032
BW		 651#endif
652
5be36d22 653#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 654#ifdef CONFIG_BFIN_SIR0
655 &bfin_sir0_device,
656#endif
657#ifdef CONFIG_BFIN_SIR1
658 &bfin_sir1_device,
659#endif
5be36d22
GY		 660#endif
661
56ce835b
MF		 662#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
663 &i2c_bfin_twi_device,
664#endif
665
1394f032 666#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 667#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1394f032 668 &bfin_sport0_uart_device,
df5de261
SZ		 669#endif
670#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1394f032
BW		 671 &bfin_sport1_uart_device,
672#endif
df5de261 673#endif
1394f032
BW		 674
675#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
676 &isp1362_hcd_device,
677#endif
678
679#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
680 &smc91x_device,
681#endif
682
683#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 684 &bfin_mii_bus,
1394f032
BW		 685 &bfin_mac_device,
686#endif
687
688#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
689 &net2272_bfin_device,
690#endif
691
692#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb
BW		 693 &bfin_spi0_device,
694#endif
695
696#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
697 &bfin_pata_device,
1394f032 698#endif
8ea89497
MF		 699
700#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
701 &cm_flash_device,
702#endif
1394f032
BW		 703};
704
9be8631b
MF		 705static int __init net2272_init(void)
706{
707#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
708 int ret;
709
710 ret = gpio_request(GPIO_PH15, driver_name);
711 if (ret)
712 return ret;
713
714 ret = gpio_request(GPIO_PH13, "net2272");
715 if (ret) {
716 gpio_free(GPIO_PH15);
717 return ret;
718 }
719
720 /* Set PH15 Low make /AMS2 work properly */
721 gpio_direction_output(GPIO_PH15, 0);
722
723 /* enable CLKBUF output */
724 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
725
726 /* Reset the USB chip */
727 gpio_direction_output(GPIO_PH13, 0);
728 mdelay(2);
729 gpio_set_value(GPIO_PH13, 1);
730#endif
731
732 return 0;
733}
734
60584344 735static int __init cm_bf537u_init(void)
1394f032 736{
b85d858b 737 printk(KERN_INFO "%s(): registering device resources\n", __func__);
60584344 738 platform_add_devices(cm_bf537u_devices, ARRAY_SIZE(cm_bf537u_devices));
1394f032
BW		 739#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
740 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
741#endif
c6c4d7bb
BW		 742
743#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
bc2f6bd8 744 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
c6c4d7bb 745#endif
9be8631b
MF		 746
747 if (net2272_init())
748 pr_warning("unable to configure net2272; it probably won't work\n");
749
1394f032
BW		 750 return 0;
751}
752
60584344 753arch_initcall(cm_bf537u_init);
137b1529 754
c13ce9fd
SZ		 755static struct platform_device *cm_bf537u_early_devices[] __initdata = {
756#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
757#ifdef CONFIG_SERIAL_BFIN_UART0
758 &bfin_uart0_device,
759#endif
760#ifdef CONFIG_SERIAL_BFIN_UART1
761 &bfin_uart1_device,
762#endif
763#endif
764
765#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
766#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
767 &bfin_sport0_uart_device,
768#endif
769#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
770 &bfin_sport1_uart_device,
771#endif
772#endif
773};
774
775void __init native_machine_early_platform_add_devices(void)
776{
777 printk(KERN_INFO "register early platform devices\n");
778 early_platform_add_devices(cm_bf537u_early_devices,
779 ARRAY_SIZE(cm_bf537u_early_devices));
780}
781
9862cc52 782void bfin_get_ether_addr(char *addr)
137b1529
MF		 783{
784 random_ether_addr(addr);
785 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
786}
9862cc52 787EXPORT_SYMBOL(bfin_get_ether_addr);
Linux kernel - Deliverables
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