[deliverable/linux.git] / arch / blackfin / mach-bf537 / include / mach / anomaly.h

/*
 * File: include/asm-blackfin/mach-bf537/anomaly.h
 * Bugs: Enter bugs at http://blackfin.uclinux.org/
 *
 * Copyright (C) 2004-2009 Analog Devices Inc.
 * Licensed under the GPL-2 or later.
 */

/* This file should be up to date with:
 *  - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
 */

#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_

/* We do not support 0.1 silicon - sorry */
#if __SILICON_REVISION__ < 2
# error will not work on BF537 silicon version 0.0 or 0.1
#endif

#if defined(__ADSPBF534__)
# define ANOMALY_BF534 1
#else
# define ANOMALY_BF534 0
#endif
#if defined(__ADSPBF536__)
# define ANOMALY_BF536 1
#else
# define ANOMALY_BF536 0
#endif
#if defined(__ADSPBF537__)
# define ANOMALY_BF537 1
#else
# define ANOMALY_BF537 0
#endif

/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000180 (1)
/* Instruction Cache Is Not Functional */
#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Buffered CLKIN Output Is Disabled by Default */
#define ANOMALY_05000247 (1)
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
/* EMAC TX DMA Error After an Early Frame Abort */
#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
/* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
/* EMAC MDIO Input Latched on Wrong MDC Edge */
#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
/* ICPLB_STATUS MMR Register May Be Corrupted */
#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
/* Stores To Data Cache May Be Lost */
#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
/* Hardware Loop Corrupted When Taking an ICPLB Exception */
#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* Writes to Synchronous SDRAM Memory May Be Lost */
#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
#define ANOMALY_05000280 (1)
/* False Hardware Error Exception when ISR Context Is Not Restored */
#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
#define ANOMALY_05000301 (1)
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (1)
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
#define ANOMALY_05000322 (1)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
/* UART Gets Disabled after UART Boot */
#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000359 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
#define ANOMALY_05000425 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)

/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)

#endif
Commit	Line	Data
1394f032	1	/*
287050fe MF	2	* File: include/asm-blackfin/mach-bf537/anomaly.h
287050fe MF	3	* Bugs: Enter bugs at http://blackfin.uclinux.org/
1394f032	4	*
c18e99cf	5	* Copyright (C) 2004-2009 Analog Devices Inc.
287050fe	6	* Licensed under the GPL-2 or later.
1394f032 BW	7	*/
1394f032 BW	8
a413647b	9	/* This file should be up to date with:
6651ece9	10	* - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
1394f032 BW	11	*/
	12
	13	#ifndef _MACH_ANOMALY_H_
	14	#define _MACH_ANOMALY_H_
	15
	16	/* We do not support 0.1 silicon - sorry */
1aafd909	17	#if __SILICON_REVISION__ < 2
7cc1c4b2	18	# error will not work on BF537 silicon version 0.0 or 0.1
1394f032 BW	19	#endif
1394f032 BW	20
1aafd909 MF	21	#if defined(__ADSPBF534__)
	22	# define ANOMALY_BF534 1
	23	#else
	24	# define ANOMALY_BF534 0
1394f032	25	#endif
1aafd909 MF	26	#if defined(__ADSPBF536__)
	27	# define ANOMALY_BF536 1
	28	#else
	29	# define ANOMALY_BF536 0
1394f032	30	#endif
1aafd909 MF	31	#if defined(__ADSPBF537__)
	32	# define ANOMALY_BF537 1
	33	#else
	34	# define ANOMALY_BF537 0
1394f032	35	#endif
1394f032	36
a200ad22	37	/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
1aafd909	38	#define ANOMALY_05000074 (1)
a413647b	39	/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
1aafd909	40	#define ANOMALY_05000119 (1)
a413647b	41	/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
1aafd909	42	#define ANOMALY_05000122 (1)
a200ad22	43	/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
1aafd909	44	#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
a413647b	45	/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
1aafd909 MF	46	#define ANOMALY_05000180 (1)
	47	/* Instruction Cache Is Not Functional */
	48	#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
a413647b	49	/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
1aafd909	50	#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
a413647b	51	/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
1aafd909	52	#define ANOMALY_05000245 (1)
a200ad22	53	/* Buffered CLKIN Output Is Disabled by Default */
1aafd909	54	#define ANOMALY_05000247 (1)
a413647b	55	/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
1aafd909	56	#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
a200ad22	57	/* EMAC TX DMA Error After an Early Frame Abort */
1aafd909	58	#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
a413647b	59	/* Maximum External Clock Speed for Timers */
1aafd909	60	#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
a413647b	61	/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
1aafd909	62	#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
a413647b	63	/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
1aafd909	64	#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
a200ad22	65	/* EMAC MDIO Input Latched on Wrong MDC Edge */
1aafd909	66	#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
a413647b	67	/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
1aafd909	68	#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
a413647b	69	/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
1aafd909	70	#define ANOMALY_05000258 (((ANOMALY_BF536 \|\| ANOMALY_BF537) && __SILICON_REVISION__ == 1) \|\| __SILICON_REVISION__ == 2)
a413647b	71	/* ICPLB_STATUS MMR Register May Be Corrupted */
1aafd909	72	#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
a413647b	73	/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
1aafd909	74	#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
a413647b	75	/* Stores To Data Cache May Be Lost */
1aafd909	76	#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
a413647b	77	/* Hardware Loop Corrupted When Taking an ICPLB Exception */
1aafd909	78	#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
a413647b	79	/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
1aafd909	80	#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
a413647b	81	/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
1aafd909	82	#define ANOMALY_05000265 (1)
a200ad22	83	/* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
1aafd909	84	#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
a413647b	85	/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
1aafd909	86	#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
a413647b	87	/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
1aafd909	88	#define ANOMALY_05000272 (1)
a413647b	89	/* Writes to Synchronous SDRAM Memory May Be Lost */
1aafd909	90	#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
a413647b	91	/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
1aafd909	92	#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
a413647b	93	/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
1aafd909	94	#define ANOMALY_05000278 (((ANOMALY_BF536 \|\| ANOMALY_BF537) && __SILICON_REVISION__ < 3) \|\| (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
a200ad22	95	/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
1aafd909	96	#define ANOMALY_05000280 (1)
a200ad22	97	/* False Hardware Error Exception when ISR Context Is Not Restored */
1aafd909	98	#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
a413647b	99	/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
1aafd909	100	#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
a200ad22	101	/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
1aafd909	102	#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
a200ad22	103	/* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
1aafd909	104	#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
a413647b	105	/* SPORTs May Receive Bad Data If FIFOs Fill Up */
1aafd909	106	#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
a413647b	107	/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
1aafd909 MF	108	#define ANOMALY_05000301 (1)
	109	/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
	110	#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
c18e99cf	111	/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
1aafd909 MF	112	#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
	113	/* SCKELOW Bit Does Not Maintain State Through Hibernate */
	114	#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
a200ad22	115	/* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
1aafd909	116	#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
a413647b	117	/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
1aafd909	118	#define ANOMALY_05000310 (1)
a200ad22	119	/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
1aafd909	120	#define ANOMALY_05000312 (1)
a413647b	121	/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
1aafd909	122	#define ANOMALY_05000313 (1)
a200ad22	123	/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
1aafd909	124	#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
a200ad22	125	/* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
1aafd909	126	#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
a200ad22	127	/* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
1aafd909	128	#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
a200ad22	129	/* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
1aafd909	130	#define ANOMALY_05000322 (1)
7cc1c4b2 MF	131	/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
7cc1c4b2 MF	132	#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
a200ad22	133	/* UART Gets Disabled after UART Boot */
a70ce072	134	#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
4d555630 SZ	135	/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
4d555630 SZ	136	#define ANOMALY_05000355 (1)
7cc1c4b2 MF	137	/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
	138	#define ANOMALY_05000357 (1)
	139	/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
	140	#define ANOMALY_05000359 (1)
4d555630 SZ	141	/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
	142	#define ANOMALY_05000366 (1)
	143	/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
	144	#define ANOMALY_05000371 (1)
	145	/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
bd411b15	146	#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
4d555630 SZ	147	/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
4d555630 SZ	148	#define ANOMALY_05000403 (1)
6651ece9 MF	149	/* Speculative Fetches Can Cause Undesired External FIFO Operations */
	150	#define ANOMALY_05000416 (1)
	151	/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
	152	#define ANOMALY_05000425 (1)
	153	/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
	154	#define ANOMALY_05000426 (1)
3529e041 MF	155	/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
3529e041 MF	156	#define ANOMALY_05000443 (1)
a200ad22	157	/* False Hardware Error when RETI Points to Invalid Memory */
a413647b	158	#define ANOMALY_05000461 (1)
4d555630	159
1aafd909	160	/* Anomalies that don't exist on this proc */
a413647b MF	161	#define ANOMALY_05000099 (0)
a413647b MF	162	#define ANOMALY_05000120 (0)
1aafd909	163	#define ANOMALY_05000125 (0)
a413647b	164	#define ANOMALY_05000149 (0)
3bebca2d	165	#define ANOMALY_05000158 (0)
a413647b MF	166	#define ANOMALY_05000171 (0)
a413647b MF	167	#define ANOMALY_05000179 (0)
a200ad22	168	#define ANOMALY_05000182 (0)
1aafd909	169	#define ANOMALY_05000183 (0)
976119bc	170	#define ANOMALY_05000189 (0)
1aafd909	171	#define ANOMALY_05000198 (0)
a200ad22	172	#define ANOMALY_05000202 (0)
a413647b MF	173	#define ANOMALY_05000215 (0)
	174	#define ANOMALY_05000220 (0)
	175	#define ANOMALY_05000227 (0)
0174dd59	176	#define ANOMALY_05000230 (0)
a413647b MF	177	#define ANOMALY_05000231 (0)
a413647b MF	178	#define ANOMALY_05000233 (0)
a200ad22	179	#define ANOMALY_05000234 (0)
a413647b MF	180	#define ANOMALY_05000242 (0)
a413647b MF	181	#define ANOMALY_05000248 (0)
1aafd909	182	#define ANOMALY_05000266 (0)
a413647b MF	183	#define ANOMALY_05000274 (0)
a413647b MF	184	#define ANOMALY_05000287 (0)
1aafd909	185	#define ANOMALY_05000311 (0)
2b39331a	186	#define ANOMALY_05000323 (0)
4e8086d6	187	#define ANOMALY_05000353 (1)
a413647b	188	#define ANOMALY_05000362 (1)
4d555630	189	#define ANOMALY_05000363 (0)
976119bc	190	#define ANOMALY_05000364 (0)
ee554be9	191	#define ANOMALY_05000380 (0)
4e8086d6	192	#define ANOMALY_05000386 (1)
a413647b MF	193	#define ANOMALY_05000389 (0)
a413647b MF	194	#define ANOMALY_05000400 (0)
6651ece9	195	#define ANOMALY_05000412 (0)
a413647b	196	#define ANOMALY_05000430 (0)
6651ece9	197	#define ANOMALY_05000432 (0)
94b28211	198	#define ANOMALY_05000435 (0)
7dbc3f6e MF	199	#define ANOMALY_05000447 (0)
7dbc3f6e MF	200	#define ANOMALY_05000448 (0)
a413647b MF	201	#define ANOMALY_05000456 (0)
a413647b MF	202	#define ANOMALY_05000450 (0)
a200ad22 MF	203	#define ANOMALY_05000465 (0)
a200ad22 MF	204	#define ANOMALY_05000467 (0)
1aafd909 MF	205
1aafd909 MF	206	#endif