Merge tag 'ceph-for-4.7-rc8' of git://github.com/ceph/ceph-client
[deliverable/linux.git] / arch / blackfin / mach-bf537 / ints-priority.c
CommitLineData
1394f032 1/*
96f1050d 2 * Copyright 2005-2009 Analog Devices Inc.
1394f032 3 *
96f1050d 4 * Licensed under the GPL-2 or later.
1394f032 5 *
96f1050d 6 * Set up the interrupt priorities
1394f032
BW
7 */
8
9#include <linux/module.h>
1f83b8f1 10#include <linux/irq.h>
1394f032 11#include <asm/blackfin.h>
1394f032 12
f58c3276
MF
13#include <asm/irq_handler.h>
14#include <asm/bfin5xx_spi.h>
15#include <asm/bfin_sport.h>
16#include <asm/bfin_can.h>
8c054103 17#include <asm/bfin_dma.h>
f58c3276
MF
18#include <asm/dpmc.h>
19
9216bbc8 20void __init program_IAR(void)
1394f032
BW
21{
22 /* Program the IAR0 Register with the configured priority */
23 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
24 ((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) |
25 ((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) |
26 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
27 ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
28 ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
29 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
30 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS));
31
32 bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
33 ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
34 ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
35 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
36 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) |
37 ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
38 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
39 ((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
40
41 bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
42 ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
43 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
6a01f230
YL
44 ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
45 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
46 ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
47 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
48 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
1394f032 49
6a01f230
YL
50 bfin_write_SIC_IAR3(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
51 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
52 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
1394f032
BW
53 ((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
54 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
55 ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
56 ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
57 ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
58
59 SSYNC();
60}
f58c3276
MF
61
62#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
63#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
64#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
65#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
66#define UART_ERR_MASK (0x6) /* UART_IIR */
67#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
68
69static int error_int_mask;
70
71static void bf537_generic_error_mask_irq(struct irq_data *d)
72{
73 error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
74 if (!error_int_mask)
75 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
76}
77
78static void bf537_generic_error_unmask_irq(struct irq_data *d)
79{
80 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
81 error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
82}
83
84static struct irq_chip bf537_generic_error_irqchip = {
85 .name = "ERROR",
86 .irq_ack = bfin_ack_noop,
87 .irq_mask_ack = bf537_generic_error_mask_irq,
88 .irq_mask = bf537_generic_error_mask_irq,
89 .irq_unmask = bf537_generic_error_unmask_irq,
90};
91
bd0b9ac4 92static void bf537_demux_error_irq(struct irq_desc *inta_desc)
f58c3276
MF
93{
94 int irq = 0;
95
96#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
97 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
98 irq = IRQ_MAC_ERROR;
99 else
100#endif
101 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
102 irq = IRQ_SPORT0_ERROR;
103 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
104 irq = IRQ_SPORT1_ERROR;
105 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
106 irq = IRQ_PPI_ERROR;
107 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
108 irq = IRQ_CAN_ERROR;
109 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
110 irq = IRQ_SPI_ERROR;
111 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
112 irq = IRQ_UART0_ERROR;
113 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
114 irq = IRQ_UART1_ERROR;
115
116 if (irq) {
117 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
118 bfin_handle_irq(irq);
119 else {
120
121 switch (irq) {
122 case IRQ_PPI_ERROR:
123 bfin_write_PPI_STATUS(PPI_ERR_MASK);
124 break;
125#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
126 case IRQ_MAC_ERROR:
127 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
128 break;
129#endif
130 case IRQ_SPORT0_ERROR:
131 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
132 break;
133
134 case IRQ_SPORT1_ERROR:
135 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
136 break;
137
138 case IRQ_CAN_ERROR:
139 bfin_write_CAN_GIS(CAN_ERR_MASK);
140 break;
141
142 case IRQ_SPI_ERROR:
143 bfin_write_SPI_STAT(SPI_ERR_MASK);
144 break;
145
146 default:
147 break;
148 }
149
150 pr_debug("IRQ %d:"
151 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
152 irq);
153 }
154 } else
155 pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
156 __func__);
157
158}
159
8c054103
MF
160#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
161static int mac_rx_int_mask;
162
163static void bf537_mac_rx_mask_irq(struct irq_data *d)
164{
165 mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
166 if (!mac_rx_int_mask)
167 bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
168}
169
170static void bf537_mac_rx_unmask_irq(struct irq_data *d)
171{
172 bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
173 mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
174}
175
176static struct irq_chip bf537_mac_rx_irqchip = {
177 .name = "ERROR",
178 .irq_ack = bfin_ack_noop,
179 .irq_mask_ack = bf537_mac_rx_mask_irq,
180 .irq_mask = bf537_mac_rx_mask_irq,
181 .irq_unmask = bf537_mac_rx_unmask_irq,
182};
183
bd0b9ac4 184static void bf537_demux_mac_rx_irq(struct irq_desc *desc)
8c054103
MF
185{
186 if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
187 bfin_handle_irq(IRQ_MAC_RX);
188 else
bd0b9ac4 189 bfin_demux_gpio_irq(desc);
8c054103
MF
190}
191#endif
192
f58c3276
MF
193void __init init_mach_irq(void)
194{
195 int irq;
196
197#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
198 /* Clear EMAC Interrupt Status bits so we can demux it later */
199 bfin_write_EMAC_SYSTAT(-1);
200#endif
201
202 irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
203 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
204 irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
205 handle_level_irq);
206
207#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
8c054103
MF
208 irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
209 irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
210 irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
211
f58c3276
MF
212 irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
213#endif
214}
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