Commit | Line | Data |
---|---|---|
dc26aec2 MH |
1 | /* |
2 | * File: include/asm-blackfin/mach-bf538/anomaly.h | |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
4 | * | |
5 | * Copyright (C) 2004-2008 Analog Devices Inc. | |
6 | * Licensed under the GPL-2 or later. | |
7 | */ | |
8 | ||
9 | /* This file shoule be up to date with: | |
10 | * - Revision F, 06/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List | |
11 | * - Revision K, 06/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List | |
12 | */ | |
13 | ||
14 | #ifndef _MACH_ANOMALY_H_ | |
15 | #define _MACH_ANOMALY_H_ | |
16 | ||
17 | #if __SILICON_REVISION__ < 4 | |
3529e041 | 18 | # error will not work on BF538 silicon version 0.0, 0.1, 0.2, or 0.3 |
dc26aec2 MH |
19 | #endif |
20 | ||
21 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | |
22 | #define ANOMALY_05000074 (1) | |
23 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | |
24 | #define ANOMALY_05000119 (1) | |
25 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
26 | #define ANOMALY_05000122 (1) | |
27 | /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ | |
28 | #define ANOMALY_05000166 (1) | |
29 | /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ | |
30 | #define ANOMALY_05000179 (1) | |
31 | /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ | |
32 | #define ANOMALY_05000180 (1) | |
33 | /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ | |
34 | #define ANOMALY_05000193 (1) | |
35 | /* Current DMA Address Shows Wrong Value During Carry Fix */ | |
36 | #define ANOMALY_05000199 (__SILICON_REVISION__ < 4) | |
37 | /* NMI Event at Boot Time Results in Unpredictable State */ | |
38 | #define ANOMALY_05000219 (1) | |
39 | /* SPI Slave Boot Mode Modifies Registers from Reset Value */ | |
40 | #define ANOMALY_05000229 (1) | |
41 | /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ | |
42 | #define ANOMALY_05000233 (1) | |
43 | /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */ | |
44 | #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) | |
45 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
46 | #define ANOMALY_05000245 (1) | |
47 | /* Maximum External Clock Speed for Timers */ | |
48 | #define ANOMALY_05000253 (1) | |
49 | /* DCPLB_FAULT_ADDR MMR register may be corrupted */ | |
50 | #define ANOMALY_05000261 (__SILICON_REVISION__ < 3) | |
51 | /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ | |
52 | #define ANOMALY_05000270 (__SILICON_REVISION__ < 4) | |
53 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | |
54 | #define ANOMALY_05000272 (1) | |
55 | /* Writes to Synchronous SDRAM Memory May Be Lost */ | |
56 | #define ANOMALY_05000273 (__SILICON_REVISION__ < 4) | |
57 | /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ | |
58 | #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) | |
59 | /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ | |
60 | #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) | |
61 | /* False Hardware Error Exception when ISR Context Is Not Restored */ | |
62 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) | |
63 | /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ | |
64 | #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) | |
65 | /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ | |
66 | #define ANOMALY_05000283 (__SILICON_REVISION__ < 4) | |
67 | /* SPORTs May Receive Bad Data If FIFOs Fill Up */ | |
68 | #define ANOMALY_05000288 (__SILICON_REVISION__ < 4) | |
69 | /* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */ | |
70 | #define ANOMALY_05000291 (__SILICON_REVISION__ < 4) | |
71 | /* Hibernate Leakage Current Is Higher Than Specified */ | |
72 | #define ANOMALY_05000293 (__SILICON_REVISION__ < 4) | |
73 | /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ | |
74 | #define ANOMALY_05000294 (1) | |
75 | /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ | |
76 | #define ANOMALY_05000301 (__SILICON_REVISION__ < 4) | |
77 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ | |
78 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 4) | |
79 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ | |
80 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 4) | |
81 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | |
82 | #define ANOMALY_05000310 (1) | |
83 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | |
84 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 5) | |
85 | /* PPI Is Level-Sensitive on First Transfer */ | |
86 | #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) | |
87 | /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ | |
88 | #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) | |
89 | /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ | |
90 | #define ANOMALY_05000318 (__SILICON_REVISION__ < 4) | |
91 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | |
92 | #define ANOMALY_05000355 (__SILICON_REVISION__ < 5) | |
93 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | |
94 | #define ANOMALY_05000357 (__SILICON_REVISION__ < 5) | |
95 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | |
96 | #define ANOMALY_05000366 (1) | |
97 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | |
98 | #define ANOMALY_05000371 (__SILICON_REVISION__ < 5) | |
99 | /* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */ | |
100 | #define ANOMALY_05000374 (__SILICON_REVISION__ == 4) | |
101 | /* New Feature: Open-Drain GPIO Outputs on PC1 and PC4 (Not Available on Older Silicon) */ | |
102 | #define ANOMALY_05000375 (__SILICON_REVISION__ < 4) | |
103 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | |
104 | #define ANOMALY_05000402 (__SILICON_REVISION__ < 4) | |
105 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | |
106 | #define ANOMALY_05000403 (1) | |
107 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | |
108 | #define ANOMALY_05000416 (1) | |
3529e041 MF |
109 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
110 | #define ANOMALY_05000443 (1) | |
dc26aec2 MH |
111 | |
112 | /* Anomalies that don't exist on this proc */ | |
dc26aec2 | 113 | #define ANOMALY_05000158 (0) |
3529e041 MF |
114 | #define ANOMALY_05000198 (0) |
115 | #define ANOMALY_05000230 (0) | |
116 | #define ANOMALY_05000263 (0) | |
dc26aec2 MH |
117 | #define ANOMALY_05000311 (0) |
118 | #define ANOMALY_05000323 (0) | |
3529e041 | 119 | #define ANOMALY_05000353 (1) |
dc26aec2 | 120 | #define ANOMALY_05000363 (0) |
3529e041 | 121 | #define ANOMALY_05000386 (1) |
94b28211 | 122 | #define ANOMALY_05000435 (0) |
dc26aec2 MH |
123 | |
124 | #endif |