projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| dc26aec2 MH |
1 | /* |
| 2 | * File: include/asm-blackfin/mach-bf538/blackfin.h | |
| 3 | * Based on: | |
| 4 | * Author: | |
| 5 | * | |
| 6 | * Created: | |
| 7 | * Description: | |
| 8 | * | |
| 9 | * Rev: | |
| 10 | * | |
| 11 | * Modified: | |
| 12 | * | |
| 13 | * | |
| 14 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
| 15 | * | |
| 16 | * This program is free software; you can redistribute it and/or modify | |
| 17 | * it under the terms of the GNU General Public License as published by | |
| 18 | * the Free Software Foundation; either version 2, or (at your option) | |
| 19 | * any later version. | |
| 20 | * | |
| 21 | * This program is distributed in the hope that it will be useful, | |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 24 | * GNU General Public License for more details. | |
| 25 | * | |
| 26 | * You should have received a copy of the GNU General Public License | |
| 27 | * along with this program; see the file COPYING. | |
| 28 | * If not, write to the Free Software Foundation, | |
| 29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
| 30 | */ | |
| 31 | ||
| 32 | #ifndef _MACH_BLACKFIN_H_ | |
| 33 | #define _MACH_BLACKFIN_H_ | |
| 34 | ||
| 35 | #define BF538_FAMILY | |
| 36 | ||
| 37 | #include "bf538.h" | |
| dc26aec2 MH |
38 | #include "defBF539.h" |
| 39 | #include "anomaly.h" | |
| 40 | ||
| 41 | ||
| 42 | #if !defined(__ASSEMBLY__) | |
| 43 | #include "cdefBF538.h" | |
| 44 | ||
| 45 | #if defined(CONFIG_BF539) | |
| 46 | #include "cdefBF539.h" | |
| 47 | #endif | |
| 48 | #endif | |
| 49 | ||
| dc26aec2 MH |
50 | #define BFIN_UART_NR_PORTS 3 |
| 51 | ||
| 52 | #define OFFSET_THR 0x00 /* Transmit Holding register */ | |
| 53 | #define OFFSET_RBR 0x00 /* Receive Buffer register */ | |
| 54 | #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ | |
| 55 | #define OFFSET_IER 0x04 /* Interrupt Enable Register */ | |
| 56 | #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ | |
| 57 | #define OFFSET_IIR 0x08 /* Interrupt Identification Register */ | |
| 58 | #define OFFSET_LCR 0x0C /* Line Control Register */ | |
| 59 | #define OFFSET_MCR 0x10 /* Modem Control Register */ | |
| 60 | #define OFFSET_LSR 0x14 /* Line Status Register */ | |
| 61 | #define OFFSET_MSR 0x18 /* Modem Status Register */ | |
| 62 | #define OFFSET_SCR 0x1C /* SCR Scratch Register */ | |
| 63 | #define OFFSET_GCTL 0x24 /* Global Control Register */ | |
| 64 | ||
| dc26aec2 MH |
65 | /* PLL_DIV Masks */ |
| 66 | #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ | |
| 67 | #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ | |
| 68 | #define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ | |
| 69 | #define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ | |
| 70 | ||
| 71 | #endif |