Commit | Line | Data |
---|---|---|
088eec11 | 1 | /* |
287050fe MF |
2 | * File: include/asm-blackfin/mach-bf548/anomaly.h |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
088eec11 | 4 | * |
c18e99cf | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
287050fe | 6 | * Licensed under the GPL-2 or later. |
088eec11 RH |
7 | */ |
8 | ||
a413647b | 9 | /* This file should be up to date with: |
bd411b15 | 10 | * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List |
1aafd909 MF |
11 | */ |
12 | ||
088eec11 RH |
13 | #ifndef _MACH_ANOMALY_H_ |
14 | #define _MACH_ANOMALY_H_ | |
287050fe | 15 | |
a413647b MF |
16 | /* We do not support 0.0 or 0.1 silicon - sorry */ |
17 | #if __SILICON_REVISION__ < 2 | |
18 | # error will not work on BF548 silicon version 0.0, or 0.1 | |
19 | #endif | |
20 | ||
a200ad22 | 21 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
1aafd909 MF |
22 | #define ANOMALY_05000074 (1) |
23 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | |
24 | #define ANOMALY_05000119 (1) | |
25 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
26 | #define ANOMALY_05000122 (1) | |
a413647b | 27 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
1aafd909 | 28 | #define ANOMALY_05000245 (1) |
1aafd909 MF |
29 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
30 | #define ANOMALY_05000265 (1) | |
31 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | |
32 | #define ANOMALY_05000272 (1) | |
a200ad22 | 33 | /* False Hardware Error Exception when ISR Context Is Not Restored */ |
7cc1c4b2 | 34 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 35 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ |
7cc1c4b2 | 36 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) |
1aafd909 MF |
37 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
38 | #define ANOMALY_05000310 (1) | |
a200ad22 | 39 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
7cc1c4b2 | 40 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) |
1aafd909 | 41 | /* TWI Slave Boot Mode Is Not Functional */ |
7cc1c4b2 | 42 | #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) |
a200ad22 | 43 | /* FIFO Boot Mode Not Functional */ |
4e8086d6 | 44 | #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) |
1aafd909 | 45 | /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ |
7cc1c4b2 | 46 | #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) |
1aafd909 | 47 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
7cc1c4b2 | 48 | #define ANOMALY_05000328 (__SILICON_REVISION__ < 1) |
1aafd909 | 49 | /* Synchronous Burst Flash Boot Mode Is Not Functional */ |
7cc1c4b2 | 50 | #define ANOMALY_05000329 (__SILICON_REVISION__ < 1) |
4e8086d6 | 51 | /* Host DMA Boot Modes Are Not Functional */ |
7cc1c4b2 | 52 | #define ANOMALY_05000330 (__SILICON_REVISION__ < 1) |
1aafd909 | 53 | /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ |
7cc1c4b2 | 54 | #define ANOMALY_05000334 (__SILICON_REVISION__ < 1) |
1aafd909 | 55 | /* Inadequate Rotary Debounce Logic Duration */ |
7cc1c4b2 | 56 | #define ANOMALY_05000335 (__SILICON_REVISION__ < 1) |
1aafd909 | 57 | /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ |
7cc1c4b2 | 58 | #define ANOMALY_05000336 (__SILICON_REVISION__ < 1) |
1aafd909 | 59 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ |
7cc1c4b2 | 60 | #define ANOMALY_05000337 (__SILICON_REVISION__ < 1) |
1aafd909 | 61 | /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ |
7cc1c4b2 | 62 | #define ANOMALY_05000338 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 63 | /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ |
7cc1c4b2 | 64 | #define ANOMALY_05000340 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 65 | /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ |
7cc1c4b2 | 66 | #define ANOMALY_05000344 (__SILICON_REVISION__ < 1) |
a413647b | 67 | /* USB Calibration Value Is Not Initialized */ |
7cc1c4b2 | 68 | #define ANOMALY_05000346 (__SILICON_REVISION__ < 1) |
202d7bd9 RG |
69 | /* USB Calibration Value to use */ |
70 | #define ANOMALY_05000346_value 0x5411 | |
4e8086d6 | 71 | /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ |
7cc1c4b2 | 72 | #define ANOMALY_05000347 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 73 | /* Data Lost when Core Reads SDH Data FIFO */ |
7cc1c4b2 | 74 | #define ANOMALY_05000349 (__SILICON_REVISION__ < 1) |
bc8c84c9 | 75 | /* PLL Status Register Is Inaccurate */ |
7cc1c4b2 | 76 | #define ANOMALY_05000351 (__SILICON_REVISION__ < 1) |
4e8086d6 MF |
77 | /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ |
78 | #define ANOMALY_05000353 (__SILICON_REVISION__ < 2) | |
79 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | |
80 | #define ANOMALY_05000355 (__SILICON_REVISION__ < 1) | |
81 | /* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ | |
82 | #define ANOMALY_05000356 (__SILICON_REVISION__ < 1) | |
7cc1c4b2 MF |
83 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
84 | #define ANOMALY_05000357 (1) | |
85 | /* External Memory Read Access Hangs Core With PLL Bypass */ | |
86 | #define ANOMALY_05000360 (1) | |
87 | /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ | |
88 | #define ANOMALY_05000365 (1) | |
4e8086d6 MF |
89 | /* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ |
90 | #define ANOMALY_05000367 (__SILICON_REVISION__ < 1) | |
7cc1c4b2 MF |
91 | /* Addressing Conflict between Boot ROM and Asynchronous Memory */ |
92 | #define ANOMALY_05000369 (1) | |
4e8086d6 MF |
93 | /* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ |
94 | #define ANOMALY_05000370 (__SILICON_REVISION__ < 1) | |
a70ce072 | 95 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
4e8086d6 MF |
96 | #define ANOMALY_05000371 (__SILICON_REVISION__ < 2) |
97 | /* USB DP/DM Data Pins May Lose State When Entering Hibernate */ | |
98 | #define ANOMALY_05000372 (__SILICON_REVISION__ < 1) | |
7cc1c4b2 | 99 | /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ |
4e8086d6 MF |
100 | #define ANOMALY_05000378 (__SILICON_REVISION__ < 2) |
101 | /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ | |
102 | #define ANOMALY_05000379 (1) | |
103 | /* 8-Bit NAND Flash Boot Mode Not Functional */ | |
104 | #define ANOMALY_05000382 (__SILICON_REVISION__ < 1) | |
105 | /* Some ATAPI Modes Are Not Functional */ | |
106 | #define ANOMALY_05000383 (1) | |
107 | /* Boot from OTP Memory Not Functional */ | |
108 | #define ANOMALY_05000385 (__SILICON_REVISION__ < 1) | |
109 | /* bfrom_SysControl() Firmware Routine Not Functional */ | |
110 | #define ANOMALY_05000386 (__SILICON_REVISION__ < 1) | |
111 | /* Programmable Preboot Settings Not Functional */ | |
112 | #define ANOMALY_05000387 (__SILICON_REVISION__ < 1) | |
113 | /* CRC32 Checksum Support Not Functional */ | |
114 | #define ANOMALY_05000388 (__SILICON_REVISION__ < 1) | |
115 | /* Reset Vector Must Not Be in SDRAM Memory Space */ | |
116 | #define ANOMALY_05000389 (__SILICON_REVISION__ < 1) | |
117 | /* Changed Meaning of BCODE Field in SYSCR Register */ | |
118 | #define ANOMALY_05000390 (__SILICON_REVISION__ < 1) | |
119 | /* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ | |
120 | #define ANOMALY_05000391 (__SILICON_REVISION__ < 1) | |
121 | /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ | |
122 | #define ANOMALY_05000392 (__SILICON_REVISION__ < 1) | |
123 | /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ | |
124 | #define ANOMALY_05000393 (__SILICON_REVISION__ < 1) | |
125 | /* Log Buffer Not Functional */ | |
126 | #define ANOMALY_05000394 (__SILICON_REVISION__ < 1) | |
127 | /* Hook Routine Not Functional */ | |
128 | #define ANOMALY_05000395 (__SILICON_REVISION__ < 1) | |
129 | /* Header Indirect Bit Not Functional */ | |
130 | #define ANOMALY_05000396 (__SILICON_REVISION__ < 1) | |
131 | /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ | |
132 | #define ANOMALY_05000397 (__SILICON_REVISION__ < 1) | |
133 | /* Lockbox SESR Disallows Certain User Interrupts */ | |
134 | #define ANOMALY_05000404 (__SILICON_REVISION__ < 2) | |
135 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ | |
136 | #define ANOMALY_05000405 (1) | |
137 | /* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */ | |
138 | #define ANOMALY_05000406 (__SILICON_REVISION__ < 2) | |
139 | /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ | |
140 | #define ANOMALY_05000407 (__SILICON_REVISION__ < 2) | |
141 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ | |
142 | #define ANOMALY_05000408 (1) | |
143 | /* Lockbox firmware leaves MDMA0 channel enabled */ | |
144 | #define ANOMALY_05000409 (__SILICON_REVISION__ < 2) | |
145 | /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ | |
146 | #define ANOMALY_05000411 (__SILICON_REVISION__ < 2) | |
147 | /* NAND Boot Mode Not Compatible With Some NAND Flash Devices */ | |
148 | #define ANOMALY_05000413 (__SILICON_REVISION__ < 2) | |
149 | /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ | |
150 | #define ANOMALY_05000414 (__SILICON_REVISION__ < 2) | |
151 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | |
152 | #define ANOMALY_05000416 (1) | |
153 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ | |
154 | #define ANOMALY_05000425 (1) | |
a413647b | 155 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ |
4e8086d6 MF |
156 | #define ANOMALY_05000426 (1) |
157 | /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ | |
158 | #define ANOMALY_05000427 (__SILICON_REVISION__ < 2) | |
a413647b | 159 | /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ |
4e8086d6 MF |
160 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) |
161 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ | |
162 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) | |
c18e99cf MF |
163 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ |
164 | #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) | |
bd411b15 YL |
165 | /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ |
166 | #define ANOMALY_05000434 (1) | |
c18e99cf MF |
167 | /* OTP Write Accesses Not Supported */ |
168 | #define ANOMALY_05000442 (__SILICON_REVISION__ < 1) | |
3529e041 MF |
169 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
170 | #define ANOMALY_05000443 (1) | |
c18e99cf MF |
171 | /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ |
172 | #define ANOMALY_05000446 (1) | |
173 | /* UART IrDA Receiver Fails on Extended Bit Pulses */ | |
174 | #define ANOMALY_05000447 (1) | |
175 | /* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */ | |
176 | #define ANOMALY_05000448 (__SILICON_REVISION__ == 1) | |
177 | /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ | |
178 | #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) | |
179 | /* USB DMA Mode 1 Short Packet Data Corruption */ | |
a413647b | 180 | #define ANOMALY_05000450 (1) |
bd411b15 YL |
181 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ |
182 | #define ANOMALY_05000452 (__SILICON_REVISION__ < 1) | |
a413647b | 183 | /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ |
bd411b15 YL |
184 | #define ANOMALY_05000456 (1) |
185 | /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ | |
186 | #define ANOMALY_05000457 (1) | |
187 | /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ | |
188 | #define ANOMALY_05000460 (1) | |
a200ad22 | 189 | /* False Hardware Error when RETI Points to Invalid Memory */ |
a413647b | 190 | #define ANOMALY_05000461 (1) |
bd411b15 YL |
191 | /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ |
192 | #define ANOMALY_05000462 (1) | |
193 | /* USB DMA RX Data Corruption */ | |
194 | #define ANOMALY_05000463 (1) | |
195 | /* USB TX DMA Hang */ | |
196 | #define ANOMALY_05000464 (1) | |
a200ad22 MF |
197 | /* USB Rx DMA hang */ |
198 | #define ANOMALY_05000465 (1) | |
bd411b15 YL |
199 | /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ |
200 | #define ANOMALY_05000466 (1) | |
a200ad22 MF |
201 | /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ |
202 | #define ANOMALY_05000467 (1) | |
1aafd909 MF |
203 | |
204 | /* Anomalies that don't exist on this proc */ | |
a413647b MF |
205 | #define ANOMALY_05000099 (0) |
206 | #define ANOMALY_05000120 (0) | |
1aafd909 | 207 | #define ANOMALY_05000125 (0) |
a413647b | 208 | #define ANOMALY_05000149 (0) |
2cbfe107 | 209 | #define ANOMALY_05000158 (0) |
a413647b MF |
210 | #define ANOMALY_05000171 (0) |
211 | #define ANOMALY_05000179 (0) | |
a200ad22 | 212 | #define ANOMALY_05000182 (0) |
1aafd909 | 213 | #define ANOMALY_05000183 (0) |
976119bc | 214 | #define ANOMALY_05000189 (0) |
1aafd909 | 215 | #define ANOMALY_05000198 (0) |
a200ad22 | 216 | #define ANOMALY_05000202 (0) |
a413647b MF |
217 | #define ANOMALY_05000215 (0) |
218 | #define ANOMALY_05000220 (0) | |
219 | #define ANOMALY_05000227 (0) | |
0174dd59 | 220 | #define ANOMALY_05000230 (0) |
a413647b MF |
221 | #define ANOMALY_05000231 (0) |
222 | #define ANOMALY_05000233 (0) | |
a200ad22 | 223 | #define ANOMALY_05000234 (0) |
a413647b | 224 | #define ANOMALY_05000242 (0) |
1aafd909 | 225 | #define ANOMALY_05000244 (0) |
a413647b MF |
226 | #define ANOMALY_05000248 (0) |
227 | #define ANOMALY_05000250 (0) | |
228 | #define ANOMALY_05000254 (0) | |
a200ad22 | 229 | #define ANOMALY_05000257 (0) |
60e9356d | 230 | #define ANOMALY_05000261 (0) |
1aafd909 MF |
231 | #define ANOMALY_05000263 (0) |
232 | #define ANOMALY_05000266 (0) | |
233 | #define ANOMALY_05000273 (0) | |
a413647b | 234 | #define ANOMALY_05000274 (0) |
ee554be9 | 235 | #define ANOMALY_05000278 (0) |
a200ad22 | 236 | #define ANOMALY_05000283 (0) |
a413647b MF |
237 | #define ANOMALY_05000287 (0) |
238 | #define ANOMALY_05000301 (0) | |
c18e99cf | 239 | #define ANOMALY_05000305 (0) |
4e8086d6 | 240 | #define ANOMALY_05000307 (0) |
1aafd909 | 241 | #define ANOMALY_05000311 (0) |
a200ad22 | 242 | #define ANOMALY_05000315 (0) |
2b39331a | 243 | #define ANOMALY_05000323 (0) |
a413647b | 244 | #define ANOMALY_05000362 (1) |
4d555630 | 245 | #define ANOMALY_05000363 (0) |
976119bc | 246 | #define ANOMALY_05000364 (0) |
1c302b6c | 247 | #define ANOMALY_05000380 (0) |
a413647b | 248 | #define ANOMALY_05000400 (0) |
bd411b15 | 249 | #define ANOMALY_05000402 (0) |
6651ece9 MF |
250 | #define ANOMALY_05000412 (0) |
251 | #define ANOMALY_05000432 (0) | |
94b28211 | 252 | #define ANOMALY_05000435 (0) |
088eec11 | 253 | |
1aafd909 | 254 | #endif |