projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 088eec11 | 1 | /* |
| 287050fe MF |
2 | * File: include/asm-blackfin/mach-bf548/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
| 088eec11 | 4 | * |
| 4e8086d6 | 5 | * Copyright (C) 2004-2008 Analog Devices Inc. |
| 287050fe | 6 | * Licensed under the GPL-2 or later. |
| 088eec11 RH |
7 | */ |
| 8 | ||
| 1aafd909 | 9 | /* This file shoule be up to date with: |
| 4e8086d6 | 10 | * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List |
| 1aafd909 MF |
11 | */ |
| 12 | ||
| 088eec11 RH |
13 | #ifndef _MACH_ANOMALY_H_ |
| 14 | #define _MACH_ANOMALY_H_ | |
| 287050fe | 15 | |
| 4e8086d6 | 16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
| 1aafd909 MF |
17 | #define ANOMALY_05000074 (1) |
| 18 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | |
| 19 | #define ANOMALY_05000119 (1) | |
| 20 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | |
| 21 | #define ANOMALY_05000122 (1) | |
| 22 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | |
| 23 | #define ANOMALY_05000245 (1) | |
| 1aafd909 MF |
24 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 25 | #define ANOMALY_05000265 (1) | |
| 26 | /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ | |
| 27 | #define ANOMALY_05000272 (1) | |
| 60e9356d | 28 | /* False Hardware Error Exception when ISR context is not restored */ |
| 7cc1c4b2 | 29 | #define ANOMALY_05000281 (__SILICON_REVISION__ < 1) |
| bc8c84c9 | 30 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ |
| 7cc1c4b2 | 31 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 1) |
| 1aafd909 MF |
32 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| 33 | #define ANOMALY_05000310 (1) | |
| 34 | /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | |
| 7cc1c4b2 | 35 | #define ANOMALY_05000312 (__SILICON_REVISION__ < 1) |
| 1aafd909 | 36 | /* TWI Slave Boot Mode Is Not Functional */ |
| 7cc1c4b2 | 37 | #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) |
| 1aafd909 | 38 | /* External FIFO Boot Mode Is Not Functional */ |
| 4e8086d6 | 39 | #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) |
| 1aafd909 | 40 | /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ |
| 7cc1c4b2 | 41 | #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) |
| 1aafd909 | 42 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
| 7cc1c4b2 | 43 | #define ANOMALY_05000328 (__SILICON_REVISION__ < 1) |
| 1aafd909 | 44 | /* Synchronous Burst Flash Boot Mode Is Not Functional */ |
| 7cc1c4b2 | 45 | #define ANOMALY_05000329 (__SILICON_REVISION__ < 1) |
| 4e8086d6 | 46 | /* Host DMA Boot Modes Are Not Functional */ |
| 7cc1c4b2 | 47 | #define ANOMALY_05000330 (__SILICON_REVISION__ < 1) |
| 1aafd909 | 48 | /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ |
| 7cc1c4b2 | 49 | #define ANOMALY_05000334 (__SILICON_REVISION__ < 1) |
| 1aafd909 | 50 | /* Inadequate Rotary Debounce Logic Duration */ |
| 7cc1c4b2 | 51 | #define ANOMALY_05000335 (__SILICON_REVISION__ < 1) |
| 1aafd909 | 52 | /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ |
| 7cc1c4b2 | 53 | #define ANOMALY_05000336 (__SILICON_REVISION__ < 1) |
| 1aafd909 | 54 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ |
| 7cc1c4b2 | 55 | #define ANOMALY_05000337 (__SILICON_REVISION__ < 1) |
| 1aafd909 | 56 | /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ |
| 7cc1c4b2 | 57 | #define ANOMALY_05000338 (__SILICON_REVISION__ < 1) |
| bc8c84c9 | 58 | /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ |
| 7cc1c4b2 | 59 | #define ANOMALY_05000340 (__SILICON_REVISION__ < 1) |
| bc8c84c9 | 60 | /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ |
| 7cc1c4b2 | 61 | #define ANOMALY_05000344 (__SILICON_REVISION__ < 1) |
| bc8c84c9 | 62 | /* USB Calibration Value Is Not Intialized */ |
| 7cc1c4b2 | 63 | #define ANOMALY_05000346 (__SILICON_REVISION__ < 1) |
| 202d7bd9 RG |
64 | /* USB Calibration Value to use */ |
| 65 | #define ANOMALY_05000346_value 0x5411 | |
| 4e8086d6 | 66 | /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ |
| 7cc1c4b2 | 67 | #define ANOMALY_05000347 (__SILICON_REVISION__ < 1) |
| bc8c84c9 | 68 | /* Data Lost when Core Reads SDH Data FIFO */ |
| 7cc1c4b2 | 69 | #define ANOMALY_05000349 (__SILICON_REVISION__ < 1) |
| bc8c84c9 | 70 | /* PLL Status Register Is Inaccurate */ |
| 7cc1c4b2 | 71 | #define ANOMALY_05000351 (__SILICON_REVISION__ < 1) |
| 4e8086d6 MF |
72 | /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ |
| 73 | #define ANOMALY_05000353 (__SILICON_REVISION__ < 2) | |
| 74 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | |
| 75 | #define ANOMALY_05000355 (__SILICON_REVISION__ < 1) | |
| 76 | /* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ | |
| 77 | #define ANOMALY_05000356 (__SILICON_REVISION__ < 1) | |
| 7cc1c4b2 MF |
78 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
| 79 | #define ANOMALY_05000357 (1) | |
| 80 | /* External Memory Read Access Hangs Core With PLL Bypass */ | |
| 81 | #define ANOMALY_05000360 (1) | |
| 82 | /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ | |
| 83 | #define ANOMALY_05000365 (1) | |
| 4e8086d6 MF |
84 | /* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ |
| 85 | #define ANOMALY_05000367 (__SILICON_REVISION__ < 1) | |
| 7cc1c4b2 MF |
86 | /* Addressing Conflict between Boot ROM and Asynchronous Memory */ |
| 87 | #define ANOMALY_05000369 (1) | |
| 4e8086d6 MF |
88 | /* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ |
| 89 | #define ANOMALY_05000370 (__SILICON_REVISION__ < 1) | |
| a70ce072 | 90 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
| 4e8086d6 MF |
91 | #define ANOMALY_05000371 (__SILICON_REVISION__ < 2) |
| 92 | /* USB DP/DM Data Pins May Lose State When Entering Hibernate */ | |
| 93 | #define ANOMALY_05000372 (__SILICON_REVISION__ < 1) | |
| 7cc1c4b2 MF |
94 | /* Mobile DDR Operation Not Functional */ |
| 95 | #define ANOMALY_05000377 (1) | |
| 96 | /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ | |
| 4e8086d6 MF |
97 | #define ANOMALY_05000378 (__SILICON_REVISION__ < 2) |
| 98 | /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ | |
| 99 | #define ANOMALY_05000379 (1) | |
| 100 | /* 8-Bit NAND Flash Boot Mode Not Functional */ | |
| 101 | #define ANOMALY_05000382 (__SILICON_REVISION__ < 1) | |
| 102 | /* Some ATAPI Modes Are Not Functional */ | |
| 103 | #define ANOMALY_05000383 (1) | |
| 104 | /* Boot from OTP Memory Not Functional */ | |
| 105 | #define ANOMALY_05000385 (__SILICON_REVISION__ < 1) | |
| 106 | /* bfrom_SysControl() Firmware Routine Not Functional */ | |
| 107 | #define ANOMALY_05000386 (__SILICON_REVISION__ < 1) | |
| 108 | /* Programmable Preboot Settings Not Functional */ | |
| 109 | #define ANOMALY_05000387 (__SILICON_REVISION__ < 1) | |
| 110 | /* CRC32 Checksum Support Not Functional */ | |
| 111 | #define ANOMALY_05000388 (__SILICON_REVISION__ < 1) | |
| 112 | /* Reset Vector Must Not Be in SDRAM Memory Space */ | |
| 113 | #define ANOMALY_05000389 (__SILICON_REVISION__ < 1) | |
| 114 | /* Changed Meaning of BCODE Field in SYSCR Register */ | |
| 115 | #define ANOMALY_05000390 (__SILICON_REVISION__ < 1) | |
| 116 | /* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ | |
| 117 | #define ANOMALY_05000391 (__SILICON_REVISION__ < 1) | |
| 118 | /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ | |
| 119 | #define ANOMALY_05000392 (__SILICON_REVISION__ < 1) | |
| 120 | /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ | |
| 121 | #define ANOMALY_05000393 (__SILICON_REVISION__ < 1) | |
| 122 | /* Log Buffer Not Functional */ | |
| 123 | #define ANOMALY_05000394 (__SILICON_REVISION__ < 1) | |
| 124 | /* Hook Routine Not Functional */ | |
| 125 | #define ANOMALY_05000395 (__SILICON_REVISION__ < 1) | |
| 126 | /* Header Indirect Bit Not Functional */ | |
| 127 | #define ANOMALY_05000396 (__SILICON_REVISION__ < 1) | |
| 128 | /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ | |
| 129 | #define ANOMALY_05000397 (__SILICON_REVISION__ < 1) | |
| 130 | /* Lockbox SESR Disallows Certain User Interrupts */ | |
| 131 | #define ANOMALY_05000404 (__SILICON_REVISION__ < 2) | |
| 132 | /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ | |
| 133 | #define ANOMALY_05000405 (1) | |
| 134 | /* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */ | |
| 135 | #define ANOMALY_05000406 (__SILICON_REVISION__ < 2) | |
| 136 | /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ | |
| 137 | #define ANOMALY_05000407 (__SILICON_REVISION__ < 2) | |
| 138 | /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ | |
| 139 | #define ANOMALY_05000408 (1) | |
| 140 | /* Lockbox firmware leaves MDMA0 channel enabled */ | |
| 141 | #define ANOMALY_05000409 (__SILICON_REVISION__ < 2) | |
| 142 | /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ | |
| 143 | #define ANOMALY_05000411 (__SILICON_REVISION__ < 2) | |
| 144 | /* NAND Boot Mode Not Compatible With Some NAND Flash Devices */ | |
| 145 | #define ANOMALY_05000413 (__SILICON_REVISION__ < 2) | |
| 146 | /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ | |
| 147 | #define ANOMALY_05000414 (__SILICON_REVISION__ < 2) | |
| 148 | /* Speculative Fetches Can Cause Undesired External FIFO Operations */ | |
| 149 | #define ANOMALY_05000416 (1) | |
| 150 | /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ | |
| 151 | #define ANOMALY_05000425 (1) | |
| 152 | /* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ | |
| 153 | #define ANOMALY_05000426 (1) | |
| 154 | /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ | |
| 155 | #define ANOMALY_05000427 (__SILICON_REVISION__ < 2) | |
| 156 | /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */ | |
| 157 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) | |
| 158 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ | |
| 159 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) | |
| 3529e041 MF |
160 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 161 | #define ANOMALY_05000443 (1) | |
| 1aafd909 MF |
162 | |
| 163 | /* Anomalies that don't exist on this proc */ | |
| 164 | #define ANOMALY_05000125 (0) | |
| 2cbfe107 | 165 | #define ANOMALY_05000158 (0) |
| 1aafd909 MF |
166 | #define ANOMALY_05000183 (0) |
| 167 | #define ANOMALY_05000198 (0) | |
| 0174dd59 | 168 | #define ANOMALY_05000230 (0) |
| 1aafd909 | 169 | #define ANOMALY_05000244 (0) |
| 60e9356d | 170 | #define ANOMALY_05000261 (0) |
| 1aafd909 MF |
171 | #define ANOMALY_05000263 (0) |
| 172 | #define ANOMALY_05000266 (0) | |
| 173 | #define ANOMALY_05000273 (0) | |
| 4e8086d6 | 174 | #define ANOMALY_05000307 (0) |
| 1aafd909 | 175 | #define ANOMALY_05000311 (0) |
| 2b39331a | 176 | #define ANOMALY_05000323 (0) |
| 4d555630 | 177 | #define ANOMALY_05000363 (0) |
| 6651ece9 MF |
178 | #define ANOMALY_05000412 (0) |
| 179 | #define ANOMALY_05000432 (0) | |
| 94b28211 | 180 | #define ANOMALY_05000435 (0) |
| 088eec11 | 181 | |
| 1aafd909 | 182 | #endif |