Commit | Line | Data |
---|---|---|
19381f02 | 1 | /* |
96f1050d | 2 | * Copyright 2007-2008 Analog Devices Inc. |
19381f02 | 3 | * |
96f1050d | 4 | * Licensed under the GPL-2 or later. |
19381f02 BW |
5 | */ |
6 | ||
7 | #ifndef _CDEF_BF54X_H | |
8 | #define _CDEF_BF54X_H | |
9 | ||
36a1548f MF |
10 | #include <asm/blackfin.h> |
11 | ||
24a07a12 | 12 | #include "defBF54x_base.h" |
19381f02 BW |
13 | |
14 | /* ************************************************************** */ | |
15 | /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ | |
16 | /* ************************************************************** */ | |
17 | ||
18 | /* PLL Registers */ | |
19 | ||
20 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) | |
19381f02 BW |
21 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
22 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) | |
23 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) | |
19381f02 BW |
24 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
25 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) | |
26 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) | |
27 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) | |
28 | ||
29 | /* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ | |
30 | ||
31 | #define bfin_read_CHIPID() bfin_read32(CHIPID) | |
32 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) | |
33 | ||
34 | /* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */ | |
35 | ||
36 | #define bfin_read_SWRST() bfin_read16(SWRST) | |
37 | #define bfin_write_SWRST(val) bfin_write16(SWRST, val) | |
38 | #define bfin_read_SYSCR() bfin_read16(SYSCR) | |
39 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) | |
40 | ||
41 | /* SIC Registers */ | |
42 | ||
43 | #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) | |
44 | #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) | |
45 | #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) | |
46 | #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) | |
47 | #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) | |
48 | #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) | |
24a07a12 RH |
49 | #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2)) |
50 | #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val) | |
51 | ||
19381f02 BW |
52 | #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) |
53 | #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) | |
54 | #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) | |
55 | #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) | |
56 | #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) | |
57 | #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) | |
24a07a12 RH |
58 | #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2)) |
59 | #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val) | |
60 | ||
19381f02 BW |
61 | #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) |
62 | #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) | |
63 | #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) | |
64 | #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) | |
65 | #define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) | |
66 | #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) | |
67 | #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) | |
68 | #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) | |
69 | #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) | |
70 | #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) | |
71 | #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) | |
72 | #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) | |
73 | #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) | |
74 | #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) | |
75 | #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) | |
76 | #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) | |
77 | #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) | |
78 | #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) | |
79 | #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) | |
80 | #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) | |
81 | #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) | |
82 | #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) | |
83 | #define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) | |
84 | #define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) | |
85 | #define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) | |
86 | #define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) | |
87 | #define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) | |
88 | #define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) | |
89 | #define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) | |
90 | #define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) | |
91 | ||
92 | /* Watchdog Timer Registers */ | |
93 | ||
94 | #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) | |
95 | #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) | |
96 | #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) | |
97 | #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) | |
98 | #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) | |
99 | #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) | |
100 | ||
101 | /* RTC Registers */ | |
102 | ||
103 | #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) | |
104 | #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) | |
105 | #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) | |
106 | #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) | |
107 | #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) | |
108 | #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) | |
109 | #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) | |
110 | #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) | |
111 | #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) | |
112 | #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) | |
113 | #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) | |
114 | #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) | |
115 | ||
116 | /* UART0 Registers */ | |
117 | ||
118 | #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) | |
119 | #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) | |
120 | #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) | |
121 | #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) | |
122 | #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) | |
123 | #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) | |
124 | #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) | |
125 | #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) | |
126 | #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) | |
127 | #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) | |
128 | #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) | |
129 | #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) | |
130 | #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) | |
131 | #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) | |
132 | #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) | |
133 | #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) | |
134 | #define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) | |
135 | #define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) | |
136 | #define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) | |
137 | #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) | |
138 | #define bfin_read_UART0_THR() bfin_read16(UART0_THR) | |
139 | #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) | |
140 | #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) | |
141 | #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) | |
142 | ||
143 | /* SPI0 Registers */ | |
144 | ||
145 | #define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) | |
146 | #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) | |
147 | #define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) | |
148 | #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) | |
149 | #define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) | |
150 | #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) | |
151 | #define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) | |
152 | #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) | |
153 | #define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) | |
154 | #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) | |
155 | #define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) | |
156 | #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) | |
157 | #define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) | |
158 | #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) | |
159 | ||
160 | /* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */ | |
161 | ||
162 | /* Two Wire Interface Registers (TWI0) */ | |
163 | ||
19381f02 BW |
164 | /* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ |
165 | ||
166 | /* SPORT1 Registers */ | |
167 | ||
168 | #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) | |
169 | #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) | |
170 | #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) | |
171 | #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) | |
172 | #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) | |
173 | #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) | |
174 | #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) | |
175 | #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) | |
176 | #define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX) | |
177 | #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) | |
178 | #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) | |
179 | #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) | |
180 | #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) | |
181 | #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) | |
182 | #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) | |
183 | #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) | |
184 | #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) | |
185 | #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) | |
186 | #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) | |
187 | #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) | |
188 | #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) | |
189 | #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) | |
190 | #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) | |
191 | #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) | |
192 | #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) | |
193 | #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) | |
194 | #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) | |
195 | #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) | |
196 | #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) | |
197 | #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) | |
198 | #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) | |
199 | #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) | |
200 | #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) | |
201 | #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) | |
202 | #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) | |
203 | #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) | |
204 | #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) | |
205 | #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) | |
206 | #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) | |
207 | #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) | |
208 | #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) | |
209 | #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) | |
210 | #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) | |
211 | #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) | |
212 | ||
213 | /* Asynchronous Memory Control Registers */ | |
214 | ||
215 | #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) | |
216 | #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) | |
217 | #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) | |
218 | #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) | |
219 | #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) | |
220 | #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) | |
221 | #define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL) | |
222 | #define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val) | |
223 | #define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) | |
224 | #define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) | |
225 | #define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) | |
226 | #define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) | |
227 | #define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL) | |
228 | #define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val) | |
229 | ||
230 | /* DDR Memory Control Registers */ | |
231 | ||
232 | #define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) | |
233 | #define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) | |
234 | #define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) | |
235 | #define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) | |
236 | #define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) | |
237 | #define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) | |
238 | #define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) | |
239 | #define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) | |
240 | #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) | |
241 | #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) | |
242 | #define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD) | |
a8a46a26 | 243 | #define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val) |
19381f02 BW |
244 | #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) |
245 | #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) | |
246 | #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) | |
247 | #define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) | |
248 | ||
249 | /* DDR BankRead and Write Count Registers */ | |
250 | ||
251 | #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) | |
252 | #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) | |
253 | #define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) | |
254 | #define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) | |
255 | #define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) | |
256 | #define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) | |
257 | #define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) | |
258 | #define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) | |
259 | #define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) | |
260 | #define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) | |
261 | #define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) | |
262 | #define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) | |
263 | #define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) | |
264 | #define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) | |
265 | #define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) | |
266 | #define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) | |
267 | #define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) | |
268 | #define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) | |
269 | #define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) | |
270 | #define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) | |
271 | #define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) | |
272 | #define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) | |
273 | #define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) | |
274 | #define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) | |
275 | #define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) | |
276 | #define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) | |
277 | #define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) | |
278 | #define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) | |
279 | #define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) | |
280 | #define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) | |
281 | #define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) | |
282 | #define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) | |
283 | #define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) | |
284 | #define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) | |
285 | #define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) | |
286 | #define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) | |
287 | #define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) | |
288 | #define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) | |
289 | #define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) | |
290 | #define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) | |
291 | #define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) | |
292 | #define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) | |
293 | #define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) | |
294 | #define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) | |
295 | #define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) | |
296 | #define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) | |
297 | #define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) | |
298 | #define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) | |
299 | #define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) | |
300 | #define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) | |
301 | ||
302 | /* DMAC0 Registers */ | |
303 | ||
2b73a19f MF |
304 | #define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER) |
305 | #define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val) | |
306 | #define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT) | |
307 | #define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val) | |
19381f02 BW |
308 | |
309 | /* DMA Channel 0 Registers */ | |
310 | ||
311 | #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) | |
a8a46a26 | 312 | #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) |
19381f02 | 313 | #define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) |
a8a46a26 | 314 | #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) |
19381f02 BW |
315 | #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) |
316 | #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) | |
317 | #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) | |
318 | #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) | |
319 | #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) | |
a8a46a26 | 320 | #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) |
19381f02 BW |
321 | #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) |
322 | #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) | |
323 | #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) | |
a8a46a26 | 324 | #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) |
19381f02 | 325 | #define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) |
a8a46a26 | 326 | #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) |
19381f02 | 327 | #define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) |
a8a46a26 | 328 | #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) |
19381f02 BW |
329 | #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) |
330 | #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) | |
331 | #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) | |
332 | #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) | |
333 | #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) | |
334 | #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) | |
335 | #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) | |
336 | #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) | |
337 | ||
338 | /* DMA Channel 1 Registers */ | |
339 | ||
340 | #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) | |
a8a46a26 | 341 | #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) |
19381f02 | 342 | #define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) |
a8a46a26 | 343 | #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) |
19381f02 BW |
344 | #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) |
345 | #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) | |
346 | #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) | |
347 | #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) | |
348 | #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) | |
a8a46a26 | 349 | #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) |
19381f02 BW |
350 | #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) |
351 | #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) | |
352 | #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) | |
a8a46a26 | 353 | #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) |
19381f02 | 354 | #define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) |
a8a46a26 | 355 | #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) |
19381f02 | 356 | #define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) |
a8a46a26 | 357 | #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) |
19381f02 BW |
358 | #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) |
359 | #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) | |
360 | #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) | |
361 | #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) | |
362 | #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) | |
363 | #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) | |
364 | #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) | |
365 | #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) | |
366 | ||
367 | /* DMA Channel 2 Registers */ | |
368 | ||
369 | #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) | |
a8a46a26 | 370 | #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) |
19381f02 | 371 | #define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) |
a8a46a26 | 372 | #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) |
19381f02 BW |
373 | #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) |
374 | #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) | |
375 | #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) | |
376 | #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) | |
377 | #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) | |
a8a46a26 | 378 | #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) |
19381f02 BW |
379 | #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) |
380 | #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) | |
381 | #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) | |
a8a46a26 | 382 | #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) |
19381f02 | 383 | #define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) |
a8a46a26 | 384 | #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) |
19381f02 | 385 | #define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) |
a8a46a26 | 386 | #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) |
19381f02 BW |
387 | #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) |
388 | #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) | |
389 | #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) | |
390 | #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) | |
391 | #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) | |
392 | #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) | |
393 | #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) | |
394 | #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) | |
395 | ||
396 | /* DMA Channel 3 Registers */ | |
397 | ||
398 | #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) | |
a8a46a26 | 399 | #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) |
19381f02 | 400 | #define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) |
a8a46a26 | 401 | #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) |
19381f02 BW |
402 | #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) |
403 | #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) | |
404 | #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) | |
405 | #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) | |
406 | #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) | |
a8a46a26 | 407 | #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) |
19381f02 BW |
408 | #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) |
409 | #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) | |
410 | #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) | |
a8a46a26 | 411 | #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) |
19381f02 | 412 | #define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) |
a8a46a26 | 413 | #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) |
19381f02 | 414 | #define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) |
a8a46a26 | 415 | #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) |
19381f02 BW |
416 | #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) |
417 | #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) | |
418 | #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) | |
419 | #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) | |
420 | #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) | |
421 | #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) | |
422 | #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) | |
423 | #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) | |
424 | ||
425 | /* DMA Channel 4 Registers */ | |
426 | ||
427 | #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) | |
a8a46a26 | 428 | #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) |
19381f02 | 429 | #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) |
a8a46a26 | 430 | #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) |
19381f02 BW |
431 | #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) |
432 | #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) | |
433 | #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) | |
434 | #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) | |
435 | #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) | |
a8a46a26 | 436 | #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) |
19381f02 BW |
437 | #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) |
438 | #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) | |
439 | #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) | |
a8a46a26 | 440 | #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) |
19381f02 | 441 | #define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) |
a8a46a26 | 442 | #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) |
19381f02 | 443 | #define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) |
a8a46a26 | 444 | #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) |
19381f02 BW |
445 | #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) |
446 | #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) | |
447 | #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) | |
448 | #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) | |
449 | #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) | |
450 | #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) | |
451 | #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) | |
452 | #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) | |
453 | ||
454 | /* DMA Channel 5 Registers */ | |
455 | ||
456 | #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) | |
a8a46a26 | 457 | #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) |
19381f02 | 458 | #define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) |
a8a46a26 | 459 | #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) |
19381f02 BW |
460 | #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) |
461 | #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) | |
462 | #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) | |
463 | #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) | |
464 | #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) | |
a8a46a26 | 465 | #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) |
19381f02 BW |
466 | #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) |
467 | #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) | |
468 | #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) | |
a8a46a26 | 469 | #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) |
19381f02 | 470 | #define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) |
a8a46a26 | 471 | #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) |
19381f02 | 472 | #define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) |
a8a46a26 | 473 | #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) |
19381f02 BW |
474 | #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) |
475 | #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) | |
476 | #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) | |
477 | #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) | |
478 | #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) | |
479 | #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) | |
480 | #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) | |
481 | #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) | |
482 | ||
483 | /* DMA Channel 6 Registers */ | |
484 | ||
485 | #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) | |
a8a46a26 | 486 | #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) |
19381f02 | 487 | #define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) |
a8a46a26 | 488 | #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) |
19381f02 BW |
489 | #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) |
490 | #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) | |
491 | #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) | |
492 | #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) | |
493 | #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) | |
a8a46a26 | 494 | #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) |
19381f02 BW |
495 | #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) |
496 | #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) | |
497 | #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) | |
a8a46a26 | 498 | #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) |
19381f02 | 499 | #define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) |
a8a46a26 | 500 | #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) |
19381f02 | 501 | #define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) |
a8a46a26 | 502 | #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) |
19381f02 BW |
503 | #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) |
504 | #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) | |
505 | #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) | |
506 | #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) | |
507 | #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) | |
508 | #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) | |
509 | #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) | |
510 | #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) | |
511 | ||
512 | /* DMA Channel 7 Registers */ | |
513 | ||
514 | #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) | |
a8a46a26 | 515 | #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) |
19381f02 | 516 | #define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) |
a8a46a26 | 517 | #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) |
19381f02 BW |
518 | #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) |
519 | #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) | |
520 | #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) | |
521 | #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) | |
522 | #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) | |
a8a46a26 | 523 | #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) |
19381f02 BW |
524 | #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) |
525 | #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) | |
526 | #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) | |
a8a46a26 | 527 | #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) |
19381f02 | 528 | #define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) |
a8a46a26 | 529 | #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) |
19381f02 | 530 | #define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) |
a8a46a26 | 531 | #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) |
19381f02 BW |
532 | #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) |
533 | #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) | |
534 | #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) | |
535 | #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) | |
536 | #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) | |
537 | #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) | |
538 | #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) | |
539 | #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) | |
540 | ||
541 | /* DMA Channel 8 Registers */ | |
542 | ||
543 | #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR) | |
a8a46a26 | 544 | #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val) |
19381f02 | 545 | #define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR) |
a8a46a26 | 546 | #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val) |
19381f02 BW |
547 | #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) |
548 | #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) | |
549 | #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) | |
550 | #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) | |
551 | #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) | |
a8a46a26 | 552 | #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) |
19381f02 BW |
553 | #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) |
554 | #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) | |
555 | #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) | |
a8a46a26 | 556 | #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) |
19381f02 | 557 | #define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR) |
a8a46a26 | 558 | #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val) |
19381f02 | 559 | #define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR) |
a8a46a26 | 560 | #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val) |
19381f02 BW |
561 | #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) |
562 | #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) | |
563 | #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) | |
564 | #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) | |
565 | #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) | |
566 | #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) | |
567 | #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) | |
568 | #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) | |
569 | ||
570 | /* DMA Channel 9 Registers */ | |
571 | ||
572 | #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR) | |
a8a46a26 | 573 | #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val) |
19381f02 | 574 | #define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR) |
a8a46a26 | 575 | #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val) |
19381f02 BW |
576 | #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) |
577 | #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) | |
578 | #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) | |
579 | #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) | |
580 | #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) | |
a8a46a26 | 581 | #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) |
19381f02 BW |
582 | #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) |
583 | #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) | |
584 | #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) | |
a8a46a26 | 585 | #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) |
19381f02 | 586 | #define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR) |
a8a46a26 | 587 | #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val) |
19381f02 | 588 | #define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR) |
a8a46a26 | 589 | #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val) |
19381f02 BW |
590 | #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) |
591 | #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) | |
592 | #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) | |
593 | #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) | |
594 | #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) | |
595 | #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) | |
596 | #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) | |
597 | #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) | |
598 | ||
599 | /* DMA Channel 10 Registers */ | |
600 | ||
601 | #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR) | |
a8a46a26 | 602 | #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val) |
19381f02 | 603 | #define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR) |
a8a46a26 | 604 | #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val) |
19381f02 BW |
605 | #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) |
606 | #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) | |
607 | #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) | |
608 | #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) | |
609 | #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) | |
a8a46a26 | 610 | #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) |
19381f02 BW |
611 | #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) |
612 | #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) | |
613 | #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) | |
a8a46a26 | 614 | #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) |
19381f02 | 615 | #define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR) |
a8a46a26 | 616 | #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val) |
19381f02 | 617 | #define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR) |
a8a46a26 | 618 | #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val) |
19381f02 BW |
619 | #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) |
620 | #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) | |
621 | #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) | |
622 | #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) | |
623 | #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) | |
624 | #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) | |
625 | #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) | |
626 | #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) | |
627 | ||
628 | /* DMA Channel 11 Registers */ | |
629 | ||
630 | #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR) | |
a8a46a26 | 631 | #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val) |
19381f02 | 632 | #define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR) |
a8a46a26 | 633 | #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val) |
19381f02 BW |
634 | #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) |
635 | #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) | |
636 | #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) | |
637 | #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) | |
638 | #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) | |
a8a46a26 | 639 | #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) |
19381f02 BW |
640 | #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) |
641 | #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) | |
642 | #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) | |
a8a46a26 | 643 | #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) |
19381f02 | 644 | #define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR) |
a8a46a26 | 645 | #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val) |
19381f02 | 646 | #define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR) |
a8a46a26 | 647 | #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val) |
19381f02 BW |
648 | #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) |
649 | #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) | |
650 | #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) | |
651 | #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) | |
652 | #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) | |
653 | #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) | |
654 | #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) | |
655 | #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) | |
656 | ||
657 | /* MDMA Stream 0 Registers */ | |
658 | ||
659 | #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) | |
a8a46a26 | 660 | #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) |
19381f02 | 661 | #define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) |
24a07a12 | 662 | #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) |
19381f02 BW |
663 | #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) |
664 | #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) | |
665 | #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) | |
666 | #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) | |
667 | #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) | |
24a07a12 | 668 | #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) |
19381f02 BW |
669 | #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) |
670 | #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) | |
671 | #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) | |
24a07a12 | 672 | #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) |
19381f02 | 673 | #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) |
24a07a12 | 674 | #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) |
19381f02 | 675 | #define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) |
24a07a12 | 676 | #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) |
19381f02 BW |
677 | #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) |
678 | #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) | |
679 | #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) | |
680 | #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) | |
681 | #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) | |
682 | #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) | |
683 | #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) | |
684 | #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) | |
685 | #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) | |
24a07a12 | 686 | #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) |
19381f02 | 687 | #define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) |
24a07a12 | 688 | #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) |
19381f02 BW |
689 | #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) |
690 | #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) | |
691 | #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) | |
692 | #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) | |
693 | #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) | |
24a07a12 | 694 | #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) |
19381f02 BW |
695 | #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) |
696 | #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) | |
697 | #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) | |
24a07a12 | 698 | #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) |
19381f02 | 699 | #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) |
24a07a12 | 700 | #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) |
19381f02 | 701 | #define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) |
24a07a12 | 702 | #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) |
19381f02 BW |
703 | #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) |
704 | #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) | |
705 | #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) | |
706 | #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) | |
707 | #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) | |
708 | #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) | |
709 | #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) | |
710 | #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) | |
711 | ||
712 | /* MDMA Stream 1 Registers */ | |
713 | ||
714 | #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) | |
24a07a12 | 715 | #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) |
19381f02 | 716 | #define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) |
24a07a12 | 717 | #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) |
19381f02 BW |
718 | #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) |
719 | #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) | |
720 | #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) | |
721 | #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) | |
722 | #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) | |
a8a46a26 | 723 | #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) |
19381f02 BW |
724 | #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) |
725 | #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) | |
726 | #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) | |
a8a46a26 | 727 | #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) |
19381f02 | 728 | #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) |
24a07a12 | 729 | #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) |
19381f02 | 730 | #define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) |
24a07a12 | 731 | #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) |
19381f02 BW |
732 | #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) |
733 | #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) | |
734 | #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) | |
735 | #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) | |
736 | #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) | |
737 | #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) | |
738 | #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) | |
739 | #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) | |
740 | #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) | |
24a07a12 | 741 | #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) |
19381f02 | 742 | #define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) |
24a07a12 | 743 | #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) |
19381f02 BW |
744 | #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) |
745 | #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) | |
746 | #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) | |
747 | #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) | |
748 | #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) | |
a8a46a26 | 749 | #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) |
19381f02 BW |
750 | #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) |
751 | #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) | |
752 | #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) | |
a8a46a26 | 753 | #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) |
19381f02 | 754 | #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) |
24a07a12 | 755 | #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) |
19381f02 | 756 | #define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) |
24a07a12 | 757 | #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) |
19381f02 BW |
758 | #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) |
759 | #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) | |
760 | #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) | |
761 | #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) | |
762 | #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) | |
763 | #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) | |
764 | #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) | |
765 | #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) | |
766 | ||
767 | /* EPPI1 Registers */ | |
768 | ||
769 | #define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) | |
770 | #define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) | |
771 | #define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) | |
772 | #define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) | |
773 | #define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) | |
774 | #define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) | |
775 | #define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) | |
776 | #define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) | |
777 | #define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) | |
778 | #define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) | |
779 | #define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) | |
780 | #define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) | |
781 | #define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) | |
782 | #define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) | |
783 | #define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) | |
784 | #define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) | |
785 | #define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) | |
786 | #define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) | |
787 | #define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) | |
788 | #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) | |
789 | #define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) | |
790 | #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) | |
791 | #define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) | |
792 | #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) | |
793 | #define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) | |
794 | #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) | |
795 | #define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) | |
796 | #define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) | |
797 | ||
798 | /* Port Interrubfin_read_()t 0 Registers (32-bit) */ | |
799 | ||
800 | #define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) | |
801 | #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) | |
802 | #define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) | |
803 | #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) | |
804 | #define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST) | |
805 | #define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val) | |
806 | #define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) | |
807 | #define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) | |
808 | #define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) | |
809 | #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) | |
810 | #define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) | |
811 | #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) | |
812 | #define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) | |
813 | #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) | |
814 | #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) | |
815 | #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) | |
816 | #define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) | |
817 | #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) | |
818 | #define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) | |
819 | #define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) | |
820 | ||
821 | /* Port Interrubfin_read_()t 1 Registers (32-bit) */ | |
822 | ||
823 | #define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) | |
824 | #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) | |
825 | #define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) | |
826 | #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) | |
827 | #define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST) | |
828 | #define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val) | |
829 | #define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) | |
830 | #define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) | |
831 | #define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) | |
832 | #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) | |
833 | #define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) | |
834 | #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) | |
835 | #define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) | |
836 | #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) | |
837 | #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) | |
838 | #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) | |
839 | #define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) | |
840 | #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) | |
841 | #define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) | |
842 | #define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) | |
843 | ||
844 | /* Port Interrubfin_read_()t 2 Registers (32-bit) */ | |
845 | ||
846 | #define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) | |
847 | #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) | |
848 | #define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) | |
849 | #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) | |
850 | #define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST) | |
851 | #define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val) | |
852 | #define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) | |
853 | #define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) | |
854 | #define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) | |
855 | #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) | |
856 | #define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) | |
857 | #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) | |
858 | #define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) | |
859 | #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) | |
860 | #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) | |
861 | #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) | |
862 | #define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) | |
863 | #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) | |
864 | #define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) | |
865 | #define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) | |
866 | ||
867 | /* Port Interrubfin_read_()t 3 Registers (32-bit) */ | |
868 | ||
869 | #define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) | |
870 | #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) | |
871 | #define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) | |
872 | #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) | |
873 | #define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST) | |
874 | #define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val) | |
875 | #define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) | |
876 | #define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) | |
877 | #define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) | |
878 | #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) | |
879 | #define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) | |
880 | #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) | |
881 | #define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) | |
882 | #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) | |
883 | #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) | |
884 | #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) | |
885 | #define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) | |
886 | #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) | |
887 | #define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) | |
888 | #define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) | |
889 | ||
890 | /* Port A Registers */ | |
891 | ||
892 | #define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) | |
893 | #define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) | |
894 | #define bfin_read_PORTA() bfin_read16(PORTA) | |
895 | #define bfin_write_PORTA(val) bfin_write16(PORTA, val) | |
896 | #define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) | |
897 | #define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) | |
898 | #define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) | |
899 | #define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) | |
900 | #define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) | |
901 | #define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) | |
902 | #define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) | |
903 | #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) | |
904 | #define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) | |
905 | #define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) | |
906 | #define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) | |
907 | #define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) | |
908 | ||
909 | /* Port B Registers */ | |
910 | ||
911 | #define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) | |
912 | #define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) | |
913 | #define bfin_read_PORTB() bfin_read16(PORTB) | |
914 | #define bfin_write_PORTB(val) bfin_write16(PORTB, val) | |
915 | #define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) | |
916 | #define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) | |
917 | #define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) | |
918 | #define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) | |
919 | #define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) | |
920 | #define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) | |
921 | #define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) | |
922 | #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) | |
923 | #define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) | |
924 | #define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) | |
925 | #define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) | |
926 | #define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) | |
927 | ||
928 | /* Port C Registers */ | |
929 | ||
930 | #define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) | |
931 | #define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) | |
932 | #define bfin_read_PORTC() bfin_read16(PORTC) | |
933 | #define bfin_write_PORTC(val) bfin_write16(PORTC, val) | |
934 | #define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) | |
935 | #define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) | |
936 | #define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) | |
937 | #define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) | |
938 | #define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) | |
939 | #define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) | |
940 | #define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) | |
941 | #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) | |
942 | #define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) | |
943 | #define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) | |
944 | #define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) | |
945 | #define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) | |
946 | ||
947 | /* Port D Registers */ | |
948 | ||
949 | #define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) | |
950 | #define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) | |
951 | #define bfin_read_PORTD() bfin_read16(PORTD) | |
952 | #define bfin_write_PORTD(val) bfin_write16(PORTD, val) | |
953 | #define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) | |
954 | #define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) | |
955 | #define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) | |
956 | #define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) | |
957 | #define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) | |
958 | #define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) | |
959 | #define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) | |
960 | #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) | |
961 | #define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) | |
962 | #define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) | |
963 | #define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) | |
964 | #define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) | |
965 | ||
966 | /* Port E Registers */ | |
967 | ||
968 | #define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) | |
969 | #define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) | |
970 | #define bfin_read_PORTE() bfin_read16(PORTE) | |
971 | #define bfin_write_PORTE(val) bfin_write16(PORTE, val) | |
972 | #define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) | |
973 | #define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) | |
974 | #define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) | |
975 | #define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) | |
976 | #define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) | |
977 | #define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) | |
978 | #define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) | |
979 | #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) | |
980 | #define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) | |
981 | #define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) | |
982 | #define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) | |
983 | #define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) | |
984 | ||
985 | /* Port F Registers */ | |
986 | ||
987 | #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) | |
988 | #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) | |
989 | #define bfin_read_PORTF() bfin_read16(PORTF) | |
990 | #define bfin_write_PORTF(val) bfin_write16(PORTF, val) | |
991 | #define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) | |
992 | #define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) | |
993 | #define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) | |
994 | #define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) | |
995 | #define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) | |
996 | #define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) | |
997 | #define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) | |
998 | #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) | |
999 | #define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) | |
1000 | #define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) | |
1001 | #define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) | |
1002 | #define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) | |
1003 | ||
1004 | /* Port G Registers */ | |
1005 | ||
1006 | #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) | |
1007 | #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) | |
1008 | #define bfin_read_PORTG() bfin_read16(PORTG) | |
1009 | #define bfin_write_PORTG(val) bfin_write16(PORTG, val) | |
1010 | #define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) | |
1011 | #define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) | |
1012 | #define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) | |
1013 | #define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) | |
1014 | #define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) | |
1015 | #define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) | |
1016 | #define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) | |
1017 | #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) | |
1018 | #define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) | |
1019 | #define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) | |
1020 | #define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) | |
1021 | #define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) | |
1022 | ||
1023 | /* Port H Registers */ | |
1024 | ||
1025 | #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) | |
1026 | #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) | |
1027 | #define bfin_read_PORTH() bfin_read16(PORTH) | |
1028 | #define bfin_write_PORTH(val) bfin_write16(PORTH, val) | |
1029 | #define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) | |
1030 | #define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) | |
1031 | #define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) | |
1032 | #define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) | |
1033 | #define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) | |
1034 | #define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) | |
1035 | #define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) | |
1036 | #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) | |
1037 | #define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) | |
1038 | #define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) | |
1039 | #define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) | |
1040 | #define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) | |
1041 | ||
1042 | /* Port I Registers */ | |
1043 | ||
1044 | #define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) | |
1045 | #define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) | |
1046 | #define bfin_read_PORTI() bfin_read16(PORTI) | |
1047 | #define bfin_write_PORTI(val) bfin_write16(PORTI, val) | |
1048 | #define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) | |
1049 | #define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) | |
1050 | #define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) | |
1051 | #define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) | |
1052 | #define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) | |
1053 | #define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) | |
1054 | #define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) | |
1055 | #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) | |
1056 | #define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) | |
1057 | #define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) | |
1058 | #define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) | |
1059 | #define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) | |
1060 | ||
1061 | /* Port J Registers */ | |
1062 | ||
1063 | #define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) | |
1064 | #define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) | |
1065 | #define bfin_read_PORTJ() bfin_read16(PORTJ) | |
1066 | #define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) | |
1067 | #define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) | |
1068 | #define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) | |
1069 | #define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) | |
1070 | #define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) | |
1071 | #define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) | |
1072 | #define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) | |
1073 | #define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) | |
1074 | #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) | |
1075 | #define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) | |
1076 | #define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) | |
1077 | #define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) | |
1078 | #define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) | |
1079 | ||
1080 | /* PWM Timer Registers */ | |
1081 | ||
1082 | #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) | |
1083 | #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) | |
1084 | #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) | |
1085 | #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) | |
1086 | #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) | |
1087 | #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) | |
1088 | #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) | |
1089 | #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) | |
1090 | #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) | |
1091 | #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) | |
1092 | #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) | |
1093 | #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) | |
1094 | #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) | |
1095 | #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) | |
1096 | #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) | |
1097 | #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) | |
1098 | #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) | |
1099 | #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) | |
1100 | #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) | |
1101 | #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) | |
1102 | #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) | |
1103 | #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) | |
1104 | #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) | |
1105 | #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) | |
1106 | #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) | |
1107 | #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) | |
1108 | #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) | |
1109 | #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) | |
1110 | #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) | |
1111 | #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) | |
1112 | #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) | |
1113 | #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) | |
1114 | #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) | |
1115 | #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) | |
1116 | #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) | |
1117 | #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) | |
1118 | #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) | |
1119 | #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) | |
1120 | #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) | |
1121 | #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) | |
1122 | #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) | |
1123 | #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) | |
1124 | #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) | |
1125 | #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) | |
1126 | #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) | |
1127 | #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) | |
1128 | #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) | |
1129 | #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) | |
1130 | #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) | |
1131 | #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) | |
1132 | #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) | |
1133 | #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) | |
1134 | #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) | |
1135 | #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) | |
1136 | #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) | |
1137 | #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) | |
1138 | #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) | |
1139 | #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) | |
1140 | #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) | |
1141 | #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) | |
1142 | #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) | |
1143 | #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) | |
1144 | #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) | |
1145 | #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) | |
1146 | ||
1147 | /* Timer Groubfin_read_() of 8 */ | |
1148 | ||
1149 | #define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) | |
1150 | #define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) | |
1151 | #define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) | |
1152 | #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) | |
1153 | #define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) | |
1154 | #define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) | |
1155 | ||
1156 | /* DMAC1 Registers */ | |
1157 | ||
2b73a19f MF |
1158 | #define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER) |
1159 | #define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val) | |
1160 | #define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT) | |
1161 | #define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val) | |
19381f02 BW |
1162 | |
1163 | /* DMA Channel 12 Registers */ | |
1164 | ||
1165 | #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR) | |
a8a46a26 | 1166 | #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val) |
19381f02 | 1167 | #define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR) |
a8a46a26 | 1168 | #define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val) |
19381f02 BW |
1169 | #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) |
1170 | #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) | |
1171 | #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) | |
1172 | #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) | |
1173 | #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) | |
a8a46a26 | 1174 | #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) |
19381f02 BW |
1175 | #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) |
1176 | #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) | |
1177 | #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) | |
a8a46a26 | 1178 | #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) |
19381f02 | 1179 | #define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR) |
a8a46a26 | 1180 | #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val) |
19381f02 | 1181 | #define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR) |
a8a46a26 | 1182 | #define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val) |
19381f02 BW |
1183 | #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) |
1184 | #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) | |
1185 | #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) | |
1186 | #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) | |
1187 | #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) | |
1188 | #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) | |
1189 | #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) | |
1190 | #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) | |
1191 | ||
1192 | /* DMA Channel 13 Registers */ | |
1193 | ||
1194 | #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR) | |
a8a46a26 | 1195 | #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val) |
19381f02 | 1196 | #define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR) |
a8a46a26 | 1197 | #define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val) |
19381f02 BW |
1198 | #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) |
1199 | #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) | |
1200 | #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) | |
1201 | #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) | |
1202 | #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) | |
a8a46a26 | 1203 | #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) |
19381f02 BW |
1204 | #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) |
1205 | #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) | |
1206 | #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) | |
a8a46a26 | 1207 | #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) |
19381f02 | 1208 | #define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR) |
a8a46a26 | 1209 | #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val) |
19381f02 | 1210 | #define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR) |
a8a46a26 | 1211 | #define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val) |
19381f02 BW |
1212 | #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) |
1213 | #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) | |
1214 | #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) | |
1215 | #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) | |
1216 | #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) | |
1217 | #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) | |
1218 | #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) | |
1219 | #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) | |
1220 | ||
1221 | /* DMA Channel 14 Registers */ | |
1222 | ||
1223 | #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR) | |
a8a46a26 | 1224 | #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val) |
19381f02 | 1225 | #define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR) |
a8a46a26 | 1226 | #define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val) |
19381f02 BW |
1227 | #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) |
1228 | #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) | |
1229 | #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) | |
1230 | #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) | |
1231 | #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) | |
a8a46a26 | 1232 | #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) |
19381f02 BW |
1233 | #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) |
1234 | #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) | |
1235 | #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) | |
a8a46a26 | 1236 | #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) |
19381f02 | 1237 | #define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR) |
a8a46a26 | 1238 | #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val) |
19381f02 | 1239 | #define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR) |
a8a46a26 | 1240 | #define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val) |
19381f02 BW |
1241 | #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) |
1242 | #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) | |
1243 | #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) | |
1244 | #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) | |
1245 | #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) | |
1246 | #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) | |
1247 | #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) | |
1248 | #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) | |
1249 | ||
1250 | /* DMA Channel 15 Registers */ | |
1251 | ||
1252 | #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR) | |
a8a46a26 | 1253 | #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val) |
19381f02 | 1254 | #define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR) |
a8a46a26 | 1255 | #define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val) |
19381f02 BW |
1256 | #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) |
1257 | #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) | |
1258 | #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) | |
1259 | #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) | |
1260 | #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) | |
a8a46a26 | 1261 | #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) |
19381f02 BW |
1262 | #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) |
1263 | #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) | |
1264 | #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) | |
a8a46a26 | 1265 | #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) |
19381f02 | 1266 | #define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR) |
a8a46a26 | 1267 | #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val) |
19381f02 | 1268 | #define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR) |
a8a46a26 | 1269 | #define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val) |
19381f02 BW |
1270 | #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) |
1271 | #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) | |
1272 | #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) | |
1273 | #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) | |
1274 | #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) | |
1275 | #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) | |
1276 | #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) | |
1277 | #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) | |
1278 | ||
1279 | /* DMA Channel 16 Registers */ | |
1280 | ||
1281 | #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR) | |
a8a46a26 | 1282 | #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val) |
19381f02 | 1283 | #define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR) |
a8a46a26 | 1284 | #define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val) |
19381f02 BW |
1285 | #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) |
1286 | #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) | |
1287 | #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) | |
1288 | #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) | |
1289 | #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) | |
a8a46a26 | 1290 | #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) |
19381f02 BW |
1291 | #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) |
1292 | #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) | |
1293 | #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) | |
a8a46a26 | 1294 | #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) |
19381f02 | 1295 | #define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR) |
a8a46a26 | 1296 | #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val) |
19381f02 | 1297 | #define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR) |
a8a46a26 | 1298 | #define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val) |
19381f02 BW |
1299 | #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) |
1300 | #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) | |
1301 | #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) | |
1302 | #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) | |
1303 | #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) | |
1304 | #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) | |
1305 | #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) | |
1306 | #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) | |
1307 | ||
1308 | /* DMA Channel 17 Registers */ | |
1309 | ||
1310 | #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR) | |
a8a46a26 | 1311 | #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val) |
19381f02 | 1312 | #define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR) |
a8a46a26 | 1313 | #define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val) |
19381f02 BW |
1314 | #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) |
1315 | #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) | |
1316 | #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) | |
1317 | #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) | |
1318 | #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) | |
a8a46a26 | 1319 | #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) |
19381f02 BW |
1320 | #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) |
1321 | #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) | |
1322 | #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) | |
a8a46a26 | 1323 | #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) |
19381f02 | 1324 | #define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR) |
a8a46a26 | 1325 | #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val) |
19381f02 | 1326 | #define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR) |
a8a46a26 | 1327 | #define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val) |
19381f02 BW |
1328 | #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) |
1329 | #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) | |
1330 | #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) | |
1331 | #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) | |
1332 | #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) | |
1333 | #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) | |
1334 | #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) | |
1335 | #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) | |
1336 | ||
1337 | /* DMA Channel 18 Registers */ | |
1338 | ||
1339 | #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR) | |
a8a46a26 | 1340 | #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val) |
19381f02 | 1341 | #define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR) |
a8a46a26 | 1342 | #define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val) |
19381f02 BW |
1343 | #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) |
1344 | #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) | |
1345 | #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) | |
1346 | #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) | |
1347 | #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) | |
a8a46a26 | 1348 | #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) |
19381f02 BW |
1349 | #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) |
1350 | #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) | |
1351 | #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) | |
a8a46a26 | 1352 | #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) |
19381f02 | 1353 | #define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR) |
a8a46a26 | 1354 | #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val) |
19381f02 | 1355 | #define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR) |
a8a46a26 | 1356 | #define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val) |
19381f02 BW |
1357 | #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) |
1358 | #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) | |
1359 | #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) | |
1360 | #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) | |
1361 | #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) | |
1362 | #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) | |
1363 | #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) | |
1364 | #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) | |
1365 | ||
1366 | /* DMA Channel 19 Registers */ | |
1367 | ||
1368 | #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR) | |
a8a46a26 | 1369 | #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val) |
19381f02 | 1370 | #define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR) |
a8a46a26 | 1371 | #define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val) |
19381f02 BW |
1372 | #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) |
1373 | #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) | |
1374 | #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) | |
1375 | #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) | |
1376 | #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) | |
a8a46a26 | 1377 | #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) |
19381f02 BW |
1378 | #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) |
1379 | #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) | |
1380 | #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) | |
a8a46a26 | 1381 | #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) |
19381f02 | 1382 | #define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR) |
a8a46a26 | 1383 | #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val) |
19381f02 | 1384 | #define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR) |
a8a46a26 | 1385 | #define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val) |
19381f02 BW |
1386 | #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) |
1387 | #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) | |
1388 | #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) | |
1389 | #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) | |
1390 | #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) | |
1391 | #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) | |
1392 | #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) | |
1393 | #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) | |
1394 | ||
1395 | /* DMA Channel 20 Registers */ | |
1396 | ||
1397 | #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR) | |
a8a46a26 | 1398 | #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val) |
19381f02 | 1399 | #define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR) |
a8a46a26 | 1400 | #define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val) |
19381f02 BW |
1401 | #define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) |
1402 | #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) | |
1403 | #define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) | |
1404 | #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) | |
1405 | #define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) | |
a8a46a26 | 1406 | #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) |
19381f02 BW |
1407 | #define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) |
1408 | #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) | |
1409 | #define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) | |
a8a46a26 | 1410 | #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) |
19381f02 | 1411 | #define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR) |
a8a46a26 | 1412 | #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val) |
19381f02 | 1413 | #define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR) |
a8a46a26 | 1414 | #define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val) |
19381f02 BW |
1415 | #define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) |
1416 | #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) | |
1417 | #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) | |
1418 | #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) | |
1419 | #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) | |
1420 | #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) | |
1421 | #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) | |
1422 | #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) | |
1423 | ||
1424 | /* DMA Channel 21 Registers */ | |
1425 | ||
1426 | #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR) | |
a8a46a26 | 1427 | #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val) |
19381f02 | 1428 | #define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR) |
a8a46a26 | 1429 | #define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val) |
19381f02 BW |
1430 | #define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) |
1431 | #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) | |
1432 | #define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) | |
1433 | #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) | |
1434 | #define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) | |
a8a46a26 | 1435 | #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) |
19381f02 BW |
1436 | #define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) |
1437 | #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) | |
1438 | #define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) | |
a8a46a26 | 1439 | #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) |
19381f02 | 1440 | #define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR) |
a8a46a26 | 1441 | #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val) |
19381f02 | 1442 | #define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR) |
a8a46a26 | 1443 | #define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val) |
19381f02 BW |
1444 | #define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) |
1445 | #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) | |
1446 | #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) | |
1447 | #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) | |
1448 | #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) | |
1449 | #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) | |
1450 | #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) | |
1451 | #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) | |
1452 | ||
1453 | /* DMA Channel 22 Registers */ | |
1454 | ||
1455 | #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR) | |
a8a46a26 | 1456 | #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val) |
19381f02 | 1457 | #define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR) |
a8a46a26 | 1458 | #define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val) |
19381f02 BW |
1459 | #define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) |
1460 | #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) | |
1461 | #define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) | |
1462 | #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) | |
1463 | #define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) | |
a8a46a26 | 1464 | #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) |
19381f02 BW |
1465 | #define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) |
1466 | #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) | |
1467 | #define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) | |
a8a46a26 | 1468 | #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) |
19381f02 | 1469 | #define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR) |
a8a46a26 | 1470 | #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val) |
19381f02 | 1471 | #define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR) |
a8a46a26 | 1472 | #define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val) |
19381f02 BW |
1473 | #define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) |
1474 | #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) | |
1475 | #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) | |
1476 | #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) | |
1477 | #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) | |
1478 | #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) | |
1479 | #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) | |
1480 | #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) | |
1481 | ||
1482 | /* DMA Channel 23 Registers */ | |
1483 | ||
1484 | #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR) | |
a8a46a26 | 1485 | #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val) |
19381f02 | 1486 | #define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR) |
a8a46a26 | 1487 | #define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val) |
19381f02 BW |
1488 | #define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) |
1489 | #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) | |
1490 | #define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) | |
1491 | #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) | |
1492 | #define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) | |
a8a46a26 | 1493 | #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) |
19381f02 BW |
1494 | #define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) |
1495 | #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) | |
1496 | #define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) | |
a8a46a26 | 1497 | #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) |
19381f02 | 1498 | #define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR) |
a8a46a26 | 1499 | #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val) |
19381f02 | 1500 | #define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR) |
a8a46a26 | 1501 | #define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val) |
19381f02 BW |
1502 | #define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) |
1503 | #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) | |
1504 | #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) | |
1505 | #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) | |
1506 | #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) | |
1507 | #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) | |
1508 | #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) | |
1509 | #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) | |
1510 | ||
1511 | /* MDMA Stream 2 Registers */ | |
1512 | ||
1513 | #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR) | |
a8a46a26 | 1514 | #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val) |
19381f02 | 1515 | #define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR) |
a8a46a26 | 1516 | #define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val) |
19381f02 BW |
1517 | #define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) |
1518 | #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) | |
1519 | #define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) | |
1520 | #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) | |
1521 | #define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) | |
a8a46a26 | 1522 | #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) |
19381f02 BW |
1523 | #define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) |
1524 | #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) | |
1525 | #define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) | |
a8a46a26 | 1526 | #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) |
19381f02 | 1527 | #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR) |
a8a46a26 | 1528 | #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val) |
19381f02 | 1529 | #define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR) |
a8a46a26 | 1530 | #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val) |
19381f02 BW |
1531 | #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) |
1532 | #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) | |
1533 | #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) | |
1534 | #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) | |
1535 | #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) | |
1536 | #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) | |
1537 | #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) | |
1538 | #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) | |
1539 | #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR) | |
a8a46a26 | 1540 | #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val) |
19381f02 | 1541 | #define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR) |
a8a46a26 | 1542 | #define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val) |
19381f02 BW |
1543 | #define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) |
1544 | #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) | |
1545 | #define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) | |
1546 | #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) | |
1547 | #define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) | |
a8a46a26 | 1548 | #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) |
19381f02 BW |
1549 | #define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) |
1550 | #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) | |
1551 | #define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) | |
a8a46a26 | 1552 | #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) |
19381f02 | 1553 | #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR) |
a8a46a26 | 1554 | #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val) |
19381f02 | 1555 | #define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR) |
a8a46a26 | 1556 | #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val) |
19381f02 BW |
1557 | #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) |
1558 | #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) | |
1559 | #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) | |
1560 | #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) | |
1561 | #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) | |
1562 | #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) | |
1563 | #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) | |
1564 | #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) | |
1565 | ||
1566 | /* MDMA Stream 3 Registers */ | |
1567 | ||
1568 | #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR) | |
a8a46a26 | 1569 | #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val) |
19381f02 | 1570 | #define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR) |
a8a46a26 | 1571 | #define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val) |
19381f02 BW |
1572 | #define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) |
1573 | #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) | |
1574 | #define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) | |
1575 | #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) | |
1576 | #define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) | |
a8a46a26 | 1577 | #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) |
19381f02 BW |
1578 | #define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) |
1579 | #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) | |
1580 | #define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) | |
a8a46a26 | 1581 | #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) |
19381f02 | 1582 | #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR) |
a8a46a26 | 1583 | #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val) |
19381f02 | 1584 | #define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR) |
a8a46a26 | 1585 | #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val) |
19381f02 BW |
1586 | #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) |
1587 | #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) | |
1588 | #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) | |
1589 | #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) | |
1590 | #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) | |
1591 | #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) | |
1592 | #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) | |
1593 | #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) | |
1594 | #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR) | |
a8a46a26 | 1595 | #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val) |
19381f02 | 1596 | #define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR) |
a8a46a26 | 1597 | #define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val) |
19381f02 BW |
1598 | #define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) |
1599 | #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) | |
1600 | #define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) | |
1601 | #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) | |
1602 | #define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) | |
a8a46a26 | 1603 | #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) |
19381f02 BW |
1604 | #define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) |
1605 | #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) | |
1606 | #define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) | |
a8a46a26 | 1607 | #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) |
19381f02 | 1608 | #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR) |
a8a46a26 | 1609 | #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val) |
19381f02 | 1610 | #define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR) |
a8a46a26 | 1611 | #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val) |
19381f02 BW |
1612 | #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) |
1613 | #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) | |
1614 | #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) | |
1615 | #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) | |
1616 | #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) | |
1617 | #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) | |
1618 | #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) | |
1619 | #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) | |
1620 | ||
1621 | /* UART1 Registers */ | |
1622 | ||
1623 | #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) | |
1624 | #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) | |
1625 | #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) | |
1626 | #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) | |
1627 | #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) | |
1628 | #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) | |
1629 | #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) | |
1630 | #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) | |
1631 | #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) | |
1632 | #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) | |
1633 | #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) | |
1634 | #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) | |
1635 | #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) | |
1636 | #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) | |
1637 | #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) | |
1638 | #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) | |
1639 | #define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) | |
1640 | #define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) | |
1641 | #define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) | |
1642 | #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) | |
1643 | #define bfin_read_UART1_THR() bfin_read16(UART1_THR) | |
1644 | #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) | |
1645 | #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) | |
1646 | #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) | |
1647 | ||
1648 | /* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */ | |
1649 | ||
1650 | /* SPI1 Registers */ | |
1651 | ||
1652 | #define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) | |
1653 | #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) | |
1654 | #define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) | |
1655 | #define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) | |
1656 | #define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) | |
1657 | #define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) | |
1658 | #define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) | |
1659 | #define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) | |
1660 | #define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) | |
1661 | #define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) | |
1662 | #define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) | |
1663 | #define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) | |
1664 | #define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) | |
1665 | #define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) | |
1666 | ||
1667 | /* SPORT2 Registers */ | |
1668 | ||
1669 | #define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) | |
1670 | #define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) | |
1671 | #define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) | |
1672 | #define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) | |
1673 | #define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) | |
1674 | #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) | |
1675 | #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) | |
1676 | #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) | |
1677 | #define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX) | |
1678 | #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) | |
1679 | #define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) | |
1680 | #define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) | |
1681 | #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) | |
1682 | #define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) | |
1683 | #define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) | |
1684 | #define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) | |
1685 | #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) | |
1686 | #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) | |
1687 | #define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) | |
1688 | #define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) | |
1689 | #define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) | |
1690 | #define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) | |
1691 | #define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) | |
1692 | #define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) | |
1693 | #define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) | |
1694 | #define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) | |
1695 | #define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) | |
1696 | #define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) | |
1697 | #define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) | |
1698 | #define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) | |
1699 | #define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) | |
1700 | #define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) | |
1701 | #define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) | |
1702 | #define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) | |
1703 | #define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) | |
1704 | #define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) | |
1705 | #define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) | |
1706 | #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) | |
1707 | #define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) | |
1708 | #define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) | |
1709 | #define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) | |
1710 | #define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) | |
1711 | #define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) | |
1712 | #define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) | |
1713 | ||
1714 | /* SPORT3 Registers */ | |
1715 | ||
1716 | #define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) | |
1717 | #define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) | |
1718 | #define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) | |
1719 | #define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) | |
1720 | #define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) | |
1721 | #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) | |
1722 | #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) | |
1723 | #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) | |
1724 | #define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX) | |
1725 | #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) | |
1726 | #define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) | |
1727 | #define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) | |
1728 | #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) | |
1729 | #define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) | |
1730 | #define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) | |
1731 | #define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) | |
1732 | #define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) | |
1733 | #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) | |
1734 | #define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) | |
1735 | #define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) | |
1736 | #define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) | |
1737 | #define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) | |
1738 | #define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) | |
1739 | #define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) | |
1740 | #define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) | |
1741 | #define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) | |
1742 | #define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) | |
1743 | #define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) | |
1744 | #define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) | |
1745 | #define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) | |
1746 | #define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) | |
1747 | #define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) | |
1748 | #define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) | |
1749 | #define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) | |
1750 | #define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) | |
1751 | #define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) | |
1752 | #define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) | |
1753 | #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) | |
1754 | #define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) | |
1755 | #define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) | |
1756 | #define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) | |
1757 | #define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) | |
1758 | #define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) | |
1759 | #define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) | |
1760 | ||
1761 | /* EPPI2 Registers */ | |
1762 | ||
1763 | #define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) | |
1764 | #define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) | |
1765 | #define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) | |
1766 | #define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) | |
1767 | #define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) | |
1768 | #define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) | |
1769 | #define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) | |
1770 | #define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) | |
1771 | #define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) | |
1772 | #define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) | |
1773 | #define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) | |
1774 | #define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) | |
1775 | #define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) | |
1776 | #define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) | |
1777 | #define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) | |
1778 | #define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) | |
1779 | #define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) | |
1780 | #define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) | |
1781 | #define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) | |
1782 | #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) | |
1783 | #define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) | |
1784 | #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) | |
1785 | #define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) | |
1786 | #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) | |
1787 | #define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) | |
1788 | #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) | |
1789 | #define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) | |
1790 | #define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) | |
1791 | ||
1792 | /* CAN Controller 0 Config 1 Registers */ | |
1793 | ||
1794 | #define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) | |
1795 | #define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) | |
1796 | #define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) | |
1797 | #define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) | |
1798 | #define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) | |
1799 | #define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) | |
1800 | #define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) | |
1801 | #define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) | |
1802 | #define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) | |
1803 | #define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) | |
1804 | #define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) | |
1805 | #define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) | |
1806 | #define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) | |
1807 | #define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) | |
1808 | #define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) | |
1809 | #define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) | |
1810 | #define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) | |
1811 | #define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) | |
1812 | #define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) | |
1813 | #define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) | |
1814 | #define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) | |
1815 | #define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) | |
1816 | #define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) | |
1817 | #define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) | |
1818 | #define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) | |
1819 | #define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) | |
1820 | ||
1821 | /* CAN Controller 0 Config 2 Registers */ | |
1822 | ||
1823 | #define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) | |
1824 | #define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) | |
1825 | #define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) | |
1826 | #define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) | |
1827 | #define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) | |
1828 | #define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) | |
1829 | #define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) | |
1830 | #define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) | |
1831 | #define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) | |
1832 | #define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) | |
1833 | #define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) | |
1834 | #define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) | |
1835 | #define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) | |
1836 | #define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) | |
1837 | #define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) | |
1838 | #define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) | |
1839 | #define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) | |
1840 | #define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) | |
1841 | #define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) | |
1842 | #define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) | |
1843 | #define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) | |
1844 | #define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) | |
1845 | #define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) | |
1846 | #define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) | |
1847 | #define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) | |
1848 | #define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) | |
1849 | ||
1850 | /* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */ | |
1851 | ||
1852 | #define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) | |
1853 | #define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) | |
1854 | #define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) | |
1855 | #define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) | |
1856 | #define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) | |
1857 | #define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) | |
1858 | #define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) | |
1859 | #define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) | |
1860 | #define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) | |
1861 | #define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) | |
1862 | #define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) | |
1863 | #define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) | |
1864 | #define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) | |
1865 | #define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) | |
1866 | #define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) | |
1867 | #define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) | |
1868 | #define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) | |
1869 | #define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) | |
1870 | #define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) | |
1871 | #define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) | |
1872 | #define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) | |
1873 | #define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) | |
1874 | #define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) | |
1875 | #define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) | |
1876 | #define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) | |
1877 | #define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) | |
1878 | #define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) | |
1879 | #define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) | |
1880 | #define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) | |
1881 | #define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) | |
1882 | #define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) | |
1883 | #define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) | |
1884 | ||
1885 | /* CAN Controller 0 Accebfin_read_()tance Registers */ | |
1886 | ||
1887 | #define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) | |
1888 | #define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) | |
1889 | #define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) | |
1890 | #define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) | |
1891 | #define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) | |
1892 | #define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) | |
1893 | #define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) | |
1894 | #define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) | |
1895 | #define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) | |
1896 | #define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) | |
1897 | #define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) | |
1898 | #define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) | |
1899 | #define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) | |
1900 | #define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) | |
1901 | #define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) | |
1902 | #define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) | |
1903 | #define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) | |
1904 | #define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) | |
1905 | #define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) | |
1906 | #define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) | |
1907 | #define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) | |
1908 | #define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) | |
1909 | #define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) | |
1910 | #define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) | |
1911 | #define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) | |
1912 | #define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) | |
1913 | #define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) | |
1914 | #define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) | |
1915 | #define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) | |
1916 | #define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) | |
1917 | #define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) | |
1918 | #define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) | |
1919 | #define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) | |
1920 | #define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) | |
1921 | #define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) | |
1922 | #define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) | |
1923 | #define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) | |
1924 | #define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) | |
1925 | #define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) | |
1926 | #define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) | |
1927 | #define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) | |
1928 | #define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) | |
1929 | #define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) | |
1930 | #define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) | |
1931 | #define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) | |
1932 | #define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) | |
1933 | #define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) | |
1934 | #define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) | |
1935 | #define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) | |
1936 | #define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) | |
1937 | #define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) | |
1938 | #define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) | |
1939 | #define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) | |
1940 | #define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) | |
1941 | #define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) | |
1942 | #define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) | |
1943 | #define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) | |
1944 | #define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) | |
1945 | #define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) | |
1946 | #define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) | |
1947 | #define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) | |
1948 | #define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) | |
1949 | #define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) | |
1950 | #define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) | |
1951 | ||
1952 | /* CAN Controller 0 Accebfin_read_()tance Registers */ | |
1953 | ||
1954 | #define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) | |
1955 | #define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) | |
1956 | #define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) | |
1957 | #define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) | |
1958 | #define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) | |
1959 | #define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) | |
1960 | #define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) | |
1961 | #define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) | |
1962 | #define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) | |
1963 | #define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) | |
1964 | #define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) | |
1965 | #define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) | |
1966 | #define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) | |
1967 | #define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) | |
1968 | #define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) | |
1969 | #define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) | |
1970 | #define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) | |
1971 | #define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) | |
1972 | #define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) | |
1973 | #define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) | |
1974 | #define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) | |
1975 | #define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) | |
1976 | #define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) | |
1977 | #define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) | |
1978 | #define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) | |
1979 | #define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) | |
1980 | #define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) | |
1981 | #define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) | |
1982 | #define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) | |
1983 | #define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) | |
1984 | #define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) | |
1985 | #define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) | |
1986 | #define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) | |
1987 | #define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) | |
1988 | #define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) | |
1989 | #define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) | |
1990 | #define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) | |
1991 | #define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) | |
1992 | #define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) | |
1993 | #define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) | |
1994 | #define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) | |
1995 | #define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) | |
1996 | #define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) | |
1997 | #define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) | |
1998 | #define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) | |
1999 | #define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) | |
2000 | #define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) | |
2001 | #define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) | |
2002 | #define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) | |
2003 | #define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) | |
2004 | #define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) | |
2005 | #define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) | |
2006 | #define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) | |
2007 | #define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) | |
2008 | #define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) | |
2009 | #define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) | |
2010 | #define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) | |
2011 | #define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) | |
2012 | #define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) | |
2013 | #define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) | |
2014 | #define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) | |
2015 | #define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) | |
2016 | #define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) | |
2017 | #define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) | |
2018 | ||
2019 | /* CAN Controller 0 Mailbox Data Registers */ | |
2020 | ||
2021 | #define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) | |
2022 | #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) | |
2023 | #define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) | |
2024 | #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) | |
2025 | #define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) | |
2026 | #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) | |
2027 | #define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) | |
2028 | #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) | |
2029 | #define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) | |
2030 | #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) | |
2031 | #define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) | |
2032 | #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) | |
2033 | #define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) | |
2034 | #define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) | |
2035 | #define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) | |
2036 | #define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) | |
2037 | #define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) | |
2038 | #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) | |
2039 | #define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) | |
2040 | #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) | |
2041 | #define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) | |
2042 | #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) | |
2043 | #define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) | |
2044 | #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) | |
2045 | #define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) | |
2046 | #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) | |
2047 | #define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) | |
2048 | #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) | |
2049 | #define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) | |
2050 | #define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) | |
2051 | #define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) | |
2052 | #define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) | |
2053 | #define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) | |
2054 | #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) | |
2055 | #define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) | |
2056 | #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) | |
2057 | #define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) | |
2058 | #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) | |
2059 | #define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) | |
2060 | #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) | |
2061 | #define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) | |
2062 | #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) | |
2063 | #define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) | |
2064 | #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) | |
2065 | #define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) | |
2066 | #define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) | |
2067 | #define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) | |
2068 | #define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) | |
2069 | #define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) | |
2070 | #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) | |
2071 | #define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) | |
2072 | #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) | |
2073 | #define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) | |
2074 | #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) | |
2075 | #define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) | |
2076 | #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) | |
2077 | #define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) | |
2078 | #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) | |
2079 | #define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) | |
2080 | #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) | |
2081 | #define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) | |
2082 | #define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) | |
2083 | #define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) | |
2084 | #define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) | |
2085 | #define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) | |
2086 | #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) | |
2087 | #define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) | |
2088 | #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) | |
2089 | #define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) | |
2090 | #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) | |
2091 | #define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) | |
2092 | #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) | |
2093 | #define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) | |
2094 | #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) | |
2095 | #define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) | |
2096 | #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) | |
2097 | #define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) | |
2098 | #define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) | |
2099 | #define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) | |
2100 | #define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) | |
2101 | #define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) | |
2102 | #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) | |
2103 | #define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) | |
2104 | #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) | |
2105 | #define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) | |
2106 | #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) | |
2107 | #define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) | |
2108 | #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) | |
2109 | #define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) | |
2110 | #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) | |
2111 | #define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) | |
2112 | #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) | |
2113 | #define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) | |
2114 | #define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) | |
2115 | #define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) | |
2116 | #define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) | |
2117 | #define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) | |
2118 | #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) | |
2119 | #define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) | |
2120 | #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) | |
2121 | #define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) | |
2122 | #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) | |
2123 | #define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) | |
2124 | #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) | |
2125 | #define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) | |
2126 | #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) | |
2127 | #define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) | |
2128 | #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) | |
2129 | #define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) | |
2130 | #define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) | |
2131 | #define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) | |
2132 | #define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) | |
2133 | #define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) | |
2134 | #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) | |
2135 | #define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) | |
2136 | #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) | |
2137 | #define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) | |
2138 | #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) | |
2139 | #define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) | |
2140 | #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) | |
2141 | #define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) | |
2142 | #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) | |
2143 | #define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) | |
2144 | #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) | |
2145 | #define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) | |
2146 | #define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) | |
2147 | #define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) | |
2148 | #define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) | |
2149 | #define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) | |
2150 | #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) | |
2151 | #define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) | |
2152 | #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) | |
2153 | #define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) | |
2154 | #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) | |
2155 | #define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) | |
2156 | #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) | |
2157 | #define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) | |
2158 | #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) | |
2159 | #define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) | |
2160 | #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) | |
2161 | #define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) | |
2162 | #define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) | |
2163 | #define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) | |
2164 | #define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) | |
2165 | #define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) | |
2166 | #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) | |
2167 | #define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) | |
2168 | #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) | |
2169 | #define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) | |
2170 | #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) | |
2171 | #define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) | |
2172 | #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) | |
2173 | #define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) | |
2174 | #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) | |
2175 | #define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) | |
2176 | #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) | |
2177 | #define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) | |
2178 | #define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) | |
2179 | #define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) | |
2180 | #define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) | |
2181 | #define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) | |
2182 | #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) | |
2183 | #define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) | |
2184 | #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) | |
2185 | #define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) | |
2186 | #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) | |
2187 | #define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) | |
2188 | #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) | |
2189 | #define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) | |
2190 | #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) | |
2191 | #define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) | |
2192 | #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) | |
2193 | #define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) | |
2194 | #define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) | |
2195 | #define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) | |
2196 | #define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) | |
2197 | #define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) | |
2198 | #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) | |
2199 | #define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) | |
2200 | #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) | |
2201 | #define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) | |
2202 | #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) | |
2203 | #define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) | |
2204 | #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) | |
2205 | #define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) | |
2206 | #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) | |
2207 | #define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) | |
2208 | #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) | |
2209 | #define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) | |
2210 | #define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) | |
2211 | #define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) | |
2212 | #define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) | |
2213 | #define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) | |
2214 | #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) | |
2215 | #define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) | |
2216 | #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) | |
2217 | #define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) | |
2218 | #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) | |
2219 | #define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) | |
2220 | #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) | |
2221 | #define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) | |
2222 | #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) | |
2223 | #define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) | |
2224 | #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) | |
2225 | #define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) | |
2226 | #define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) | |
2227 | #define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) | |
2228 | #define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) | |
2229 | #define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) | |
2230 | #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) | |
2231 | #define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) | |
2232 | #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) | |
2233 | #define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) | |
2234 | #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) | |
2235 | #define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) | |
2236 | #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) | |
2237 | #define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) | |
2238 | #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) | |
2239 | #define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) | |
2240 | #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) | |
2241 | #define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) | |
2242 | #define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) | |
2243 | #define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) | |
2244 | #define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) | |
2245 | #define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) | |
2246 | #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) | |
2247 | #define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) | |
2248 | #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) | |
2249 | #define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) | |
2250 | #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) | |
2251 | #define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) | |
2252 | #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) | |
2253 | #define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) | |
2254 | #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) | |
2255 | #define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) | |
2256 | #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) | |
2257 | #define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) | |
2258 | #define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) | |
2259 | #define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) | |
2260 | #define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) | |
2261 | #define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) | |
2262 | #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) | |
2263 | #define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) | |
2264 | #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) | |
2265 | #define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) | |
2266 | #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) | |
2267 | #define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) | |
2268 | #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) | |
2269 | #define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) | |
2270 | #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) | |
2271 | #define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) | |
2272 | #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) | |
2273 | #define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) | |
2274 | #define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) | |
2275 | #define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) | |
2276 | #define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) | |
2277 | ||
2278 | /* CAN Controller 0 Mailbox Data Registers */ | |
2279 | ||
2280 | #define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) | |
2281 | #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) | |
2282 | #define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) | |
2283 | #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) | |
2284 | #define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) | |
2285 | #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) | |
2286 | #define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) | |
2287 | #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) | |
2288 | #define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) | |
2289 | #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) | |
2290 | #define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) | |
2291 | #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) | |
2292 | #define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) | |
2293 | #define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) | |
2294 | #define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) | |
2295 | #define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) | |
2296 | #define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) | |
2297 | #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) | |
2298 | #define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) | |
2299 | #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) | |
2300 | #define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) | |
2301 | #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) | |
2302 | #define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) | |
2303 | #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) | |
2304 | #define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) | |
2305 | #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) | |
2306 | #define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) | |
2307 | #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) | |
2308 | #define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) | |
2309 | #define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) | |
2310 | #define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) | |
2311 | #define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) | |
2312 | #define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) | |
2313 | #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) | |
2314 | #define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) | |
2315 | #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) | |
2316 | #define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) | |
2317 | #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) | |
2318 | #define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) | |
2319 | #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) | |
2320 | #define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) | |
2321 | #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) | |
2322 | #define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) | |
2323 | #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) | |
2324 | #define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) | |
2325 | #define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) | |
2326 | #define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) | |
2327 | #define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) | |
2328 | #define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) | |
2329 | #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) | |
2330 | #define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) | |
2331 | #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) | |
2332 | #define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) | |
2333 | #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) | |
2334 | #define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) | |
2335 | #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) | |
2336 | #define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) | |
2337 | #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) | |
2338 | #define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) | |
2339 | #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) | |
2340 | #define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) | |
2341 | #define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) | |
2342 | #define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) | |
2343 | #define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) | |
2344 | #define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) | |
2345 | #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) | |
2346 | #define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) | |
2347 | #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) | |
2348 | #define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) | |
2349 | #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) | |
2350 | #define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) | |
2351 | #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) | |
2352 | #define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) | |
2353 | #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) | |
2354 | #define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) | |
2355 | #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) | |
2356 | #define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) | |
2357 | #define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) | |
2358 | #define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) | |
2359 | #define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) | |
2360 | #define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) | |
2361 | #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) | |
2362 | #define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) | |
2363 | #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) | |
2364 | #define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) | |
2365 | #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) | |
2366 | #define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) | |
2367 | #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) | |
2368 | #define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) | |
2369 | #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) | |
2370 | #define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) | |
2371 | #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) | |
2372 | #define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) | |
2373 | #define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) | |
2374 | #define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) | |
2375 | #define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) | |
2376 | #define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) | |
2377 | #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) | |
2378 | #define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) | |
2379 | #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) | |
2380 | #define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) | |
2381 | #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) | |
2382 | #define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) | |
2383 | #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) | |
2384 | #define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) | |
2385 | #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) | |
2386 | #define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) | |
2387 | #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) | |
2388 | #define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) | |
2389 | #define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) | |
2390 | #define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) | |
2391 | #define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) | |
2392 | #define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) | |
2393 | #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) | |
2394 | #define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) | |
2395 | #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) | |
2396 | #define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) | |
2397 | #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) | |
2398 | #define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) | |
2399 | #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) | |
2400 | #define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) | |
2401 | #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) | |
2402 | #define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) | |
2403 | #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) | |
2404 | #define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) | |
2405 | #define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) | |
2406 | #define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) | |
2407 | #define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) | |
2408 | #define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) | |
2409 | #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) | |
2410 | #define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) | |
2411 | #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) | |
2412 | #define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) | |
2413 | #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) | |
2414 | #define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) | |
2415 | #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) | |
2416 | #define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) | |
2417 | #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) | |
2418 | #define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) | |
2419 | #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) | |
2420 | #define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) | |
2421 | #define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) | |
2422 | #define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) | |
2423 | #define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) | |
2424 | #define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) | |
2425 | #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) | |
2426 | #define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) | |
2427 | #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) | |
2428 | #define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) | |
2429 | #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) | |
2430 | #define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) | |
2431 | #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) | |
2432 | #define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) | |
2433 | #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) | |
2434 | #define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) | |
2435 | #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) | |
2436 | #define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) | |
2437 | #define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) | |
2438 | #define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) | |
2439 | #define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) | |
2440 | #define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) | |
2441 | #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) | |
2442 | #define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) | |
2443 | #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) | |
2444 | #define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) | |
2445 | #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) | |
2446 | #define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) | |
2447 | #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) | |
2448 | #define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) | |
2449 | #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) | |
2450 | #define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) | |
2451 | #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) | |
2452 | #define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) | |
2453 | #define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) | |
2454 | #define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) | |
2455 | #define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) | |
2456 | #define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) | |
2457 | #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) | |
2458 | #define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) | |
2459 | #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) | |
2460 | #define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) | |
2461 | #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) | |
2462 | #define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) | |
2463 | #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) | |
2464 | #define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) | |
2465 | #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) | |
2466 | #define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) | |
2467 | #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) | |
2468 | #define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) | |
2469 | #define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) | |
2470 | #define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) | |
2471 | #define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) | |
2472 | #define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) | |
2473 | #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) | |
2474 | #define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) | |
2475 | #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) | |
2476 | #define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) | |
2477 | #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) | |
2478 | #define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) | |
2479 | #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) | |
2480 | #define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) | |
2481 | #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) | |
2482 | #define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) | |
2483 | #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) | |
2484 | #define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) | |
2485 | #define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) | |
2486 | #define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) | |
2487 | #define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) | |
2488 | #define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) | |
2489 | #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) | |
2490 | #define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) | |
2491 | #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) | |
2492 | #define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) | |
2493 | #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) | |
2494 | #define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) | |
2495 | #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) | |
2496 | #define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) | |
2497 | #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) | |
2498 | #define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) | |
2499 | #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) | |
2500 | #define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) | |
2501 | #define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) | |
2502 | #define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) | |
2503 | #define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) | |
2504 | #define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) | |
2505 | #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) | |
2506 | #define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) | |
2507 | #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) | |
2508 | #define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) | |
2509 | #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) | |
2510 | #define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) | |
2511 | #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) | |
2512 | #define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) | |
2513 | #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) | |
2514 | #define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) | |
2515 | #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) | |
2516 | #define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) | |
2517 | #define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) | |
2518 | #define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) | |
2519 | #define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) | |
2520 | #define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) | |
2521 | #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) | |
2522 | #define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) | |
2523 | #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) | |
2524 | #define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) | |
2525 | #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) | |
2526 | #define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) | |
2527 | #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) | |
2528 | #define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) | |
2529 | #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) | |
2530 | #define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) | |
2531 | #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) | |
2532 | #define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) | |
2533 | #define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) | |
2534 | #define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) | |
2535 | #define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) | |
2536 | ||
2537 | /* UART3 Registers */ | |
2538 | ||
2539 | #define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) | |
2540 | #define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) | |
2541 | #define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) | |
2542 | #define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) | |
2543 | #define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) | |
2544 | #define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) | |
2545 | #define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) | |
2546 | #define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) | |
2547 | #define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) | |
2548 | #define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) | |
2549 | #define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) | |
2550 | #define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) | |
2551 | #define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) | |
2552 | #define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) | |
2553 | #define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) | |
2554 | #define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) | |
2555 | #define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) | |
2556 | #define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) | |
2557 | #define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) | |
2558 | #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) | |
2559 | #define bfin_read_UART3_THR() bfin_read16(UART3_THR) | |
2560 | #define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) | |
2561 | #define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) | |
2562 | #define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) | |
2563 | ||
2564 | /* NFC Registers */ | |
2565 | ||
2566 | #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) | |
2567 | #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) | |
2568 | #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) | |
2569 | #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) | |
2570 | #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) | |
2571 | #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) | |
2572 | #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) | |
2573 | #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) | |
2574 | #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) | |
2575 | #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) | |
2576 | #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) | |
2577 | #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) | |
2578 | #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) | |
2579 | #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) | |
2580 | #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) | |
2581 | #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) | |
2582 | #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) | |
2583 | #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) | |
2584 | #define bfin_read_NFC_RST() bfin_read16(NFC_RST) | |
2585 | #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) | |
2586 | #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) | |
2587 | #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) | |
2588 | #define bfin_read_NFC_READ() bfin_read16(NFC_READ) | |
2589 | #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) | |
2590 | #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) | |
2591 | #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) | |
2592 | #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) | |
2593 | #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) | |
2594 | #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) | |
2595 | #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) | |
2596 | #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) | |
2597 | #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) | |
2598 | ||
2599 | /* Counter Registers */ | |
2600 | ||
2601 | #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) | |
2602 | #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) | |
2603 | #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) | |
2604 | #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) | |
2605 | #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) | |
2606 | #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) | |
2607 | #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) | |
2608 | #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) | |
2609 | #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) | |
2610 | #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) | |
2611 | #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) | |
2612 | #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) | |
2613 | #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) | |
2614 | #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) | |
2615 | #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) | |
2616 | #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) | |
2617 | ||
19381f02 BW |
2618 | /* Security Registers */ |
2619 | ||
2620 | #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) | |
2621 | #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) | |
2622 | #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) | |
2623 | #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) | |
2624 | #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) | |
2625 | #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) | |
2626 | ||
2627 | /* DMA Peribfin_read_()heral Mux Register */ | |
2628 | ||
2629 | #define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) | |
2630 | #define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) | |
2631 | ||
19381f02 BW |
2632 | /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ |
2633 | ||
2634 | /* legacy definitions */ | |
2635 | #define bfin_read_EBIU_AMCBCTL0 bfin_read_EBIU_AMBCTL0 | |
2636 | #define bfin_write_EBIU_AMCBCTL0 bfin_write_EBIU_AMBCTL0 | |
2637 | #define bfin_read_EBIU_AMCBCTL1 bfin_read_EBIU_AMBCTL1 | |
2638 | #define bfin_write_EBIU_AMCBCTL1 bfin_write_EBIU_AMBCTL1 | |
2639 | #define bfin_read_PINT0_IRQ bfin_read_PINT0_REQUEST | |
2640 | #define bfin_write_PINT0_IRQ bfin_write_PINT0_REQUEST | |
2641 | #define bfin_read_PINT1_IRQ bfin_read_PINT1_REQUEST | |
2642 | #define bfin_write_PINT1_IRQ bfin_write_PINT1_REQUEST | |
2643 | #define bfin_read_PINT2_IRQ bfin_read_PINT2_REQUEST | |
2644 | #define bfin_write_PINT2_IRQ bfin_write_PINT2_REQUEST | |
2645 | #define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST | |
2646 | #define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST | |
2647 | ||
53442e1c | 2648 | /* These need to be last due to the cdef/linux inter-dependencies */ |
b6070576 | 2649 | #include <asm/irq.h> |
53442e1c | 2650 | |
19381f02 BW |
2651 | #endif /* _CDEF_BF54X_H */ |
2652 |