[deliverable/linux.git] / arch / blackfin / mach-bf561 / boards / cm_bf561.c

/*
 * File:         arch/blackfin/mach-bf533/boards/cm_bf561.c
 * Based on:     arch/blackfin/mach-bf533/boards/ezkit.c
 * Author:       Aidan Williams <aidan@nicta.com.au> Copyright 2005
 *
 * Created:      2006
 * Description:  Board description file
 *
 * Modified:
 *               Copyright 2004-2006 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb/isp1362.h>
#endif
#include <linux/ata_platform.h>
#include <linux/irq.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>

/*
 * Name the Board for the /proc/cpuinfo
 */
const char bfin_board_name[] = "Bluetechnix CM BF561";

#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* all SPI peripherals info goes here */

#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
static struct mtd_partition bfin_spi_flash_partitions[] = {
	{
		.name = "bootloader(spi)",
		.size = 0x00020000,
		.offset = 0,
		.mask_flags = MTD_CAP_ROM
	}, {
		.name = "linux kernel(spi)",
		.size = 0xe0000,
		.offset = 0x20000
	}, {
		.name = "file system(spi)",
		.size = 0x700000,
		.offset = 0x00100000,
	}
};

static struct flash_platform_data bfin_spi_flash_data = {
	.name = "m25p80",
	.parts = bfin_spi_flash_partitions,
	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
	.type = "m25p64",
};

/* SPI flash chip (m25p64) */
static struct bfin5xx_spi_chip spi_flash_chip_info = {
	.enable_dma = 0,         /* use dma transfer with this chip*/
	.bits_per_word = 8,
};
#endif

#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
	.enable_dma = 1,         /* use dma transfer with this chip*/
	.bits_per_word = 16,
};
#endif

#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
	.enable_dma = 0,
	.bits_per_word = 16,
};
#endif

#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
	.enable_dma = 0,
	.bits_per_word = 16,
};
#endif

#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
static struct bfin5xx_spi_chip mmc_spi_chip_info = {
	.enable_dma = 0,
	.bits_per_word = 8,
};
#endif

static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
	{
		/* the modalias must be the same as spi device driver name */
		.modalias = "m25p80", /* Name of spi_driver for this device */
		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0, /* Framework bus number */
		.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
		.platform_data = &bfin_spi_flash_data,
		.controller_data = &spi_flash_chip_info,
		.mode = SPI_MODE_3,
	},
#endif

#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
	{
		.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
		.max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0, /* Framework bus number */
		.chip_select = 1, /* Framework chip select. */
		.platform_data = NULL, /* No spi_driver specific config */
		.controller_data = &spi_adc_chip_info,
	},
#endif

#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
	{
		.modalias = "ad1836-spi",
		.max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
		.controller_data = &ad1836_spi_chip_info,
	},
#endif
#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
	{
		.modalias = "ad9960-spi",
		.max_speed_hz = 10000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = 1,
		.controller_data = &ad9960_spi_chip_info,
	},
#endif
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
	{
		.modalias = "mmc_spi",
		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
		.bus_num = 0,
		.chip_select = 5,
		.controller_data = &mmc_spi_chip_info,
		.mode = SPI_MODE_3,
	},
#endif
};

/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
	[0] = {
		.start = SPI0_REGBASE,
		.end   = SPI0_REGBASE + 0xFF,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = CH_SPI,
		.end   = CH_SPI,
		.flags = IORESOURCE_IRQ,
	}
};

/* SPI controller data */
static struct bfin5xx_spi_master bfin_spi0_info = {
	.num_chipselect = 8,
	.enable_dma = 1,  /* master has the ability to do dma transfer */
	.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};

static struct platform_device bfin_spi0_device = {
	.name = "bfin-spi",
	.id = 0, /* Bus number */
	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
	.resource = bfin_spi0_resource,
	.dev = {
		.platform_data = &bfin_spi0_info, /* Passed to driver */
	},
};
#endif  /* spi master and devices */


#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
static struct platform_device hitachi_fb_device = {
	.name = "hitachi-tx09",
};
#endif


#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)

static struct resource smc91x_resources[] = {
	{
		.name = "smc91x-regs",
		.start = 0x28000300,
		.end = 0x28000300 + 16,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IRQ_PF0,
		.end = IRQ_PF0,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};
static struct platform_device smc91x_device = {
	.name = "smc91x",
	.id = 0,
	.num_resources = ARRAY_SIZE(smc91x_resources),
	.resource = smc91x_resources,
};
#endif

static struct resource bfin_gpios_resources = {
	.start = 0,
	.end   = MAX_BLACKFIN_GPIOS - 1,
	.flags = IORESOURCE_IRQ,
};

static struct platform_device bfin_gpios_device = {
	.name = "simple-gpio",
	.id = -1,
	.num_resources = 1,
	.resource = &bfin_gpios_resources,
};

#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
static struct resource isp1362_hcd_resources[] = {
	{
		.start = 0x24008000,
		.end = 0x24008000,
		.flags = IORESOURCE_MEM,
	}, {
		.start = 0x24008004,
		.end = 0x24008004,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IRQ_PF47,
		.end = IRQ_PF47,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	},
};

static struct isp1362_platform_data isp1362_priv = {
	.sel15Kres = 1,
	.clknotstop = 0,
	.oc_enable = 0,
	.int_act_high = 0,
	.int_edge_triggered = 0,
	.remote_wakeup_connected = 0,
	.no_power_switching = 1,
	.power_switching_mode = 0,
};

static struct platform_device isp1362_hcd_device = {
	.name = "isp1362-hcd",
	.id = 0,
	.dev = {
		.platform_data = &isp1362_priv,
	},
	.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
	.resource = isp1362_hcd_resources,
};
#endif

#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
static struct resource bfin_uart_resources[] = {
	{
		.start = 0xFFC00400,
		.end = 0xFFC004FF,
		.flags = IORESOURCE_MEM,
	},
};

static struct platform_device bfin_uart_device = {
	.name = "bfin-uart",
	.id = 1,
	.num_resources = ARRAY_SIZE(bfin_uart_resources),
	.resource = bfin_uart_resources,
};
#endif

#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
#ifdef CONFIG_BFIN_SIR0
static struct resource bfin_sir0_resources[] = {
	{
		.start = 0xFFC00400,
		.end = 0xFFC004FF,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_UART0_RX,
		.end = IRQ_UART0_RX+1,
		.flags = IORESOURCE_IRQ,
	},
	{
		.start = CH_UART0_RX,
		.end = CH_UART0_RX+1,
		.flags = IORESOURCE_DMA,
	},
};

static struct platform_device bfin_sir0_device = {
	.name = "bfin_sir",
	.id = 0,
	.num_resources = ARRAY_SIZE(bfin_sir0_resources),
	.resource = bfin_sir0_resources,
};
#endif
#endif

#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
#define PATA_INT	IRQ_PF46

static struct pata_platform_info bfin_pata_platform_data = {
	.ioport_shift = 2,
	.irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
};

static struct resource bfin_pata_resources[] = {
	{
		.start = 0x2400C000,
		.end = 0x2400C001F,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = 0x2400D018,
		.end = 0x2400D01B,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = PATA_INT,
		.end = PATA_INT,
		.flags = IORESOURCE_IRQ,
	},
};

static struct platform_device bfin_pata_device = {
	.name = "pata_platform",
	.id = -1,
	.num_resources = ARRAY_SIZE(bfin_pata_resources),
	.resource = bfin_pata_resources,
	.dev = {
		.platform_data = &bfin_pata_platform_data,
	}
};
#endif

static const unsigned int cclk_vlev_datasheet[] =
{
	VRPAIR(VLEV_085, 250000000),
	VRPAIR(VLEV_090, 300000000),
	VRPAIR(VLEV_095, 313000000),
	VRPAIR(VLEV_100, 350000000),
	VRPAIR(VLEV_105, 400000000),
	VRPAIR(VLEV_110, 444000000),
	VRPAIR(VLEV_115, 450000000),
	VRPAIR(VLEV_120, 475000000),
	VRPAIR(VLEV_125, 500000000),
	VRPAIR(VLEV_130, 600000000),
};

static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
	.tuple_tab = cclk_vlev_datasheet,
	.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
	.vr_settling_time = 25 /* us */,
};

static struct platform_device bfin_dpmc = {
	.name = "bfin dpmc",
	.dev = {
		.platform_data = &bfin_dmpc_vreg_data,
	},
};

static struct platform_device *cm_bf561_devices[] __initdata = {

	&bfin_dpmc,

#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
	&hitachi_fb_device,
#endif

#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
	&bfin_uart_device,
#endif

#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
#ifdef CONFIG_BFIN_SIR0
	&bfin_sir0_device,
#endif
#endif

#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
	&isp1362_hcd_device,
#endif

#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
	&smc91x_device,
#endif

#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
	&bfin_spi0_device,
#endif

#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
	&bfin_pata_device,
#endif

	&bfin_gpios_device,
};

static int __init cm_bf561_init(void)
{
	printk(KERN_INFO "%s(): registering device resources\n", __func__);
	platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices));
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
#endif

#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
	irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
#endif
	return 0;
}

arch_initcall(cm_bf561_init);
Commit	Line	Data
1394f032 BW	1	/*
	2	* File: arch/blackfin/mach-bf533/boards/cm_bf561.c
	3	* Based on: arch/blackfin/mach-bf533/boards/ezkit.c
d2d50aa9	4	* Author: Aidan Williams <aidan@nicta.com.au> Copyright 2005
1394f032 BW	5	*
	6	* Created: 2006
	7	* Description: Board description file
	8	*
	9	* Modified:
	10	* Copyright 2004-2006 Analog Devices Inc.
	11	*
	12	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	13	*
	14	* This program is free software; you can redistribute it and/or modify
	15	* it under the terms of the GNU General Public License as published by
	16	* the Free Software Foundation; either version 2 of the License, or
	17	* (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, see the file COPYING, or write
	26	* to the Free Software Foundation, Inc.,
	27	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	28	*/
	29
	30	#include <linux/device.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/mtd/mtd.h>
	33	#include <linux/mtd/partitions.h>
	34	#include <linux/spi/spi.h>
	35	#include <linux/spi/flash.h>
b964c592	36	#if defined(CONFIG_USB_ISP1362_HCD) \|\| defined(CONFIG_USB_ISP1362_HCD_MODULE)
f02bcec5	37	#include <linux/usb/isp1362.h>
b964c592	38	#endif
0a87e3e9	39	#include <linux/ata_platform.h>
1f83b8f1	40	#include <linux/irq.h>
c6c4d7bb	41	#include <asm/dma.h>
1394f032	42	#include <asm/bfin5xx_spi.h>
5d448dd5	43	#include <asm/portmux.h>
14b03204	44	#include <asm/dpmc.h>
1394f032 BW	45
	46	/*
	47	* Name the Board for the /proc/cpuinfo
	48	*/
066954a3	49	const char bfin_board_name[] = "Bluetechnix CM BF561";
1394f032 BW	50
1394f032 BW	51	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
d2d50aa9	52	/* all SPI peripherals info goes here */
1394f032 BW	53
	54	#if defined(CONFIG_MTD_M25P80) \|\| defined(CONFIG_MTD_M25P80_MODULE)
	55	static struct mtd_partition bfin_spi_flash_partitions[] = {
	56	{
aa582977	57	.name = "bootloader(spi)",
1394f032 BW	58	.size = 0x00020000,
	59	.offset = 0,
	60	.mask_flags = MTD_CAP_ROM
1f83b8f1	61	}, {
aa582977	62	.name = "linux kernel(spi)",
1394f032 BW	63	.size = 0xe0000,
1394f032 BW	64	.offset = 0x20000
1f83b8f1	65	}, {
aa582977	66	.name = "file system(spi)",
1394f032 BW	67	.size = 0x700000,
	68	.offset = 0x00100000,
	69	}
	70	};
	71
	72	static struct flash_platform_data bfin_spi_flash_data = {
	73	.name = "m25p80",
	74	.parts = bfin_spi_flash_partitions,
	75	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
	76	.type = "m25p64",
	77	};
	78
	79	/* SPI flash chip (m25p64) */
	80	static struct bfin5xx_spi_chip spi_flash_chip_info = {
	81	.enable_dma = 0, /* use dma transfer with this chip*/
	82	.bits_per_word = 8,
	83	};
	84	#endif
	85
	86	#if defined(CONFIG_SPI_ADC_BF533) \|\| defined(CONFIG_SPI_ADC_BF533_MODULE)
	87	/* SPI ADC chip */
	88	static struct bfin5xx_spi_chip spi_adc_chip_info = {
	89	.enable_dma = 1, /* use dma transfer with this chip*/
	90	.bits_per_word = 16,
	91	};
	92	#endif
	93
	94	#if defined(CONFIG_SND_BLACKFIN_AD1836) \|\| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
	95	static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
	96	.enable_dma = 0,
	97	.bits_per_word = 16,
	98	};
	99	#endif
	100
	101	#if defined(CONFIG_AD9960) \|\| defined(CONFIG_AD9960_MODULE)
	102	static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
	103	.enable_dma = 0,
	104	.bits_per_word = 16,
	105	};
	106	#endif
	107
f3f704d3 MH	108	#if defined(CONFIG_MMC_SPI) \|\| defined(CONFIG_MMC_SPI_MODULE)
	109	static struct bfin5xx_spi_chip mmc_spi_chip_info = {
	110	.enable_dma = 0,
1394f032 BW	111	.bits_per_word = 8,
	112	};
	113	#endif
	114
	115	static struct spi_board_info bfin_spi_board_info[] __initdata = {
	116	#if defined(CONFIG_MTD_M25P80) \|\| defined(CONFIG_MTD_M25P80_MODULE)
	117	{
	118	/* the modalias must be the same as spi device driver name */
	119	.modalias = "m25p80", /* Name of spi_driver for this device */
	120	.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	121	.bus_num = 0, /* Framework bus number */
1394f032 BW	122	.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
	123	.platform_data = &bfin_spi_flash_data,
	124	.controller_data = &spi_flash_chip_info,
	125	.mode = SPI_MODE_3,
	126	},
	127	#endif
	128
	129	#if defined(CONFIG_SPI_ADC_BF533) \|\| defined(CONFIG_SPI_ADC_BF533_MODULE)
	130	{
	131	.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
	132	.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	133	.bus_num = 0, /* Framework bus number */
1394f032 BW	134	.chip_select = 1, /* Framework chip select. */
	135	.platform_data = NULL, /* No spi_driver specific config */
	136	.controller_data = &spi_adc_chip_info,
	137	},
	138	#endif
	139
	140	#if defined(CONFIG_SND_BLACKFIN_AD1836) \|\| defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
	141	{
	142	.modalias = "ad1836-spi",
	143	.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	144	.bus_num = 0,
1394f032 BW	145	.chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
	146	.controller_data = &ad1836_spi_chip_info,
	147	},
	148	#endif
	149	#if defined(CONFIG_AD9960) \|\| defined(CONFIG_AD9960_MODULE)
	150	{
	151	.modalias = "ad9960-spi",
	152	.max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	153	.bus_num = 0,
1394f032 BW	154	.chip_select = 1,
	155	.controller_data = &ad9960_spi_chip_info,
	156	},
	157	#endif
f3f704d3	158	#if defined(CONFIG_MMC_SPI) \|\| defined(CONFIG_MMC_SPI_MODULE)
1394f032	159	{
f3f704d3	160	.modalias = "mmc_spi",
1394f032	161	.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
c6c4d7bb	162	.bus_num = 0,
f3f704d3 MH	163	.chip_select = 5,
f3f704d3 MH	164	.controller_data = &mmc_spi_chip_info,
1394f032 BW	165	.mode = SPI_MODE_3,
	166	},
	167	#endif
	168	};
	169
c6c4d7bb BW	170	/* SPI (0) */
	171	static struct resource bfin_spi0_resource[] = {
	172	[0] = {
	173	.start = SPI0_REGBASE,
	174	.end = SPI0_REGBASE + 0xFF,
	175	.flags = IORESOURCE_MEM,
	176	},
	177	[1] = {
	178	.start = CH_SPI,
	179	.end = CH_SPI,
	180	.flags = IORESOURCE_IRQ,
	181	}
	182	};
	183
1394f032	184	/* SPI controller data */
c6c4d7bb	185	static struct bfin5xx_spi_master bfin_spi0_info = {
1394f032 BW	186	.num_chipselect = 8,
1394f032 BW	187	.enable_dma = 1, /* master has the ability to do dma transfer */
5d448dd5	188	.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1394f032 BW	189	};
1394f032 BW	190
c6c4d7bb BW	191	static struct platform_device bfin_spi0_device = {
	192	.name = "bfin-spi",
	193	.id = 0, /* Bus number */
	194	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
	195	.resource = bfin_spi0_resource,
1394f032	196	.dev = {
c6c4d7bb	197	.platform_data = &bfin_spi0_info, /* Passed to driver */
1394f032 BW	198	},
	199	};
	200	#endif /* spi master and devices */
	201
	202
0d4a89bb MH	203	#if defined(CONFIG_FB_HITACHI_TX09) \|\| defined(CONFIG_FB_HITACHI_TX09_MODULE)
	204	static struct platform_device hitachi_fb_device = {
	205	.name = "hitachi-tx09",
	206	};
	207	#endif
	208
	209
1394f032 BW	210	#if defined(CONFIG_SMC91X) \|\| defined(CONFIG_SMC91X_MODULE)
	211
	212	static struct resource smc91x_resources[] = {
	213	{
	214	.name = "smc91x-regs",
	215	.start = 0x28000300,
	216	.end = 0x28000300 + 16,
	217	.flags = IORESOURCE_MEM,
1f83b8f1	218	}, {
1394f032 BW	219	.start = IRQ_PF0,
	220	.end = IRQ_PF0,
	221	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
	222	},
	223	};
	224	static struct platform_device smc91x_device = {
	225	.name = "smc91x",
	226	.id = 0,
	227	.num_resources = ARRAY_SIZE(smc91x_resources),
	228	.resource = smc91x_resources,
	229	};
	230	#endif
	231
c97618d3 MF	232	static struct resource bfin_gpios_resources = {
	233	.start = 0,
	234	.end = MAX_BLACKFIN_GPIOS - 1,
	235	.flags = IORESOURCE_IRQ,
	236	};
	237
	238	static struct platform_device bfin_gpios_device = {
	239	.name = "simple-gpio",
	240	.id = -1,
	241	.num_resources = 1,
	242	.resource = &bfin_gpios_resources,
	243	};
	244
1394f032 BW	245	#if defined(CONFIG_USB_ISP1362_HCD) \|\| defined(CONFIG_USB_ISP1362_HCD_MODULE)
	246	static struct resource isp1362_hcd_resources[] = {
	247	{
	248	.start = 0x24008000,
	249	.end = 0x24008000,
	250	.flags = IORESOURCE_MEM,
1f83b8f1	251	}, {
1394f032 BW	252	.start = 0x24008004,
	253	.end = 0x24008004,
	254	.flags = IORESOURCE_MEM,
1f83b8f1	255	}, {
1394f032 BW	256	.start = IRQ_PF47,
	257	.end = IRQ_PF47,
	258	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
	259	},
	260	};
	261
	262	static struct isp1362_platform_data isp1362_priv = {
	263	.sel15Kres = 1,
	264	.clknotstop = 0,
	265	.oc_enable = 0,
	266	.int_act_high = 0,
	267	.int_edge_triggered = 0,
	268	.remote_wakeup_connected = 0,
	269	.no_power_switching = 1,
	270	.power_switching_mode = 0,
	271	};
	272
	273	static struct platform_device isp1362_hcd_device = {
	274	.name = "isp1362-hcd",
	275	.id = 0,
	276	.dev = {
	277	.platform_data = &isp1362_priv,
	278	},
	279	.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
	280	.resource = isp1362_hcd_resources,
	281	};
	282	#endif
	283
	284	#if defined(CONFIG_SERIAL_BFIN) \|\| defined(CONFIG_SERIAL_BFIN_MODULE)
	285	static struct resource bfin_uart_resources[] = {
1f83b8f1 MF	286	{
	287	.start = 0xFFC00400,
	288	.end = 0xFFC004FF,
	289	.flags = IORESOURCE_MEM,
	290	},
1394f032 BW	291	};
	292
	293	static struct platform_device bfin_uart_device = {
1f83b8f1 MF	294	.name = "bfin-uart",
	295	.id = 1,
	296	.num_resources = ARRAY_SIZE(bfin_uart_resources),
	297	.resource = bfin_uart_resources,
1394f032 BW	298	};
	299	#endif
	300
5be36d22	301	#if defined(CONFIG_BFIN_SIR) \|\| defined(CONFIG_BFIN_SIR_MODULE)
5be36d22	302	#ifdef CONFIG_BFIN_SIR0
42bd8bcb	303	static struct resource bfin_sir0_resources[] = {
5be36d22 GY	304	{
	305	.start = 0xFFC00400,
	306	.end = 0xFFC004FF,
	307	.flags = IORESOURCE_MEM,
	308	},
42bd8bcb GY	309	{
	310	.start = IRQ_UART0_RX,
	311	.end = IRQ_UART0_RX+1,
	312	.flags = IORESOURCE_IRQ,
	313	},
	314	{
	315	.start = CH_UART0_RX,
	316	.end = CH_UART0_RX+1,
	317	.flags = IORESOURCE_DMA,
	318	},
5be36d22 GY	319	};
5be36d22 GY	320
42bd8bcb	321	static struct platform_device bfin_sir0_device = {
5be36d22 GY	322	.name = "bfin_sir",
5be36d22 GY	323	.id = 0,
42bd8bcb GY	324	.num_resources = ARRAY_SIZE(bfin_sir0_resources),
42bd8bcb GY	325	.resource = bfin_sir0_resources,
5be36d22 GY	326	};
5be36d22 GY	327	#endif
42bd8bcb	328	#endif
5be36d22	329
c6c4d7bb	330	#if defined(CONFIG_PATA_PLATFORM) \|\| defined(CONFIG_PATA_PLATFORM_MODULE)
fe5aeb93	331	#define PATA_INT IRQ_PF46
c6c4d7bb BW	332
	333	static struct pata_platform_info bfin_pata_platform_data = {
	334	.ioport_shift = 2,
	335	.irq_type = IRQF_TRIGGER_HIGH \| IRQF_DISABLED,
	336	};
	337
	338	static struct resource bfin_pata_resources[] = {
	339	{
	340	.start = 0x2400C000,
	341	.end = 0x2400C001F,
	342	.flags = IORESOURCE_MEM,
	343	},
	344	{
	345	.start = 0x2400D018,
	346	.end = 0x2400D01B,
	347	.flags = IORESOURCE_MEM,
	348	},
	349	{
	350	.start = PATA_INT,
	351	.end = PATA_INT,
	352	.flags = IORESOURCE_IRQ,
	353	},
	354	};
	355
	356	static struct platform_device bfin_pata_device = {
	357	.name = "pata_platform",
	358	.id = -1,
	359	.num_resources = ARRAY_SIZE(bfin_pata_resources),
	360	.resource = bfin_pata_resources,
	361	.dev = {
	362	.platform_data = &bfin_pata_platform_data,
	363	}
	364	};
	365	#endif
	366
14b03204 MH	367	static const unsigned int cclk_vlev_datasheet[] =
	368	{
	369	VRPAIR(VLEV_085, 250000000),
	370	VRPAIR(VLEV_090, 300000000),
	371	VRPAIR(VLEV_095, 313000000),
	372	VRPAIR(VLEV_100, 350000000),
	373	VRPAIR(VLEV_105, 400000000),
	374	VRPAIR(VLEV_110, 444000000),
	375	VRPAIR(VLEV_115, 450000000),
	376	VRPAIR(VLEV_120, 475000000),
	377	VRPAIR(VLEV_125, 500000000),
	378	VRPAIR(VLEV_130, 600000000),
	379	};
	380
	381	static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
	382	.tuple_tab = cclk_vlev_datasheet,
	383	.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
	384	.vr_settling_time = 25 /* us */,
	385	};
	386
	387	static struct platform_device bfin_dpmc = {
	388	.name = "bfin dpmc",
	389	.dev = {
	390	.platform_data = &bfin_dmpc_vreg_data,
	391	},
	392	};
	393
1394f032 BW	394	static struct platform_device *cm_bf561_devices[] __initdata = {
1394f032 BW	395
14b03204 MH	396	&bfin_dpmc,
14b03204 MH	397
0d4a89bb MH	398	#if defined(CONFIG_FB_HITACHI_TX09) \|\| defined(CONFIG_FB_HITACHI_TX09_MODULE)
	399	&hitachi_fb_device,
	400	#endif
	401
1394f032	402	#if defined(CONFIG_SERIAL_BFIN) \|\| defined(CONFIG_SERIAL_BFIN_MODULE)
1f83b8f1	403	&bfin_uart_device,
1394f032 BW	404	#endif
1394f032 BW	405
5be36d22	406	#if defined(CONFIG_BFIN_SIR) \|\| defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb GY	407	#ifdef CONFIG_BFIN_SIR0
	408	&bfin_sir0_device,
	409	#endif
5be36d22 GY	410	#endif
5be36d22 GY	411
1394f032 BW	412	#if defined(CONFIG_USB_ISP1362_HCD) \|\| defined(CONFIG_USB_ISP1362_HCD_MODULE)
	413	&isp1362_hcd_device,
	414	#endif
	415
	416	#if defined(CONFIG_SMC91X) \|\| defined(CONFIG_SMC91X_MODULE)
	417	&smc91x_device,
	418	#endif
	419
	420	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
c6c4d7bb	421	&bfin_spi0_device,
1394f032 BW	422	#endif
1394f032 BW	423
c6c4d7bb BW	424	#if defined(CONFIG_PATA_PLATFORM) \|\| defined(CONFIG_PATA_PLATFORM_MODULE)
	425	&bfin_pata_device,
	426	#endif
c97618d3 MF	427
c97618d3 MF	428	&bfin_gpios_device,
1394f032 BW	429	};
	430
	431	static int __init cm_bf561_init(void)
	432	{
b85d858b	433	printk(KERN_INFO "%s(): registering device resources\n", __func__);
1394f032 BW	434	platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices));
	435	#if defined(CONFIG_SPI_BFIN) \|\| defined(CONFIG_SPI_BFIN_MODULE)
	436	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
	437	#endif
c6c4d7bb BW	438
	439	#if defined(CONFIG_PATA_PLATFORM) \|\| defined(CONFIG_PATA_PLATFORM_MODULE)
	440	irq_desc[PATA_INT].status \|= IRQ_NOAUTOEN;
	441	#endif
1394f032 BW	442	return 0;
	443	}
	444
	445	arch_initcall(cm_bf561_init);