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1394f032 BW |
1 | /* |
2 | * File: arch/blackfin/mach-bf533/boards/cm_bf561.c | |
3 | * Based on: arch/blackfin/mach-bf533/boards/ezkit.c | |
d2d50aa9 | 4 | * Author: Aidan Williams <aidan@nicta.com.au> Copyright 2005 |
1394f032 BW |
5 | * |
6 | * Created: 2006 | |
7 | * Description: Board description file | |
8 | * | |
9 | * Modified: | |
10 | * Copyright 2004-2006 Analog Devices Inc. | |
11 | * | |
12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, see the file COPYING, or write | |
26 | * to the Free Software Foundation, Inc., | |
27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
28 | */ | |
29 | ||
30 | #include <linux/device.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/mtd/mtd.h> | |
33 | #include <linux/mtd/partitions.h> | |
34 | #include <linux/spi/spi.h> | |
35 | #include <linux/spi/flash.h> | |
b964c592 | 36 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
f02bcec5 | 37 | #include <linux/usb/isp1362.h> |
b964c592 | 38 | #endif |
0a87e3e9 | 39 | #include <linux/ata_platform.h> |
1f83b8f1 | 40 | #include <linux/irq.h> |
c6c4d7bb | 41 | #include <asm/dma.h> |
1394f032 | 42 | #include <asm/bfin5xx_spi.h> |
5d448dd5 | 43 | #include <asm/portmux.h> |
14b03204 | 44 | #include <asm/dpmc.h> |
1394f032 BW |
45 | |
46 | /* | |
47 | * Name the Board for the /proc/cpuinfo | |
48 | */ | |
066954a3 | 49 | const char bfin_board_name[] = "Bluetechnix CM BF561"; |
1394f032 BW |
50 | |
51 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
d2d50aa9 | 52 | /* all SPI peripherals info goes here */ |
1394f032 BW |
53 | |
54 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | |
55 | static struct mtd_partition bfin_spi_flash_partitions[] = { | |
56 | { | |
aa582977 | 57 | .name = "bootloader(spi)", |
1394f032 BW |
58 | .size = 0x00020000, |
59 | .offset = 0, | |
60 | .mask_flags = MTD_CAP_ROM | |
1f83b8f1 | 61 | }, { |
aa582977 | 62 | .name = "linux kernel(spi)", |
1394f032 BW |
63 | .size = 0xe0000, |
64 | .offset = 0x20000 | |
1f83b8f1 | 65 | }, { |
aa582977 | 66 | .name = "file system(spi)", |
1394f032 BW |
67 | .size = 0x700000, |
68 | .offset = 0x00100000, | |
69 | } | |
70 | }; | |
71 | ||
72 | static struct flash_platform_data bfin_spi_flash_data = { | |
73 | .name = "m25p80", | |
74 | .parts = bfin_spi_flash_partitions, | |
75 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | |
76 | .type = "m25p64", | |
77 | }; | |
78 | ||
79 | /* SPI flash chip (m25p64) */ | |
80 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | |
81 | .enable_dma = 0, /* use dma transfer with this chip*/ | |
82 | .bits_per_word = 8, | |
83 | }; | |
84 | #endif | |
85 | ||
a261eec0 | 86 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
1394f032 BW |
87 | /* SPI ADC chip */ |
88 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | |
89 | .enable_dma = 1, /* use dma transfer with this chip*/ | |
90 | .bits_per_word = 16, | |
91 | }; | |
92 | #endif | |
93 | ||
94 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | |
95 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |
96 | .enable_dma = 0, | |
97 | .bits_per_word = 16, | |
98 | }; | |
99 | #endif | |
100 | ||
f3f704d3 MH |
101 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
102 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { | |
103 | .enable_dma = 0, | |
1394f032 BW |
104 | .bits_per_word = 8, |
105 | }; | |
106 | #endif | |
107 | ||
108 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | |
109 | #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) | |
110 | { | |
111 | /* the modalias must be the same as spi device driver name */ | |
112 | .modalias = "m25p80", /* Name of spi_driver for this device */ | |
113 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 114 | .bus_num = 0, /* Framework bus number */ |
1394f032 BW |
115 | .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ |
116 | .platform_data = &bfin_spi_flash_data, | |
117 | .controller_data = &spi_flash_chip_info, | |
118 | .mode = SPI_MODE_3, | |
119 | }, | |
120 | #endif | |
121 | ||
a261eec0 | 122 | #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) |
1394f032 BW |
123 | { |
124 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | |
125 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | |
c6c4d7bb | 126 | .bus_num = 0, /* Framework bus number */ |
1394f032 BW |
127 | .chip_select = 1, /* Framework chip select. */ |
128 | .platform_data = NULL, /* No spi_driver specific config */ | |
129 | .controller_data = &spi_adc_chip_info, | |
130 | }, | |
131 | #endif | |
132 | ||
133 | #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | |
134 | { | |
dac98174 | 135 | .modalias = "ad1836", |
1394f032 | 136 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ |
c6c4d7bb | 137 | .bus_num = 0, |
1394f032 BW |
138 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, |
139 | .controller_data = &ad1836_spi_chip_info, | |
140 | }, | |
141 | #endif | |
f3f704d3 | 142 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
1394f032 | 143 | { |
f3f704d3 | 144 | .modalias = "mmc_spi", |
1394f032 | 145 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
c6c4d7bb | 146 | .bus_num = 0, |
f3f704d3 MH |
147 | .chip_select = 5, |
148 | .controller_data = &mmc_spi_chip_info, | |
1394f032 BW |
149 | .mode = SPI_MODE_3, |
150 | }, | |
151 | #endif | |
152 | }; | |
153 | ||
c6c4d7bb BW |
154 | /* SPI (0) */ |
155 | static struct resource bfin_spi0_resource[] = { | |
156 | [0] = { | |
157 | .start = SPI0_REGBASE, | |
158 | .end = SPI0_REGBASE + 0xFF, | |
159 | .flags = IORESOURCE_MEM, | |
160 | }, | |
161 | [1] = { | |
162 | .start = CH_SPI, | |
163 | .end = CH_SPI, | |
53122693 YL |
164 | .flags = IORESOURCE_DMA, |
165 | }, | |
166 | [2] = { | |
167 | .start = IRQ_SPI, | |
168 | .end = IRQ_SPI, | |
c6c4d7bb | 169 | .flags = IORESOURCE_IRQ, |
53122693 | 170 | }, |
c6c4d7bb BW |
171 | }; |
172 | ||
1394f032 | 173 | /* SPI controller data */ |
c6c4d7bb | 174 | static struct bfin5xx_spi_master bfin_spi0_info = { |
1394f032 BW |
175 | .num_chipselect = 8, |
176 | .enable_dma = 1, /* master has the ability to do dma transfer */ | |
5d448dd5 | 177 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, |
1394f032 BW |
178 | }; |
179 | ||
c6c4d7bb BW |
180 | static struct platform_device bfin_spi0_device = { |
181 | .name = "bfin-spi", | |
182 | .id = 0, /* Bus number */ | |
183 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
184 | .resource = bfin_spi0_resource, | |
1394f032 | 185 | .dev = { |
c6c4d7bb | 186 | .platform_data = &bfin_spi0_info, /* Passed to driver */ |
1394f032 BW |
187 | }, |
188 | }; | |
189 | #endif /* spi master and devices */ | |
190 | ||
191 | ||
0d4a89bb MH |
192 | #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) |
193 | static struct platform_device hitachi_fb_device = { | |
194 | .name = "hitachi-tx09", | |
195 | }; | |
196 | #endif | |
197 | ||
198 | ||
1394f032 | 199 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
61f09b5a MH |
200 | #include <linux/smc91x.h> |
201 | ||
202 | static struct smc91x_platdata smc91x_info = { | |
203 | .flags = SMC91X_USE_32BIT | SMC91X_NOWAIT, | |
204 | .leda = RPC_LED_100_10, | |
205 | .ledb = RPC_LED_TX_RX, | |
206 | }; | |
1394f032 BW |
207 | |
208 | static struct resource smc91x_resources[] = { | |
209 | { | |
210 | .name = "smc91x-regs", | |
211 | .start = 0x28000300, | |
212 | .end = 0x28000300 + 16, | |
213 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 214 | }, { |
1394f032 BW |
215 | .start = IRQ_PF0, |
216 | .end = IRQ_PF0, | |
217 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
218 | }, | |
219 | }; | |
220 | static struct platform_device smc91x_device = { | |
221 | .name = "smc91x", | |
222 | .id = 0, | |
223 | .num_resources = ARRAY_SIZE(smc91x_resources), | |
224 | .resource = smc91x_resources, | |
61f09b5a MH |
225 | .dev = { |
226 | .platform_data = &smc91x_info, | |
227 | }, | |
1394f032 BW |
228 | }; |
229 | #endif | |
230 | ||
c97618d3 MF |
231 | static struct resource bfin_gpios_resources = { |
232 | .start = 0, | |
233 | .end = MAX_BLACKFIN_GPIOS - 1, | |
234 | .flags = IORESOURCE_IRQ, | |
235 | }; | |
236 | ||
237 | static struct platform_device bfin_gpios_device = { | |
238 | .name = "simple-gpio", | |
239 | .id = -1, | |
240 | .num_resources = 1, | |
241 | .resource = &bfin_gpios_resources, | |
242 | }; | |
243 | ||
1394f032 BW |
244 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
245 | static struct resource isp1362_hcd_resources[] = { | |
246 | { | |
247 | .start = 0x24008000, | |
248 | .end = 0x24008000, | |
249 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 250 | }, { |
1394f032 BW |
251 | .start = 0x24008004, |
252 | .end = 0x24008004, | |
253 | .flags = IORESOURCE_MEM, | |
1f83b8f1 | 254 | }, { |
1394f032 BW |
255 | .start = IRQ_PF47, |
256 | .end = IRQ_PF47, | |
257 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | |
258 | }, | |
259 | }; | |
260 | ||
261 | static struct isp1362_platform_data isp1362_priv = { | |
262 | .sel15Kres = 1, | |
263 | .clknotstop = 0, | |
264 | .oc_enable = 0, | |
265 | .int_act_high = 0, | |
266 | .int_edge_triggered = 0, | |
267 | .remote_wakeup_connected = 0, | |
268 | .no_power_switching = 1, | |
269 | .power_switching_mode = 0, | |
270 | }; | |
271 | ||
272 | static struct platform_device isp1362_hcd_device = { | |
273 | .name = "isp1362-hcd", | |
274 | .id = 0, | |
275 | .dev = { | |
276 | .platform_data = &isp1362_priv, | |
277 | }, | |
278 | .num_resources = ARRAY_SIZE(isp1362_hcd_resources), | |
279 | .resource = isp1362_hcd_resources, | |
280 | }; | |
281 | #endif | |
282 | ||
283 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
284 | static struct resource bfin_uart_resources[] = { | |
1f83b8f1 MF |
285 | { |
286 | .start = 0xFFC00400, | |
287 | .end = 0xFFC004FF, | |
288 | .flags = IORESOURCE_MEM, | |
289 | }, | |
1394f032 BW |
290 | }; |
291 | ||
292 | static struct platform_device bfin_uart_device = { | |
1f83b8f1 MF |
293 | .name = "bfin-uart", |
294 | .id = 1, | |
295 | .num_resources = ARRAY_SIZE(bfin_uart_resources), | |
296 | .resource = bfin_uart_resources, | |
1394f032 BW |
297 | }; |
298 | #endif | |
299 | ||
5be36d22 | 300 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
5be36d22 | 301 | #ifdef CONFIG_BFIN_SIR0 |
42bd8bcb | 302 | static struct resource bfin_sir0_resources[] = { |
5be36d22 GY |
303 | { |
304 | .start = 0xFFC00400, | |
305 | .end = 0xFFC004FF, | |
306 | .flags = IORESOURCE_MEM, | |
307 | }, | |
42bd8bcb GY |
308 | { |
309 | .start = IRQ_UART0_RX, | |
310 | .end = IRQ_UART0_RX+1, | |
311 | .flags = IORESOURCE_IRQ, | |
312 | }, | |
313 | { | |
314 | .start = CH_UART0_RX, | |
315 | .end = CH_UART0_RX+1, | |
316 | .flags = IORESOURCE_DMA, | |
317 | }, | |
5be36d22 GY |
318 | }; |
319 | ||
42bd8bcb | 320 | static struct platform_device bfin_sir0_device = { |
5be36d22 GY |
321 | .name = "bfin_sir", |
322 | .id = 0, | |
42bd8bcb GY |
323 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
324 | .resource = bfin_sir0_resources, | |
5be36d22 GY |
325 | }; |
326 | #endif | |
42bd8bcb | 327 | #endif |
5be36d22 | 328 | |
c6c4d7bb | 329 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) |
fe5aeb93 | 330 | #define PATA_INT IRQ_PF46 |
c6c4d7bb BW |
331 | |
332 | static struct pata_platform_info bfin_pata_platform_data = { | |
333 | .ioport_shift = 2, | |
334 | .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED, | |
335 | }; | |
336 | ||
337 | static struct resource bfin_pata_resources[] = { | |
338 | { | |
339 | .start = 0x2400C000, | |
340 | .end = 0x2400C001F, | |
341 | .flags = IORESOURCE_MEM, | |
342 | }, | |
343 | { | |
344 | .start = 0x2400D018, | |
345 | .end = 0x2400D01B, | |
346 | .flags = IORESOURCE_MEM, | |
347 | }, | |
348 | { | |
349 | .start = PATA_INT, | |
350 | .end = PATA_INT, | |
351 | .flags = IORESOURCE_IRQ, | |
352 | }, | |
353 | }; | |
354 | ||
355 | static struct platform_device bfin_pata_device = { | |
356 | .name = "pata_platform", | |
357 | .id = -1, | |
358 | .num_resources = ARRAY_SIZE(bfin_pata_resources), | |
359 | .resource = bfin_pata_resources, | |
360 | .dev = { | |
361 | .platform_data = &bfin_pata_platform_data, | |
362 | } | |
363 | }; | |
364 | #endif | |
365 | ||
14b03204 MH |
366 | static const unsigned int cclk_vlev_datasheet[] = |
367 | { | |
368 | VRPAIR(VLEV_085, 250000000), | |
369 | VRPAIR(VLEV_090, 300000000), | |
370 | VRPAIR(VLEV_095, 313000000), | |
371 | VRPAIR(VLEV_100, 350000000), | |
372 | VRPAIR(VLEV_105, 400000000), | |
373 | VRPAIR(VLEV_110, 444000000), | |
374 | VRPAIR(VLEV_115, 450000000), | |
375 | VRPAIR(VLEV_120, 475000000), | |
376 | VRPAIR(VLEV_125, 500000000), | |
377 | VRPAIR(VLEV_130, 600000000), | |
378 | }; | |
379 | ||
380 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | |
381 | .tuple_tab = cclk_vlev_datasheet, | |
382 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | |
383 | .vr_settling_time = 25 /* us */, | |
384 | }; | |
385 | ||
386 | static struct platform_device bfin_dpmc = { | |
387 | .name = "bfin dpmc", | |
388 | .dev = { | |
389 | .platform_data = &bfin_dmpc_vreg_data, | |
390 | }, | |
391 | }; | |
392 | ||
1394f032 BW |
393 | static struct platform_device *cm_bf561_devices[] __initdata = { |
394 | ||
14b03204 MH |
395 | &bfin_dpmc, |
396 | ||
0d4a89bb MH |
397 | #if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) |
398 | &hitachi_fb_device, | |
399 | #endif | |
400 | ||
1394f032 | 401 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
1f83b8f1 | 402 | &bfin_uart_device, |
1394f032 BW |
403 | #endif |
404 | ||
5be36d22 | 405 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
42bd8bcb GY |
406 | #ifdef CONFIG_BFIN_SIR0 |
407 | &bfin_sir0_device, | |
408 | #endif | |
5be36d22 GY |
409 | #endif |
410 | ||
1394f032 BW |
411 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
412 | &isp1362_hcd_device, | |
413 | #endif | |
414 | ||
415 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | |
416 | &smc91x_device, | |
417 | #endif | |
418 | ||
419 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
c6c4d7bb | 420 | &bfin_spi0_device, |
1394f032 BW |
421 | #endif |
422 | ||
c6c4d7bb BW |
423 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) |
424 | &bfin_pata_device, | |
425 | #endif | |
c97618d3 MF |
426 | |
427 | &bfin_gpios_device, | |
1394f032 BW |
428 | }; |
429 | ||
430 | static int __init cm_bf561_init(void) | |
431 | { | |
b85d858b | 432 | printk(KERN_INFO "%s(): registering device resources\n", __func__); |
1394f032 BW |
433 | platform_add_devices(cm_bf561_devices, ARRAY_SIZE(cm_bf561_devices)); |
434 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
435 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); | |
436 | #endif | |
c6c4d7bb BW |
437 | |
438 | #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) | |
439 | irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; | |
440 | #endif | |
1394f032 BW |
441 | return 0; |
442 | } | |
443 | ||
444 | arch_initcall(cm_bf561_init); |