Commit | Line | Data |
---|---|---|
c8f36dc3 | 1 | /* Load firmware into Core B on a BF561 |
1394f032 | 2 | * |
c8f36dc3 MF |
3 | * Copyright 2004-2009 Analog Devices Inc. |
4 | * Licensed under the GPL-2 or later. | |
5 | */ | |
6 | ||
7 | /* The Core B reset func requires code in the application that is loaded into | |
8 | * Core B. In order to reset, the application needs to install an interrupt | |
9 | * handler for Supplemental Interrupt 0, that sets RETI to 0xff600000 and | |
10 | * writes bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. This causes Core | |
11 | * B to stall when Supplemental Interrupt 0 is set, and will reset PC to | |
12 | * 0xff600000 when COREB_SRAM_INIT is cleared. | |
1394f032 BW |
13 | */ |
14 | ||
1394f032 | 15 | #include <linux/device.h> |
76a7f404 | 16 | #include <linux/fs.h> |
c8f36dc3 MF |
17 | #include <linux/kernel.h> |
18 | #include <linux/miscdevice.h> | |
19 | #include <linux/module.h> | |
1394f032 | 20 | |
7696eecf MF |
21 | #define CMD_COREB_START _IO('b', 0) |
22 | #define CMD_COREB_STOP _IO('b', 1) | |
23 | #define CMD_COREB_RESET _IO('b', 2) | |
1394f032 | 24 | |
17a1b5e3 MF |
25 | static long |
26 | coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
1394f032 | 27 | { |
c8f36dc3 | 28 | int ret = 0; |
1394f032 BW |
29 | |
30 | switch (cmd) { | |
1394f032 | 31 | case CMD_COREB_START: |
39c99969 | 32 | bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020); |
1394f032 | 33 | break; |
1394f032 | 34 | case CMD_COREB_STOP: |
39c99969 | 35 | bfin_write_SYSCR(bfin_read_SYSCR() | 0x0020); |
1394f032 | 36 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); |
1394f032 BW |
37 | break; |
38 | case CMD_COREB_RESET: | |
1394f032 BW |
39 | bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | 0x0080); |
40 | break; | |
c8f36dc3 MF |
41 | default: |
42 | ret = -EINVAL; | |
43 | break; | |
1394f032 BW |
44 | } |
45 | ||
c8f36dc3 MF |
46 | CSYNC(); |
47 | ||
48 | return ret; | |
1394f032 BW |
49 | } |
50 | ||
828c0950 | 51 | static const struct file_operations coreb_fops = { |
17a1b5e3 MF |
52 | .owner = THIS_MODULE, |
53 | .unlocked_ioctl = coreb_ioctl, | |
6038f373 | 54 | .llseek = noop_llseek, |
1394f032 BW |
55 | }; |
56 | ||
57 | static struct miscdevice coreb_dev = { | |
c8f36dc3 MF |
58 | .minor = MISC_DYNAMIC_MINOR, |
59 | .name = "coreb", | |
60 | .fops = &coreb_fops, | |
1394f032 BW |
61 | }; |
62 | ||
c8f36dc3 | 63 | static int __init bf561_coreb_init(void) |
1394f032 | 64 | { |
c8f36dc3 | 65 | return misc_register(&coreb_dev); |
1394f032 | 66 | } |
c8f36dc3 | 67 | module_init(bf561_coreb_init); |
1394f032 | 68 | |
c8f36dc3 | 69 | static void __exit bf561_coreb_exit(void) |
1394f032 | 70 | { |
1394f032 | 71 | misc_deregister(&coreb_dev); |
1394f032 | 72 | } |
1394f032 BW |
73 | module_exit(bf561_coreb_exit); |
74 | ||
75 | MODULE_AUTHOR("Bas Vermeulen <bvermeul@blackstar.xs4all.nl>"); | |
76 | MODULE_DESCRIPTION("BF561 Core B Support"); | |
6cf4d0fa | 77 | MODULE_LICENSE("GPL"); |