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pm: bf609: cleanup smc nor flash
[deliverable/linux.git] / arch / blackfin / mach-bf609 / boards / ezkit.c
CommitLineData
22a82628
SZ		 1/*
2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/irq.h>
17#include <linux/i2c.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
54e4ff4d
SZ		 20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/platform_data/pinctrl-adi2.h>
766e3721 23#include <linux/spi/adi_spi3.h>
22a82628
SZ		 24#include <asm/dma.h>
25#include <asm/gpio.h>
26#include <asm/nand.h>
27#include <asm/dpmc.h>
28#include <asm/portmux.h>
29#include <asm/bfin_sdh.h>
30#include <linux/input.h>
31#include <linux/spi/ad7877.h>
32
33/*
34 * Name the Board for the /proc/cpuinfo
35 */
36const char bfin_board_name[] = "ADI BF609-EZKIT";
37
38/*
39 * Driver needs to know address, irq and flag pin.
40 */
41
c4a2c58d 42#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
22a82628
SZ		 43#include <linux/usb/isp1760.h>
44static struct resource bfin_isp1760_resources[] = {
45 [0] = {
46 .start = 0x2C0C0000,
47 .end = 0x2C0C0000 + 0xfffff,
48 .flags = IORESOURCE_MEM,
49 },
50 [1] = {
51 .start = IRQ_PG7,
52 .end = IRQ_PG7,
53 .flags = IORESOURCE_IRQ,
54 },
55};
56
57static struct isp1760_platform_data isp1760_priv = {
58 .is_isp1761 = 0,
59 .bus_width_16 = 1,
60 .port1_otg = 0,
61 .analog_oc = 0,
62 .dack_polarity_high = 0,
63 .dreq_polarity_high = 0,
64};
65
66static struct platform_device bfin_isp1760_device = {
67 .name = "isp1760",
68 .id = 0,
69 .dev = {
70 .platform_data = &isp1760_priv,
71 },
72 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
73 .resource = bfin_isp1760_resources,
74};
75#endif
76
c4a2c58d 77#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
22a82628
SZ		 78#include <asm/bfin_rotary.h>
79
80static struct bfin_rotary_platform_data bfin_rotary_data = {
81 /*.rotary_up_key = KEY_UP,*/
82 /*.rotary_down_key = KEY_DOWN,*/
83 .rotary_rel_code = REL_WHEEL,
84 .rotary_button_key = KEY_ENTER,
85 .debounce = 10, /* 0..17 */
86 .mode = ROT_QUAD_ENC | ROT_DEBE,
87};
88
89static struct resource bfin_rotary_resources[] = {
90 {
91 .start = IRQ_CNT,
92 .end = IRQ_CNT,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device bfin_rotary_device = {
98 .name = "bfin-rotary",
99 .id = -1,
100 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
101 .resource = bfin_rotary_resources,
102 .dev = {
103 .platform_data = &bfin_rotary_data,
104 },
105};
106#endif
107
c4a2c58d 108#if IS_ENABLED(CONFIG_STMMAC_ETH)
22a82628 109#include <linux/stmmac.h>
1d899fd6 110#include <linux/phy.h>
22a82628
SZ		 111
112static struct stmmac_mdio_bus_data phy_private_data = {
22a82628
SZ		 113 .phy_mask = 1,
114};
115
1d899fd6
SZ		 116static struct stmmac_dma_cfg eth_dma_cfg = {
117 .pbl = 2,
118};
119
1f370c57 120int stmmac_ptp_clk_init(struct platform_device *pdev, void *priv)
1d899fd6
SZ		 121{
122 bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0);
123 return 0;
124}
125
22a82628 126static struct plat_stmmacenet_data eth_private_data = {
1d899fd6 127 .has_gmac = 1,
22a82628
SZ		 128 .bus_id = 0,
129 .enh_desc = 1,
130 .phy_addr = 1,
131 .mdio_bus_data = &phy_private_data,
1d899fd6
SZ		 132 .dma_cfg = &eth_dma_cfg,
133 .force_thresh_dma_mode = 1,
134 .interface = PHY_INTERFACE_MODE_RMII,
135 .init = stmmac_ptp_clk_init,
22a82628
SZ		 136};
137
138static struct platform_device bfin_eth_device = {
139 .name = "stmmaceth",
140 .id = 0,
141 .num_resources = 2,
142 .resource = (struct resource[]) {
143 {
144 .start = EMAC0_MACCFG,
145 .end = EMAC0_MACCFG + 0x1274,
146 .flags = IORESOURCE_MEM,
147 },
148 {
149 .name = "macirq",
150 .start = IRQ_EMAC0_STAT,
151 .end = IRQ_EMAC0_STAT,
152 .flags = IORESOURCE_IRQ,
153 },
154 },
155 .dev = {
6e1953e1 156 .power.can_wakeup = 1,
22a82628
SZ		 157 .platform_data = &eth_private_data,
158 }
159};
160#endif
161
c4a2c58d 162#if IS_ENABLED(CONFIG_INPUT_ADXL34X)
22a82628
SZ		 163#include <linux/input/adxl34x.h>
164static const struct adxl34x_platform_data adxl34x_info = {
165 .x_axis_offset = 0,
166 .y_axis_offset = 0,
167 .z_axis_offset = 0,
168 .tap_threshold = 0x31,
169 .tap_duration = 0x10,
170 .tap_latency = 0x60,
171 .tap_window = 0xF0,
172 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
173 .act_axis_control = 0xFF,
174 .activity_threshold = 5,
175 .inactivity_threshold = 3,
176 .inactivity_time = 4,
177 .free_fall_threshold = 0x7,
178 .free_fall_time = 0x20,
179 .data_rate = 0x8,
180 .data_range = ADXL_FULL_RES,
181
182 .ev_type = EV_ABS,
183 .ev_code_x = ABS_X, /* EV_REL */
184 .ev_code_y = ABS_Y, /* EV_REL */
185 .ev_code_z = ABS_Z, /* EV_REL */
186
187 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
188
189/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
190/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
191 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
192 .fifo_mode = ADXL_FIFO_STREAM,
193 .orientation_enable = ADXL_EN_ORIENTATION_3D,
194 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
195 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
196 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
197 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
198};
199#endif
200
c4a2c58d 201#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
22a82628
SZ		 202static struct platform_device rtc_device = {
203 .name = "rtc-bfin",
204 .id = -1,
205};
206#endif
207
c4a2c58d 208#if IS_ENABLED(CONFIG_SERIAL_BFIN)
22a82628
SZ		 209#ifdef CONFIG_SERIAL_BFIN_UART0
210static struct resource bfin_uart0_resources[] = {
211 {
212 .start = UART0_REVID,
213 .end = UART0_RXDIV+4,
214 .flags = IORESOURCE_MEM,
215 },
eb06c064
SZ		 216#ifdef CONFIG_EARLY_PRINTK
217 {
218 .start = PORTD_FER,
219 .end = PORTD_FER+2,
220 .flags = IORESOURCE_REG,
221 },
222 {
223 .start = PORTD_MUX,
224 .end = PORTD_MUX+3,
225 .flags = IORESOURCE_REG,
226 },
227#endif
22a82628
SZ		 228 {
229 .start = IRQ_UART0_TX,
230 .end = IRQ_UART0_TX,
231 .flags = IORESOURCE_IRQ,
232 },
233 {
234 .start = IRQ_UART0_RX,
235 .end = IRQ_UART0_RX,
236 .flags = IORESOURCE_IRQ,
237 },
238 {
239 .start = IRQ_UART0_STAT,
240 .end = IRQ_UART0_STAT,
241 .flags = IORESOURCE_IRQ,
242 },
243 {
244 .start = CH_UART0_TX,
245 .end = CH_UART0_TX,
246 .flags = IORESOURCE_DMA,
247 },
248 {
249 .start = CH_UART0_RX,
250 .end = CH_UART0_RX,
251 .flags = IORESOURCE_DMA,
252 },
253#ifdef CONFIG_BFIN_UART0_CTSRTS
254 { /* CTS pin -- 0 means not supported */
255 .start = GPIO_PD10,
256 .end = GPIO_PD10,
257 .flags = IORESOURCE_IO,
258 },
259 { /* RTS pin -- 0 means not supported */
260 .start = GPIO_PD9,
261 .end = GPIO_PD9,
262 .flags = IORESOURCE_IO,
263 },
264#endif
265};
266
267static unsigned short bfin_uart0_peripherals[] = {
268 P_UART0_TX, P_UART0_RX,
269#ifdef CONFIG_BFIN_UART0_CTSRTS
270 P_UART0_RTS, P_UART0_CTS,
271#endif
272 0
273};
274
275static struct platform_device bfin_uart0_device = {
276 .name = "bfin-uart",
277 .id = 0,
278 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
279 .resource = bfin_uart0_resources,
280 .dev = {
281 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
282 },
283};
284#endif
285#ifdef CONFIG_SERIAL_BFIN_UART1
286static struct resource bfin_uart1_resources[] = {
287 {
288 .start = UART1_REVID,
289 .end = UART1_RXDIV+4,
290 .flags = IORESOURCE_MEM,
291 },
eb06c064
SZ		 292#ifdef CONFIG_EARLY_PRINTK
293 {
294 .start = PORTG_FER_SET,
295 .end = PORTG_FER_SET+2,
296 .flags = IORESOURCE_REG,
297 },
298#endif
22a82628
SZ		 299 {
300 .start = IRQ_UART1_TX,
301 .end = IRQ_UART1_TX,
302 .flags = IORESOURCE_IRQ,
303 },
304 {
305 .start = IRQ_UART1_RX,
306 .end = IRQ_UART1_RX,
307 .flags = IORESOURCE_IRQ,
308 },
309 {
310 .start = IRQ_UART1_STAT,
311 .end = IRQ_UART1_STAT,
312 .flags = IORESOURCE_IRQ,
313 },
314 {
315 .start = CH_UART1_TX,
316 .end = CH_UART1_TX,
317 .flags = IORESOURCE_DMA,
318 },
319 {
320 .start = CH_UART1_RX,
321 .end = CH_UART1_RX,
322 .flags = IORESOURCE_DMA,
323 },
324#ifdef CONFIG_BFIN_UART1_CTSRTS
325 { /* CTS pin -- 0 means not supported */
326 .start = GPIO_PG13,
327 .end = GPIO_PG13,
328 .flags = IORESOURCE_IO,
329 },
330 { /* RTS pin -- 0 means not supported */
331 .start = GPIO_PG10,
332 .end = GPIO_PG10,
333 .flags = IORESOURCE_IO,
334 },
335#endif
336};
337
338static unsigned short bfin_uart1_peripherals[] = {
339 P_UART1_TX, P_UART1_RX,
340#ifdef CONFIG_BFIN_UART1_CTSRTS
341 P_UART1_RTS, P_UART1_CTS,
342#endif
343 0
344};
345
346static struct platform_device bfin_uart1_device = {
347 .name = "bfin-uart",
348 .id = 1,
349 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
350 .resource = bfin_uart1_resources,
351 .dev = {
352 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
353 },
354};
355#endif
356#endif
357
c4a2c58d 358#if IS_ENABLED(CONFIG_BFIN_SIR)
22a82628
SZ		 359#ifdef CONFIG_BFIN_SIR0
360static struct resource bfin_sir0_resources[] = {
361 {
362 .start = 0xFFC00400,
363 .end = 0xFFC004FF,
364 .flags = IORESOURCE_MEM,
365 },
366 {
367 .start = IRQ_UART0_TX,
368 .end = IRQ_UART0_TX+1,
369 .flags = IORESOURCE_IRQ,
370 },
371 {
372 .start = CH_UART0_TX,
373 .end = CH_UART0_TX+1,
374 .flags = IORESOURCE_DMA,
375 },
376};
377static struct platform_device bfin_sir0_device = {
378 .name = "bfin_sir",
379 .id = 0,
380 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
381 .resource = bfin_sir0_resources,
382};
383#endif
384#ifdef CONFIG_BFIN_SIR1
385static struct resource bfin_sir1_resources[] = {
386 {
387 .start = 0xFFC02000,
388 .end = 0xFFC020FF,
389 .flags = IORESOURCE_MEM,
390 },
391 {
392 .start = IRQ_UART1_TX,
393 .end = IRQ_UART1_TX+1,
394 .flags = IORESOURCE_IRQ,
395 },
396 {
397 .start = CH_UART1_TX,
398 .end = CH_UART1_TX+1,
399 .flags = IORESOURCE_DMA,
400 },
401};
402static struct platform_device bfin_sir1_device = {
403 .name = "bfin_sir",
404 .id = 1,
405 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
406 .resource = bfin_sir1_resources,
407};
408#endif
409#endif
410
c4a2c58d 411#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
22a82628
SZ		 412static struct resource musb_resources[] = {
413 [0] = {
414 .start = 0xFFCC1000,
415 .end = 0xFFCC1398,
416 .flags = IORESOURCE_MEM,
417 },
418 [1] = { /* general IRQ */
419 .start = IRQ_USB_STAT,
420 .end = IRQ_USB_STAT,
421 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
422 .name = "mc"
423 },
424 [2] = { /* DMA IRQ */
425 .start = IRQ_USB_DMA,
426 .end = IRQ_USB_DMA,
427 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
428 .name = "dma"
429 },
430};
431
432static struct musb_hdrc_config musb_config = {
433 .multipoint = 1,
434 .dyn_fifo = 0,
435 .dma = 1,
436 .num_eps = 16,
437 .dma_channels = 8,
438 .clkin = 48, /* musb CLKIN in MHZ */
439};
440
441static struct musb_hdrc_platform_data musb_plat = {
442#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
443 .mode = MUSB_OTG,
444#elif defined(CONFIG_USB_MUSB_HDRC)
445 .mode = MUSB_HOST,
446#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
447 .mode = MUSB_PERIPHERAL,
448#endif
449 .config = &musb_config,
450};
451
452static u64 musb_dmamask = ~(u32)0;
453
454static struct platform_device musb_device = {
455 .name = "musb-blackfin",
456 .id = 0,
457 .dev = {
458 .dma_mask = &musb_dmamask,
459 .coherent_dma_mask = 0xffffffff,
460 .platform_data = &musb_plat,
461 },
462 .num_resources = ARRAY_SIZE(musb_resources),
463 .resource = musb_resources,
464};
465#endif
466
c4a2c58d 467#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
22a82628
SZ		 468#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
469static struct resource bfin_sport0_uart_resources[] = {
470 {
471 .start = SPORT0_TCR1,
472 .end = SPORT0_MRCS3+4,
473 .flags = IORESOURCE_MEM,
474 },
475 {
476 .start = IRQ_SPORT0_RX,
477 .end = IRQ_SPORT0_RX+1,
478 .flags = IORESOURCE_IRQ,
479 },
480 {
481 .start = IRQ_SPORT0_ERROR,
482 .end = IRQ_SPORT0_ERROR,
483 .flags = IORESOURCE_IRQ,
484 },
485};
486
487static unsigned short bfin_sport0_peripherals[] = {
488 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
489 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
490};
491
492static struct platform_device bfin_sport0_uart_device = {
493 .name = "bfin-sport-uart",
494 .id = 0,
495 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
496 .resource = bfin_sport0_uart_resources,
497 .dev = {
498 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
499 },
500};
501#endif
502#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
503static struct resource bfin_sport1_uart_resources[] = {
504 {
505 .start = SPORT1_TCR1,
506 .end = SPORT1_MRCS3+4,
507 .flags = IORESOURCE_MEM,
508 },
509 {
510 .start = IRQ_SPORT1_RX,
511 .end = IRQ_SPORT1_RX+1,
512 .flags = IORESOURCE_IRQ,
513 },
514 {
515 .start = IRQ_SPORT1_ERROR,
516 .end = IRQ_SPORT1_ERROR,
517 .flags = IORESOURCE_IRQ,
518 },
519};
520
521static unsigned short bfin_sport1_peripherals[] = {
522 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
523 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
524};
525
526static struct platform_device bfin_sport1_uart_device = {
527 .name = "bfin-sport-uart",
528 .id = 1,
529 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
530 .resource = bfin_sport1_uart_resources,
531 .dev = {
532 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
533 },
534};
535#endif
536#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
537static struct resource bfin_sport2_uart_resources[] = {
538 {
539 .start = SPORT2_TCR1,
540 .end = SPORT2_MRCS3+4,
541 .flags = IORESOURCE_MEM,
542 },
543 {
544 .start = IRQ_SPORT2_RX,
545 .end = IRQ_SPORT2_RX+1,
546 .flags = IORESOURCE_IRQ,
547 },
548 {
549 .start = IRQ_SPORT2_ERROR,
550 .end = IRQ_SPORT2_ERROR,
551 .flags = IORESOURCE_IRQ,
552 },
553};
554
555static unsigned short bfin_sport2_peripherals[] = {
556 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
557 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
558};
559
560static struct platform_device bfin_sport2_uart_device = {
561 .name = "bfin-sport-uart",
562 .id = 2,
563 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
564 .resource = bfin_sport2_uart_resources,
565 .dev = {
566 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
567 },
568};
569#endif
570#endif
571
c4a2c58d 572#if IS_ENABLED(CONFIG_CAN_BFIN)
22a82628
SZ		 573
574static unsigned short bfin_can0_peripherals[] = {
575 P_CAN0_RX, P_CAN0_TX, 0
576};
577
578static struct resource bfin_can0_resources[] = {
579 {
580 .start = 0xFFC00A00,
581 .end = 0xFFC00FFF,
582 .flags = IORESOURCE_MEM,
583 },
584 {
585 .start = IRQ_CAN0_RX,
586 .end = IRQ_CAN0_RX,
587 .flags = IORESOURCE_IRQ,
588 },
589 {
590 .start = IRQ_CAN0_TX,
591 .end = IRQ_CAN0_TX,
592 .flags = IORESOURCE_IRQ,
593 },
594 {
595 .start = IRQ_CAN0_STAT,
596 .end = IRQ_CAN0_STAT,
597 .flags = IORESOURCE_IRQ,
598 },
599};
600
601static struct platform_device bfin_can0_device = {
602 .name = "bfin_can",
603 .id = 0,
604 .num_resources = ARRAY_SIZE(bfin_can0_resources),
605 .resource = bfin_can0_resources,
606 .dev = {
607 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
608 },
609};
610
611#endif
612
c4a2c58d 613#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
22a82628
SZ		 614static struct mtd_partition partition_info[] = {
615 {
616 .name = "bootloader(nand)",
617 .offset = 0,
618 .size = 0x80000,
619 }, {
620 .name = "linux kernel(nand)",
621 .offset = MTDPART_OFS_APPEND,
622 .size = 4 * 1024 * 1024,
623 },
624 {
625 .name = "file system(nand)",
626 .offset = MTDPART_OFS_APPEND,
627 .size = MTDPART_SIZ_FULL,
628 },
629};
630
631static struct bf5xx_nand_platform bfin_nand_platform = {
632 .data_width = NFC_NWIDTH_8,
633 .partitions = partition_info,
634 .nr_partitions = ARRAY_SIZE(partition_info),
635 .rd_dly = 3,
636 .wr_dly = 3,
637};
638
639static struct resource bfin_nand_resources[] = {
640 {
641 .start = 0xFFC03B00,
642 .end = 0xFFC03B4F,
643 .flags = IORESOURCE_MEM,
644 },
645 {
646 .start = CH_NFC,
647 .end = CH_NFC,
648 .flags = IORESOURCE_IRQ,
649 },
650};
651
652static struct platform_device bfin_nand_device = {
653 .name = "bfin-nand",
654 .id = 0,
655 .num_resources = ARRAY_SIZE(bfin_nand_resources),
656 .resource = bfin_nand_resources,
657 .dev = {
658 .platform_data = &bfin_nand_platform,
659 },
660};
661#endif
662
c4a2c58d 663#if IS_ENABLED(CONFIG_SDH_BFIN)
22a82628
SZ		 664
665static struct bfin_sd_host bfin_sdh_data = {
666 .dma_chan = CH_RSI,
667 .irq_int0 = IRQ_RSI_INT0,
668 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
669};
670
671static struct platform_device bfin_sdh_device = {
672 .name = "bfin-sdh",
673 .id = 0,
674 .dev = {
675 .platform_data = &bfin_sdh_data,
676 },
677};
678#endif
679
c4a2c58d 680#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
22a82628
SZ		 681static struct mtd_partition ezkit_partitions[] = {
682 {
683 .name = "bootloader(nor)",
684 .size = 0x80000,
685 .offset = 0,
686 }, {
687 .name = "linux kernel(nor)",
688 .size = 0x400000,
689 .offset = MTDPART_OFS_APPEND,
690 }, {
691 .name = "file system(nor)",
692 .size = 0x1000000 - 0x80000 - 0x400000,
693 .offset = MTDPART_OFS_APPEND,
694 },
695};
696
54e4ff4d 697int bf609_nor_flash_init(struct platform_device *pdev)
22a82628
SZ		 698{
699#define CONFIG_SMC_GCTL_VAL 0x00000010
22a82628
SZ		 700
701 bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
1c400939 702 bfin_write32(SMC_B0CTL, 0x01002011);
22a82628
SZ		 703 bfin_write32(SMC_B0TIM, 0x08170977);
704 bfin_write32(SMC_B0ETIM, 0x00092231);
705 return 0;
706}
707
37035d62 708void bf609_nor_flash_exit(struct platform_device *pdev)
0220874a 709{
0220874a 710 bfin_write32(SMC_GCTL, 0);
0220874a
SM		 711}
712
22a82628
SZ		 713static struct physmap_flash_data ezkit_flash_data = {
714 .width = 2,
715 .parts = ezkit_partitions,
0220874a
SM		 716 .init = bf609_nor_flash_init,
717 .exit = bf609_nor_flash_exit,
22a82628 718 .nr_parts = ARRAY_SIZE(ezkit_partitions),
3fa8c4b0
BL		 719#ifdef CONFIG_ROMKERNEL
720 .probe_type = "map_rom",
721#endif
22a82628
SZ		 722};
723
724static struct resource ezkit_flash_resource = {
725 .start = 0xb0000000,
726 .end = 0xb0ffffff,
727 .flags = IORESOURCE_MEM,
728};
729
730static struct platform_device ezkit_flash_device = {
1c400939 731 .name = "physmap-flash",
22a82628
SZ		 732 .id = 0,
733 .dev = {
734 .platform_data = &ezkit_flash_data,
735 },
736 .num_resources = 1,
737 .resource = &ezkit_flash_resource,
738};
739#endif
740
c4a2c58d 741#if IS_ENABLED(CONFIG_MTD_M25P80)
22a82628
SZ		 742/* SPI flash chip (w25q32) */
743static struct mtd_partition bfin_spi_flash_partitions[] = {
744 {
745 .name = "bootloader(spi)",
746 .size = 0x00080000,
747 .offset = 0,
748 .mask_flags = MTD_CAP_ROM
749 }, {
750 .name = "linux kernel(spi)",
751 .size = 0x00180000,
752 .offset = MTDPART_OFS_APPEND,
753 }, {
754 .name = "file system(spi)",
755 .size = MTDPART_SIZ_FULL,
756 .offset = MTDPART_OFS_APPEND,
757 }
758};
759
760static struct flash_platform_data bfin_spi_flash_data = {
761 .name = "m25p80",
762 .parts = bfin_spi_flash_partitions,
763 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
764 .type = "w25q32",
765};
766
766e3721 767static struct adi_spi3_chip spi_flash_chip_info = {
22a82628
SZ		 768 .enable_dma = true, /* use dma transfer with this chip*/
769};
770#endif
771
c4a2c58d 772#if IS_ENABLED(CONFIG_SPI_SPIDEV)
766e3721 773static struct adi_spi3_chip spidev_chip_info = {
22a82628
SZ		 774 .enable_dma = true,
775};
776#endif
777
c4a2c58d 778#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
22a82628
SZ		 779static struct platform_device bfin_i2s_pcm = {
780 .name = "bfin-i2s-pcm-audio",
781 .id = -1,
782};
783#endif
784
c4a2c58d 785#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
22a82628
SZ		 786#include <asm/bfin_sport3.h>
787static struct resource bfin_snd_resources[] = {
788 {
789 .start = SPORT0_CTL_A,
790 .end = SPORT0_CTL_A,
791 .flags = IORESOURCE_MEM,
792 },
793 {
794 .start = SPORT0_CTL_B,
795 .end = SPORT0_CTL_B,
796 .flags = IORESOURCE_MEM,
797 },
798 {
799 .start = CH_SPORT0_TX,
800 .end = CH_SPORT0_TX,
801 .flags = IORESOURCE_DMA,
802 },
803 {
804 .start = CH_SPORT0_RX,
805 .end = CH_SPORT0_RX,
806 .flags = IORESOURCE_DMA,
807 },
808 {
809 .start = IRQ_SPORT0_TX_STAT,
810 .end = IRQ_SPORT0_TX_STAT,
811 .flags = IORESOURCE_IRQ,
812 },
813 {
814 .start = IRQ_SPORT0_RX_STAT,
815 .end = IRQ_SPORT0_RX_STAT,
816 .flags = IORESOURCE_IRQ,
817 },
818};
819
820static const unsigned short bfin_snd_pin[] = {
821 P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
822 P_SPORT0_BFS, P_SPORT0_BD0, 0,
823};
824
825static struct bfin_snd_platform_data bfin_snd_data = {
826 .pin_req = bfin_snd_pin,
827};
828
829static struct platform_device bfin_i2s = {
830 .name = "bfin-i2s",
831 .num_resources = ARRAY_SIZE(bfin_snd_resources),
832 .resource = bfin_snd_resources,
833 .dev = {
834 .platform_data = &bfin_snd_data,
835 },
836};
837#endif
838
c4a2c58d 839#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
63f49dce 840static const char * const ad1836_link[] = {
34f40955 841 "bfin-i2s.0",
63f49dce
SJ		 842 "spi0.76",
843};
844static struct platform_device bfin_ad1836_machine = {
845 .name = "bfin-snd-ad1836",
846 .id = -1,
847 .dev = {
848 .platform_data = (void *)ad1836_link,
849 },
850};
851#endif
852
c4a2c58d 853#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
22a82628
SZ		 854static struct platform_device adau1761_device = {
855 .name = "bfin-eval-adau1x61",
856};
857#endif
858
c4a2c58d 859#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
22a82628
SZ		 860#include <sound/adau17x1.h>
861static struct adau1761_platform_data adau1761_info = {
862 .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
863 .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
864};
865#endif
866
c4a2c58d 867#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
22a82628
SZ		 868#include <linux/videodev2.h>
869#include <media/blackfin/bfin_capture.h>
870#include <media/blackfin/ppi.h>
871
872static const unsigned short ppi_req[] = {
873 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
874 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
338881a5
SJ		 875 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
876 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
c4a2c58d 877#if !IS_ENABLED(CONFIG_VIDEO_VS6624)
338881a5
SJ		 878 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
879 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
00afdbbf 880#endif
22a82628
SZ		 881 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
882 0,
883};
884
885static const struct ppi_info ppi_info = {
886 .type = PPI_TYPE_EPPI3,
887 .dma_ch = CH_EPPI0_CH0,
888 .irq_err = IRQ_EPPI0_STAT,
889 .base = (void __iomem *)EPPI0_STAT,
890 .pin_req = ppi_req,
891};
892
c4a2c58d 893#if IS_ENABLED(CONFIG_VIDEO_VS6624)
22a82628
SZ		 894static struct v4l2_input vs6624_inputs[] = {
895 {
896 .index = 0,
897 .name = "Camera",
898 .type = V4L2_INPUT_TYPE_CAMERA,
899 .std = V4L2_STD_UNKNOWN,
900 },
901};
902
903static struct bcap_route vs6624_routes[] = {
904 {
905 .input = 0,
906 .output = 0,
907 },
908};
909
00afdbbf 910static const unsigned vs6624_ce_pin = GPIO_PE4;
22a82628
SZ		 911
912static struct bfin_capture_config bfin_capture_data = {
913 .card_name = "BF609",
914 .inputs = vs6624_inputs,
915 .num_inputs = ARRAY_SIZE(vs6624_inputs),
916 .routes = vs6624_routes,
917 .i2c_adapter_id = 0,
918 .board_info = {
919 .type = "vs6624",
920 .addr = 0x10,
921 .platform_data = (void *)&vs6624_ce_pin,
922 },
923 .ppi_info = &ppi_info,
924 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
925 | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
ac5bb893 926 .blank_pixels = 4,
22a82628
SZ		 927};
928#endif
929
c4a2c58d 930#if IS_ENABLED(CONFIG_VIDEO_ADV7842)
338881a5
SJ		 931#include <media/adv7842.h>
932
933static struct v4l2_input adv7842_inputs[] = {
934 {
935 .index = 0,
936 .name = "Composite",
937 .type = V4L2_INPUT_TYPE_CAMERA,
938 .std = V4L2_STD_ALL,
688da5e8 939 .capabilities = V4L2_IN_CAP_STD,
338881a5
SJ		 940 },
941 {
942 .index = 1,
943 .name = "S-Video",
944 .type = V4L2_INPUT_TYPE_CAMERA,
945 .std = V4L2_STD_ALL,
688da5e8 946 .capabilities = V4L2_IN_CAP_STD,
338881a5
SJ		 947 },
948 {
949 .index = 2,
950 .name = "Component",
951 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 952 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
338881a5
SJ		 953 },
954 {
955 .index = 3,
956 .name = "VGA",
957 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 958 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
338881a5
SJ		 959 },
960 {
961 .index = 4,
962 .name = "HDMI",
963 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 964 .capabilities = V4L2_IN_CAP_DV_TIMINGS,
338881a5
SJ		 965 },
966};
967
968static struct bcap_route adv7842_routes[] = {
969 {
970 .input = 3,
b5c00ae7 971 .output = 0,
688da5e8
SJ		 972 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
973 | EPPI_CTL_ACTIVE656),
338881a5
SJ		 974 },
975 {
976 .input = 4,
b5c00ae7 977 .output = 0,
338881a5
SJ		 978 },
979 {
980 .input = 2,
b5c00ae7 981 .output = 0,
338881a5
SJ		 982 },
983 {
984 .input = 1,
b5c00ae7 985 .output = 0,
338881a5
SJ		 986 },
987 {
988 .input = 0,
688da5e8
SJ		 989 .output = 1,
990 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
991 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
992 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
b5c00ae7
SJ		 993 },
994};
995
996static struct adv7842_output_format adv7842_opf[] = {
997 {
998 .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
999 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
1000 .op_656_range = 1,
1001 .blank_data = 1,
1002 .insert_av_codes = 1,
338881a5 1003 },
688da5e8
SJ		 1004 {
1005 .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
1006 .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
1007 .op_656_range = 1,
1008 .blank_data = 1,
1009 },
338881a5
SJ		 1010};
1011
1012static struct adv7842_platform_data adv7842_data = {
b5c00ae7
SJ		 1013 .opf = adv7842_opf,
1014 .num_opf = ARRAY_SIZE(adv7842_opf),
338881a5 1015 .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
338881a5
SJ		 1016 .prim_mode = ADV7842_PRIM_MODE_SDP,
1017 .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
f0ec1742
MB		 1018 .hdmi_free_run_enable = 1,
1019 .sdp_free_run_auto = 1,
fe808f3c 1020 .llc_dll_phase = 0x10,
e942d619
SJ		 1021 .i2c_sdp_io = 0x40,
1022 .i2c_sdp = 0x41,
1023 .i2c_cp = 0x42,
1024 .i2c_vdp = 0x43,
1025 .i2c_afe = 0x44,
1026 .i2c_hdmi = 0x45,
1027 .i2c_repeater = 0x46,
1028 .i2c_edid = 0x47,
1029 .i2c_infoframe = 0x48,
1030 .i2c_cec = 0x49,
1031 .i2c_avlink = 0x4a,
b5c00ae7 1032 .i2c_ex = 0x26,
338881a5
SJ		 1033};
1034
1035static struct bfin_capture_config bfin_capture_data = {
1036 .card_name = "BF609",
1037 .inputs = adv7842_inputs,
1038 .num_inputs = ARRAY_SIZE(adv7842_inputs),
1039 .routes = adv7842_routes,
1040 .i2c_adapter_id = 0,
1041 .board_info = {
1042 .type = "adv7842",
1043 .addr = 0x20,
1044 .platform_data = (void *)&adv7842_data,
1045 },
1046 .ppi_info = &ppi_info,
1047 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
1048 | EPPI_CTL_ACTIVE656),
1049};
1050#endif
1051
22a82628
SZ		 1052static struct platform_device bfin_capture_device = {
1053 .name = "bfin_capture",
1054 .dev = {
1055 .platform_data = &bfin_capture_data,
1056 },
1057};
1058#endif
1059
c4a2c58d 1060#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
e942d619
SJ		 1061#include <linux/videodev2.h>
1062#include <media/blackfin/bfin_display.h>
1063#include <media/blackfin/ppi.h>
1064
1065static const unsigned short ppi_req_disp[] = {
1066 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
1067 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
1068 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
1069 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
1070 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
1071 0,
1072};
1073
1074static const struct ppi_info ppi_info = {
1075 .type = PPI_TYPE_EPPI3,
1076 .dma_ch = CH_EPPI0_CH0,
1077 .irq_err = IRQ_EPPI0_STAT,
1078 .base = (void __iomem *)EPPI0_STAT,
1079 .pin_req = ppi_req_disp,
1080};
1081
c4a2c58d 1082#if IS_ENABLED(CONFIG_VIDEO_ADV7511)
e942d619
SJ		 1083#include <media/adv7511.h>
1084
1085static struct v4l2_output adv7511_outputs[] = {
1086 {
1087 .index = 0,
1088 .name = "HDMI",
1089 .type = V4L2_INPUT_TYPE_CAMERA,
a8451ed2 1090 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
e942d619
SJ		 1091 },
1092};
1093
1094static struct disp_route adv7511_routes[] = {
1095 {
1096 .output = 0,
1097 },
1098};
1099
1100static struct adv7511_platform_data adv7511_data = {
1101 .edid_addr = 0x7e,
1102 .i2c_ex = 0x25,
1103};
1104
1105static struct bfin_display_config bfin_display_data = {
1106 .card_name = "BF609",
1107 .outputs = adv7511_outputs,
1108 .num_outputs = ARRAY_SIZE(adv7511_outputs),
1109 .routes = adv7511_routes,
1110 .i2c_adapter_id = 0,
1111 .board_info = {
1112 .type = "adv7511",
1113 .addr = 0x39,
1114 .platform_data = (void *)&adv7511_data,
1115 },
1116 .ppi_info = &ppi_info,
1117 .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
1118 | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
1119 | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
1120 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1121};
1122#endif
1123
4940c53d
SJ		 1124#if IS_ENABLED(CONFIG_VIDEO_ADV7343)
1125#include <media/adv7343.h>
1126
1127static struct v4l2_output adv7343_outputs[] = {
1128 {
1129 .index = 0,
1130 .name = "Composite",
1131 .type = V4L2_OUTPUT_TYPE_ANALOG,
1132 .std = V4L2_STD_ALL,
1133 .capabilities = V4L2_OUT_CAP_STD,
1134 },
e5786092
SJ		 1135 {
1136 .index = 1,
1137 .name = "S-Video",
1138 .type = V4L2_OUTPUT_TYPE_ANALOG,
1139 .std = V4L2_STD_ALL,
1140 .capabilities = V4L2_OUT_CAP_STD,
1141 },
1142 {
1143 .index = 2,
1144 .name = "Component",
1145 .type = V4L2_OUTPUT_TYPE_ANALOG,
1146 .std = V4L2_STD_ALL,
1147 .capabilities = V4L2_OUT_CAP_STD,
1148 },
1149
4940c53d
SJ		 1150};
1151
1152static struct disp_route adv7343_routes[] = {
1153 {
e5786092
SJ		 1154 .output = ADV7343_COMPOSITE_ID,
1155 },
1156 {
1157 .output = ADV7343_SVIDEO_ID,
1158 },
1159 {
1160 .output = ADV7343_COMPONENT_ID,
4940c53d
SJ		 1161 },
1162};
1163
1164static struct adv7343_platform_data adv7343_data = {
1165 .mode_config = {
1166 .sleep_mode = false,
1167 .pll_control = false,
1168 .dac_1 = true,
1169 .dac_2 = true,
1170 .dac_3 = true,
1171 .dac_4 = true,
1172 .dac_5 = true,
1173 .dac_6 = true,
1174 },
1175 .sd_config = {
1176 .sd_dac_out1 = false,
1177 .sd_dac_out2 = false,
1178 },
1179};
1180
1181static struct bfin_display_config bfin_display_data = {
1182 .card_name = "BF609",
1183 .outputs = adv7343_outputs,
1184 .num_outputs = ARRAY_SIZE(adv7343_outputs),
1185 .routes = adv7343_routes,
1186 .i2c_adapter_id = 0,
1187 .board_info = {
1188 .type = "adv7343",
1189 .addr = 0x2b,
1190 .platform_data = (void *)&adv7343_data,
1191 },
1192 .ppi_info = &ppi_info_disp,
1193 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1LO_FS2LO
1194 | EPPI_CTL_POLC3 | EPPI_CTL_BLANKGEN | EPPI_CTL_SYNC2
1195 | EPPI_CTL_NON656 | EPPI_CTL_DIR),
1196};
1197#endif
1198
e942d619
SJ		 1199static struct platform_device bfin_display_device = {
1200 .name = "bfin_display",
1201 .dev = {
1202 .platform_data = &bfin_display_data,
1203 },
1204};
1205#endif
1206
22a82628
SZ		 1207#if defined(CONFIG_BFIN_CRC)
1208#define BFIN_CRC_NAME "bfin-crc"
1209
1210static struct resource bfin_crc0_resources[] = {
1211 {
1212 .start = REG_CRC0_CTL,
1213 .end = REG_CRC0_REVID+4,
1214 .flags = IORESOURCE_MEM,
1215 },
1216 {
1217 .start = IRQ_CRC0_DCNTEXP,
1218 .end = IRQ_CRC0_DCNTEXP,
1219 .flags = IORESOURCE_IRQ,
1220 },
1221 {
1222 .start = CH_MEM_STREAM0_SRC_CRC0,
1223 .end = CH_MEM_STREAM0_SRC_CRC0,
1224 .flags = IORESOURCE_DMA,
1225 },
1226 {
1227 .start = CH_MEM_STREAM0_DEST_CRC0,
1228 .end = CH_MEM_STREAM0_DEST_CRC0,
1229 .flags = IORESOURCE_DMA,
1230 },
1231};
1232
1233static struct platform_device bfin_crc0_device = {
1234 .name = BFIN_CRC_NAME,
1235 .id = 0,
1236 .num_resources = ARRAY_SIZE(bfin_crc0_resources),
1237 .resource = bfin_crc0_resources,
1238};
1239
1240static struct resource bfin_crc1_resources[] = {
1241 {
1242 .start = REG_CRC1_CTL,
1243 .end = REG_CRC1_REVID+4,
1244 .flags = IORESOURCE_MEM,
1245 },
1246 {
1247 .start = IRQ_CRC1_DCNTEXP,
1248 .end = IRQ_CRC1_DCNTEXP,
1249 .flags = IORESOURCE_IRQ,
1250 },
1251 {
1252 .start = CH_MEM_STREAM1_SRC_CRC1,
1253 .end = CH_MEM_STREAM1_SRC_CRC1,
1254 .flags = IORESOURCE_DMA,
1255 },
1256 {
1257 .start = CH_MEM_STREAM1_DEST_CRC1,
1258 .end = CH_MEM_STREAM1_DEST_CRC1,
1259 .flags = IORESOURCE_DMA,
1260 },
1261};
1262
1263static struct platform_device bfin_crc1_device = {
1264 .name = BFIN_CRC_NAME,
1265 .id = 1,
1266 .num_resources = ARRAY_SIZE(bfin_crc1_resources),
1267 .resource = bfin_crc1_resources,
1268};
1269#endif
1270
c21e783b
SZ		 1271#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
1272#define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
1273#define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
1274
1275static struct resource bfin_crypto_crc_resources[] = {
1276 {
1277 .start = REG_CRC0_CTL,
1278 .end = REG_CRC0_REVID+4,
1279 .flags = IORESOURCE_MEM,
1280 },
1281 {
1282 .start = IRQ_CRC0_DCNTEXP,
1283 .end = IRQ_CRC0_DCNTEXP,
1284 .flags = IORESOURCE_IRQ,
1285 },
1286 {
1287 .start = CH_MEM_STREAM0_SRC_CRC0,
1288 .end = CH_MEM_STREAM0_SRC_CRC0,
1289 .flags = IORESOURCE_DMA,
1290 },
c21e783b
SZ		 1291};
1292
1293static struct platform_device bfin_crypto_crc_device = {
1294 .name = BFIN_CRYPTO_CRC_NAME,
1295 .id = 0,
1296 .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
1297 .resource = bfin_crypto_crc_resources,
1298 .dev = {
1299 .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
1300 },
1301};
1302#endif
1303
c4a2c58d 1304#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
22a82628
SZ		 1305static const struct ad7877_platform_data bfin_ad7877_ts_info = {
1306 .model = 7877,
1307 .vref_delay_usecs = 50, /* internal, no capacitor */
1308 .x_plate_ohms = 419,
1309 .y_plate_ohms = 486,
1310 .pressure_max = 1000,
1311 .pressure_min = 0,
1312 .stopacq_polarity = 1,
1313 .first_conversion_delay = 3,
1314 .acquisition_time = 1,
1315 .averaging = 1,
1316 .pen_down_acc_interval = 1,
1317};
1318#endif
1319
54e4ff4d
SZ		 1320#ifdef CONFIG_PINCTRL_ADI2
1321
1322# define ADI_PINT_DEVNAME "adi-gpio-pint"
1323# define ADI_GPIO_DEVNAME "adi-gpio"
1324# define ADI_PINCTRL_DEVNAME "pinctrl-adi2"
1325
1326static struct platform_device bfin_pinctrl_device = {
1327 .name = ADI_PINCTRL_DEVNAME,
1328 .id = 0,
1329};
1330
54e4ff4d
SZ		 1331static struct resource bfin_pint0_resources[] = {
1332 {
1333 .start = PINT0_MASK_SET,
1334 .end = PINT0_LATCH + 3,
1335 .flags = IORESOURCE_MEM,
1336 },
1337 {
1338 .start = IRQ_PINT0,
1339 .end = IRQ_PINT0,
1340 .flags = IORESOURCE_IRQ,
1341 },
1342};
1343
1344static struct platform_device bfin_pint0_device = {
1345 .name = ADI_PINT_DEVNAME,
1346 .id = 0,
1347 .num_resources = ARRAY_SIZE(bfin_pint0_resources),
1348 .resource = bfin_pint0_resources,
1349};
1350
1351static struct resource bfin_pint1_resources[] = {
1352 {
1353 .start = PINT1_MASK_SET,
1354 .end = PINT1_LATCH + 3,
1355 .flags = IORESOURCE_MEM,
1356 },
1357 {
1358 .start = IRQ_PINT1,
1359 .end = IRQ_PINT1,
1360 .flags = IORESOURCE_IRQ,
1361 },
1362};
1363
1364static struct platform_device bfin_pint1_device = {
1365 .name = ADI_PINT_DEVNAME,
1366 .id = 1,
1367 .num_resources = ARRAY_SIZE(bfin_pint1_resources),
1368 .resource = bfin_pint1_resources,
1369};
1370
1371static struct resource bfin_pint2_resources[] = {
1372 {
1373 .start = PINT2_MASK_SET,
1374 .end = PINT2_LATCH + 3,
1375 .flags = IORESOURCE_MEM,
1376 },
1377 {
1378 .start = IRQ_PINT2,
1379 .end = IRQ_PINT2,
1380 .flags = IORESOURCE_IRQ,
1381 },
1382};
1383
1384static struct platform_device bfin_pint2_device = {
1385 .name = ADI_PINT_DEVNAME,
1386 .id = 2,
1387 .num_resources = ARRAY_SIZE(bfin_pint2_resources),
1388 .resource = bfin_pint2_resources,
1389};
1390
1391static struct resource bfin_pint3_resources[] = {
1392 {
1393 .start = PINT3_MASK_SET,
1394 .end = PINT3_LATCH + 3,
1395 .flags = IORESOURCE_MEM,
1396 },
1397 {
1398 .start = IRQ_PINT3,
1399 .end = IRQ_PINT3,
1400 .flags = IORESOURCE_IRQ,
1401 },
1402};
1403
1404static struct platform_device bfin_pint3_device = {
1405 .name = ADI_PINT_DEVNAME,
1406 .id = 3,
1407 .num_resources = ARRAY_SIZE(bfin_pint3_resources),
1408 .resource = bfin_pint3_resources,
1409};
1410
1411static struct resource bfin_pint4_resources[] = {
1412 {
1413 .start = PINT4_MASK_SET,
1414 .end = PINT4_LATCH + 3,
1415 .flags = IORESOURCE_MEM,
1416 },
1417 {
1418 .start = IRQ_PINT4,
1419 .end = IRQ_PINT4,
1420 .flags = IORESOURCE_IRQ,
1421 },
1422};
1423
1424static struct platform_device bfin_pint4_device = {
1425 .name = ADI_PINT_DEVNAME,
1426 .id = 4,
1427 .num_resources = ARRAY_SIZE(bfin_pint4_resources),
1428 .resource = bfin_pint4_resources,
1429};
1430
1431static struct resource bfin_pint5_resources[] = {
1432 {
1433 .start = PINT5_MASK_SET,
1434 .end = PINT5_LATCH + 3,
1435 .flags = IORESOURCE_MEM,
1436 },
1437 {
1438 .start = IRQ_PINT5,
1439 .end = IRQ_PINT5,
1440 .flags = IORESOURCE_IRQ,
1441 },
1442};
1443
1444static struct platform_device bfin_pint5_device = {
1445 .name = ADI_PINT_DEVNAME,
1446 .id = 5,
1447 .num_resources = ARRAY_SIZE(bfin_pint5_resources),
1448 .resource = bfin_pint5_resources,
1449};
1450
1451static struct resource bfin_gpa_resources[] = {
1452 {
1453 .start = PORTA_FER,
1454 .end = PORTA_MUX + 3,
1455 .flags = IORESOURCE_MEM,
1456 },
1457 { /* optional */
1458 .start = IRQ_PA0,
1459 .end = IRQ_PA0,
1460 .flags = IORESOURCE_IRQ,
1461 },
1462};
1463
1464static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = {
1465 .port_pin_base = GPIO_PA0,
1466 .port_width = GPIO_BANKSIZE,
1467 .pint_id = 0, /* PINT0 */
1468 .pint_assign = true, /* PINT upper 16 bit */
1469 .pint_map = 0, /* mapping mask in PINT */
1470};
1471
1472static struct platform_device bfin_gpa_device = {
1473 .name = ADI_GPIO_DEVNAME,
1474 .id = 0,
1475 .num_resources = ARRAY_SIZE(bfin_gpa_resources),
1476 .resource = bfin_gpa_resources,
1477 .dev = {
1478 .platform_data = &bfin_gpa_pdata, /* Passed to driver */
1479 },
1480};
1481
1482static struct resource bfin_gpb_resources[] = {
1483 {
1484 .start = PORTB_FER,
1485 .end = PORTB_MUX + 3,
1486 .flags = IORESOURCE_MEM,
1487 },
1488 {
1489 .start = IRQ_PB0,
1490 .end = IRQ_PB0,
1491 .flags = IORESOURCE_IRQ,
1492 },
1493};
1494
1495static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = {
1496 .port_pin_base = GPIO_PB0,
1497 .port_width = GPIO_BANKSIZE,
1498 .pint_id = 0,
1499 .pint_assign = false,
1500 .pint_map = 1,
1501};
1502
1503static struct platform_device bfin_gpb_device = {
1504 .name = ADI_GPIO_DEVNAME,
1505 .id = 1,
1506 .num_resources = ARRAY_SIZE(bfin_gpb_resources),
1507 .resource = bfin_gpb_resources,
1508 .dev = {
1509 .platform_data = &bfin_gpb_pdata, /* Passed to driver */
1510 },
1511};
1512
1513static struct resource bfin_gpc_resources[] = {
1514 {
1515 .start = PORTC_FER,
1516 .end = PORTC_MUX + 3,
1517 .flags = IORESOURCE_MEM,
1518 },
1519 {
1520 .start = IRQ_PC0,
1521 .end = IRQ_PC0,
1522 .flags = IORESOURCE_IRQ,
1523 },
1524};
1525
1526static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = {
1527 .port_pin_base = GPIO_PC0,
1528 .port_width = GPIO_BANKSIZE,
1529 .pint_id = 1,
1530 .pint_assign = false,
1531 .pint_map = 1,
1532};
1533
1534static struct platform_device bfin_gpc_device = {
1535 .name = ADI_GPIO_DEVNAME,
1536 .id = 2,
1537 .num_resources = ARRAY_SIZE(bfin_gpc_resources),
1538 .resource = bfin_gpc_resources,
1539 .dev = {
1540 .platform_data = &bfin_gpc_pdata, /* Passed to driver */
1541 },
1542};
1543
1544static struct resource bfin_gpd_resources[] = {
1545 {
1546 .start = PORTD_FER,
1547 .end = PORTD_MUX + 3,
1548 .flags = IORESOURCE_MEM,
1549 },
1550 {
1551 .start = IRQ_PD0,
1552 .end = IRQ_PD0,
1553 .flags = IORESOURCE_IRQ,
1554 },
1555};
1556
1557static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = {
1558 .port_pin_base = GPIO_PD0,
1559 .port_width = GPIO_BANKSIZE,
1560 .pint_id = 2,
1561 .pint_assign = false,
1562 .pint_map = 1,
1563};
1564
1565static struct platform_device bfin_gpd_device = {
1566 .name = ADI_GPIO_DEVNAME,
1567 .id = 3,
1568 .num_resources = ARRAY_SIZE(bfin_gpd_resources),
1569 .resource = bfin_gpd_resources,
1570 .dev = {
1571 .platform_data = &bfin_gpd_pdata, /* Passed to driver */
1572 },
1573};
1574
1575static struct resource bfin_gpe_resources[] = {
1576 {
1577 .start = PORTE_FER,
1578 .end = PORTE_MUX + 3,
1579 .flags = IORESOURCE_MEM,
1580 },
1581 {
1582 .start = IRQ_PE0,
1583 .end = IRQ_PE0,
1584 .flags = IORESOURCE_IRQ,
1585 },
1586};
1587
1588static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = {
1589 .port_pin_base = GPIO_PE0,
1590 .port_width = GPIO_BANKSIZE,
1591 .pint_id = 3,
1592 .pint_assign = false,
1593 .pint_map = 1,
1594};
1595
1596static struct platform_device bfin_gpe_device = {
1597 .name = ADI_GPIO_DEVNAME,
1598 .id = 4,
1599 .num_resources = ARRAY_SIZE(bfin_gpe_resources),
1600 .resource = bfin_gpe_resources,
1601 .dev = {
1602 .platform_data = &bfin_gpe_pdata, /* Passed to driver */
1603 },
1604};
1605
1606static struct resource bfin_gpf_resources[] = {
1607 {
1608 .start = PORTF_FER,
1609 .end = PORTF_MUX + 3,
1610 .flags = IORESOURCE_MEM,
1611 },
1612 {
1613 .start = IRQ_PF0,
1614 .end = IRQ_PF0,
1615 .flags = IORESOURCE_IRQ,
1616 },
1617};
1618
1619static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = {
1620 .port_pin_base = GPIO_PF0,
1621 .port_width = GPIO_BANKSIZE,
1622 .pint_id = 4,
1623 .pint_assign = false,
1624 .pint_map = 1,
1625};
1626
1627static struct platform_device bfin_gpf_device = {
1628 .name = ADI_GPIO_DEVNAME,
1629 .id = 5,
1630 .num_resources = ARRAY_SIZE(bfin_gpf_resources),
1631 .resource = bfin_gpf_resources,
1632 .dev = {
1633 .platform_data = &bfin_gpf_pdata, /* Passed to driver */
1634 },
1635};
1636
1637static struct resource bfin_gpg_resources[] = {
1638 {
1639 .start = PORTG_FER,
1640 .end = PORTG_MUX + 3,
1641 .flags = IORESOURCE_MEM,
1642 },
1643 {
1644 .start = IRQ_PG0,
1645 .end = IRQ_PG0,
1646 .flags = IORESOURCE_IRQ,
1647 },
1648};
1649
1650static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = {
1651 .port_pin_base = GPIO_PG0,
1652 .port_width = GPIO_BANKSIZE,
1653 .pint_id = 5,
1654 .pint_assign = false,
1655 .pint_map = 1,
1656};
1657
1658static struct platform_device bfin_gpg_device = {
1659 .name = ADI_GPIO_DEVNAME,
1660 .id = 6,
1661 .num_resources = ARRAY_SIZE(bfin_gpg_resources),
1662 .resource = bfin_gpg_resources,
1663 .dev = {
1664 .platform_data = &bfin_gpg_pdata, /* Passed to driver */
1665 },
1666};
1667
1668#endif
1669
c4a2c58d 1670#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
bbca5c6d
SM		 1671#include <linux/input.h>
1672#include <linux/gpio_keys.h>
1673
1674static struct gpio_keys_button bfin_gpio_keys_table[] = {
1675 {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
1676 {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
1677};
1678
1679static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1680 .buttons = bfin_gpio_keys_table,
1681 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1682};
1683
1684static struct platform_device bfin_device_gpiokeys = {
1685 .name = "gpio-keys",
1686 .dev = {
1687 .platform_data = &bfin_gpio_keys_data,
1688 },
1689};
1690#endif
1691
22a82628 1692static struct spi_board_info bfin_spi_board_info[] __initdata = {
c4a2c58d 1693#if IS_ENABLED(CONFIG_MTD_M25P80)
22a82628
SZ		 1694 {
1695 /* the modalias must be the same as spi device driver name */
1696 .modalias = "m25p80", /* Name of spi_driver for this device */
1697 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
1698 .bus_num = 0, /* Framework bus number */
54e4ff4d 1699 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
22a82628
SZ		 1700 .platform_data = &bfin_spi_flash_data,
1701 .controller_data = &spi_flash_chip_info,
1702 .mode = SPI_MODE_3,
1703 },
1704#endif
c4a2c58d 1705#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877)
22a82628
SZ		 1706 {
1707 .modalias = "ad7877",
1708 .platform_data = &bfin_ad7877_ts_info,
2cdd7008 1709 .irq = IRQ_PD9,
22a82628
SZ		 1710 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
1711 .bus_num = 0,
54e4ff4d 1712 .chip_select = MAX_CTRL_CS + GPIO_PC15, /* SPI_SSEL4 */
22a82628
SZ		 1713 },
1714#endif
c4a2c58d 1715#if IS_ENABLED(CONFIG_SPI_SPIDEV)
22a82628
SZ		 1716 {
1717 .modalias = "spidev",
1718 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
1719 .bus_num = 0,
54e4ff4d 1720 .chip_select = MAX_CTRL_CS + GPIO_PD11, /* SPI_SSEL1*/
22a82628
SZ		 1721 .controller_data = &spidev_chip_info,
1722 },
1723#endif
c4a2c58d 1724#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI)
22a82628
SZ		 1725 {
1726 .modalias = "adxl34x",
1727 .platform_data = &adxl34x_info,
1728 .irq = IRQ_PC5,
1729 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1730 .bus_num = 1,
1731 .chip_select = 2,
1732 .mode = SPI_MODE_3,
1733 },
1734#endif
1735};
766e3721 1736#if IS_ENABLED(CONFIG_SPI_ADI_V3)
22a82628
SZ		 1737/* SPI (0) */
1738static struct resource bfin_spi0_resource[] = {
1739 {
1740 .start = SPI0_REGBASE,
1741 .end = SPI0_REGBASE + 0xFF,
1742 .flags = IORESOURCE_MEM,
1743 },
1744 {
1745 .start = CH_SPI0_TX,
1746 .end = CH_SPI0_TX,
1747 .flags = IORESOURCE_DMA,
1748 },
1749 {
1750 .start = CH_SPI0_RX,
1751 .end = CH_SPI0_RX,
1752 .flags = IORESOURCE_DMA,
1753 },
1754};
1755
1756/* SPI (1) */
1757static struct resource bfin_spi1_resource[] = {
1758 {
1759 .start = SPI1_REGBASE,
1760 .end = SPI1_REGBASE + 0xFF,
1761 .flags = IORESOURCE_MEM,
1762 },
1763 {
1764 .start = CH_SPI1_TX,
1765 .end = CH_SPI1_TX,
1766 .flags = IORESOURCE_DMA,
1767 },
1768 {
1769 .start = CH_SPI1_RX,
1770 .end = CH_SPI1_RX,
1771 .flags = IORESOURCE_DMA,
1772 },
1773
1774};
1775
1776/* SPI controller data */
766e3721 1777static struct adi_spi3_master bf60x_spi_master_info0 = {
2cdd7008 1778 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
22a82628
SZ		 1779 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1780};
1781
1782static struct platform_device bf60x_spi_master0 = {
766e3721 1783 .name = "adi-spi3",
22a82628
SZ		 1784 .id = 0, /* Bus number */
1785 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1786 .resource = bfin_spi0_resource,
1787 .dev = {
1788 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1789 },
1790};
1791
766e3721 1792static struct adi_spi3_master bf60x_spi_master_info1 = {
2cdd7008 1793 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
22a82628
SZ		 1794 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1795};
1796
1797static struct platform_device bf60x_spi_master1 = {
766e3721 1798 .name = "adi-spi3",
22a82628
SZ		 1799 .id = 1, /* Bus number */
1800 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1801 .resource = bfin_spi1_resource,
1802 .dev = {
1803 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1804 },
1805};
1806#endif /* spi master and devices */
1807
c4a2c58d 1808#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
cf93feb3
SZ		 1809static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1810
22a82628
SZ		 1811static struct resource bfin_twi0_resource[] = {
1812 [0] = {
1813 .start = TWI0_CLKDIV,
1814 .end = TWI0_CLKDIV + 0xFF,
1815 .flags = IORESOURCE_MEM,
1816 },
1817 [1] = {
1818 .start = IRQ_TWI0,
1819 .end = IRQ_TWI0,
1820 .flags = IORESOURCE_IRQ,
1821 },
1822};
1823
1824static struct platform_device i2c_bfin_twi0_device = {
1825 .name = "i2c-bfin-twi",
1826 .id = 0,
1827 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1828 .resource = bfin_twi0_resource,
cf93feb3
SZ		 1829 .dev = {
1830 .platform_data = &bfin_twi0_pins,
1831 },
22a82628
SZ		 1832};
1833
cf93feb3
SZ		 1834static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1835
22a82628
SZ		 1836static struct resource bfin_twi1_resource[] = {
1837 [0] = {
1838 .start = TWI1_CLKDIV,
1839 .end = TWI1_CLKDIV + 0xFF,
1840 .flags = IORESOURCE_MEM,
1841 },
1842 [1] = {
1843 .start = IRQ_TWI1,
1844 .end = IRQ_TWI1,
1845 .flags = IORESOURCE_IRQ,
1846 },
1847};
1848
1849static struct platform_device i2c_bfin_twi1_device = {
1850 .name = "i2c-bfin-twi",
1851 .id = 1,
1852 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1853 .resource = bfin_twi1_resource,
cf93feb3
SZ		 1854 .dev = {
1855 .platform_data = &bfin_twi1_pins,
1856 },
22a82628
SZ		 1857};
1858#endif
1859
1860static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
c4a2c58d 1861#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C)
22a82628
SZ		 1862 {
1863 I2C_BOARD_INFO("adxl34x", 0x53),
1864 .irq = IRQ_PC5,
1865 .platform_data = (void *)&adxl34x_info,
1866 },
1867#endif
c4a2c58d 1868#if IS_ENABLED(CONFIG_SND_SOC_ADAU1761)
22a82628
SZ		 1869 {
1870 I2C_BOARD_INFO("adau1761", 0x38),
1871 .platform_data = (void *)&adau1761_info
1872 },
1873#endif
c4a2c58d 1874#if IS_ENABLED(CONFIG_SND_SOC_SSM2602)
335dd559
SJ		 1875 {
1876 I2C_BOARD_INFO("ssm2602", 0x1b),
1877 },
1878#endif
22a82628
SZ		 1879};
1880
1881static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1882};
1883
1884static const unsigned int cclk_vlev_datasheet[] =
1885{
1886/*
1887 * Internal VLEV BF54XSBBC1533
1888 ****temporarily using these values until data sheet is updated
1889 */
1890 VRPAIR(VLEV_085, 150000000),
1891 VRPAIR(VLEV_090, 250000000),
1892 VRPAIR(VLEV_110, 276000000),
1893 VRPAIR(VLEV_115, 301000000),
1894 VRPAIR(VLEV_120, 525000000),
1895 VRPAIR(VLEV_125, 550000000),
1896 VRPAIR(VLEV_130, 600000000),
1897};
1898
1899static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1900 .tuple_tab = cclk_vlev_datasheet,
1901 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1902 .vr_settling_time = 25 /* us */,
1903};
1904
1905static struct platform_device bfin_dpmc = {
1906 .name = "bfin dpmc",
1907 .dev = {
1908 .platform_data = &bfin_dmpc_vreg_data,
1909 },
1910};
1911
1912static struct platform_device *ezkit_devices[] __initdata = {
1913
1914 &bfin_dpmc,
54e4ff4d
SZ		 1915#if defined(CONFIG_PINCTRL_ADI2)
1916 &bfin_pinctrl_device,
1917 &bfin_pint0_device,
1918 &bfin_pint1_device,
1919 &bfin_pint2_device,
1920 &bfin_pint3_device,
1921 &bfin_pint4_device,
1922 &bfin_pint5_device,
1923 &bfin_gpa_device,
1924 &bfin_gpb_device,
1925 &bfin_gpc_device,
1926 &bfin_gpd_device,
1927 &bfin_gpe_device,
1928 &bfin_gpf_device,
1929 &bfin_gpg_device,
1930#endif
22a82628 1931
c4a2c58d 1932#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
22a82628
SZ		 1933 &rtc_device,
1934#endif
1935
c4a2c58d 1936#if IS_ENABLED(CONFIG_SERIAL_BFIN)
22a82628
SZ		 1937#ifdef CONFIG_SERIAL_BFIN_UART0
1938 &bfin_uart0_device,
1939#endif
1940#ifdef CONFIG_SERIAL_BFIN_UART1
1941 &bfin_uart1_device,
1942#endif
1943#endif
1944
c4a2c58d 1945#if IS_ENABLED(CONFIG_BFIN_SIR)
22a82628
SZ		 1946#ifdef CONFIG_BFIN_SIR0
1947 &bfin_sir0_device,
1948#endif
1949#ifdef CONFIG_BFIN_SIR1
1950 &bfin_sir1_device,
1951#endif
1952#endif
1953
c4a2c58d 1954#if IS_ENABLED(CONFIG_STMMAC_ETH)
22a82628
SZ		 1955 &bfin_eth_device,
1956#endif
1957
c4a2c58d 1958#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
22a82628
SZ		 1959 &musb_device,
1960#endif
1961
c4a2c58d 1962#if IS_ENABLED(CONFIG_USB_ISP1760_HCD)
22a82628
SZ		 1963 &bfin_isp1760_device,
1964#endif
1965
c4a2c58d 1966#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
22a82628
SZ		 1967#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1968 &bfin_sport0_uart_device,
1969#endif
1970#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1971 &bfin_sport1_uart_device,
1972#endif
1973#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1974 &bfin_sport2_uart_device,
1975#endif
1976#endif
1977
c4a2c58d 1978#if IS_ENABLED(CONFIG_CAN_BFIN)
22a82628
SZ		 1979 &bfin_can0_device,
1980#endif
1981
c4a2c58d 1982#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
22a82628
SZ		 1983 &bfin_nand_device,
1984#endif
1985
c4a2c58d 1986#if IS_ENABLED(CONFIG_SDH_BFIN)
22a82628
SZ		 1987 &bfin_sdh_device,
1988#endif
1989
766e3721 1990#if IS_ENABLED(CONFIG_SPI_ADI_V3)
22a82628
SZ		 1991 &bf60x_spi_master0,
1992 &bf60x_spi_master1,
1993#endif
1994
c4a2c58d 1995#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
22a82628
SZ		 1996 &bfin_rotary_device,
1997#endif
1998
c4a2c58d 1999#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
22a82628
SZ		 2000 &i2c_bfin_twi0_device,
2001#if !defined(CONFIG_BF542)
2002 &i2c_bfin_twi1_device,
2003#endif
2004#endif
2005
2006#if defined(CONFIG_BFIN_CRC)
2007 &bfin_crc0_device,
2008 &bfin_crc1_device,
2009#endif
c21e783b
SZ		 2010#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
2011 &bfin_crypto_crc_device,
2012#endif
22a82628 2013
c4a2c58d 2014#if IS_ENABLED(CONFIG_KEYBOARD_GPIO)
22a82628
SZ		 2015 &bfin_device_gpiokeys,
2016#endif
2017
c4a2c58d 2018#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
22a82628
SZ		 2019 &ezkit_flash_device,
2020#endif
c4a2c58d 2021#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
22a82628
SZ		 2022 &bfin_i2s_pcm,
2023#endif
c4a2c58d 2024#if IS_ENABLED(CONFIG_SND_BF6XX_SOC_I2S)
22a82628
SZ		 2025 &bfin_i2s,
2026#endif
c4a2c58d 2027#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1836)
63f49dce
SJ		 2028 &bfin_ad1836_machine,
2029#endif
c4a2c58d 2030#if IS_ENABLED(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61)
22a82628
SZ		 2031 &adau1761_device,
2032#endif
c4a2c58d 2033#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE)
22a82628
SZ		 2034 &bfin_capture_device,
2035#endif
c4a2c58d 2036#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_DISPLAY)
e942d619
SJ		 2037 &bfin_display_device,
2038#endif
2039
22a82628
SZ		 2040};
2041
54e4ff4d
SZ		 2042/* Pin control settings */
2043static struct pinctrl_map __initdata bfin_pinmux_map[] = {
2044 /* per-device maps */
2045 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"),
2046 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"),
2047 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"),
2048 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"),
2049 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"),
2050 PIN_MAP_MUX_GROUP_DEFAULT("stmmaceth.0", "pinctrl-adi2.0", NULL, "eth0"),
766e3721
SJ		 2051 PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.0", "pinctrl-adi2.0", NULL, "spi0"),
2052 PIN_MAP_MUX_GROUP_DEFAULT("adi-spi3.1", "pinctrl-adi2.0", NULL, "spi1"),
54e4ff4d
SZ		 2053 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"),
2054 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"),
2055 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"),
2056 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"),
2057 PIN_MAP_MUX_GROUP_DEFAULT("physmap-flash.0", "pinctrl-adi2.0", NULL, "smc0"),
2058 PIN_MAP_MUX_GROUP_DEFAULT("bf609_nl8048.2", "pinctrl-adi2.0", NULL, "ppi2_16b"),
2059 PIN_MAP_MUX_GROUP_DEFAULT("bfin_display.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
c4a2c58d 2060#if IS_ENABLED(CONFIG_VIDEO_MT9M114)
54e4ff4d 2061 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_8b"),
c4a2c58d 2062#elif IS_ENABLED(CONFIG_VIDEO_VS6624)
54e4ff4d
SZ		 2063 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_16b"),
2064#else
2065 PIN_MAP_MUX_GROUP_DEFAULT("bfin_capture.0", "pinctrl-adi2.0", NULL, "ppi0_24b"),
2066#endif
2067 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"),
2068 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"),
2069 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"),
2070 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"),
2071 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"),
2072 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"),
2073};
2074
22a82628
SZ		 2075static int __init ezkit_init(void)
2076{
2077 printk(KERN_INFO "%s(): registering device resources\n", __func__);
2078
54e4ff4d
SZ		 2079 /* Initialize pinmuxing */
2080 pinctrl_register_mappings(bfin_pinmux_map,
2081 ARRAY_SIZE(bfin_pinmux_map));
2082
22a82628
SZ		 2083 i2c_register_board_info(0, bfin_i2c_board_info0,
2084 ARRAY_SIZE(bfin_i2c_board_info0));
2085 i2c_register_board_info(1, bfin_i2c_board_info1,
2086 ARRAY_SIZE(bfin_i2c_board_info1));
2087
22a82628
SZ		 2088 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
2089
2090 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
2091
2092 return 0;
2093}
2094
2095arch_initcall(ezkit_init);
2096
2097static struct platform_device *ezkit_early_devices[] __initdata = {
2098#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
2099#ifdef CONFIG_SERIAL_BFIN_UART0
2100 &bfin_uart0_device,
2101#endif
2102#ifdef CONFIG_SERIAL_BFIN_UART1
2103 &bfin_uart1_device,
2104#endif
2105#endif
22a82628
SZ		 2106};
2107
2108void __init native_machine_early_platform_add_devices(void)
2109{
2110 printk(KERN_INFO "register early platform devices\n");
2111 early_platform_add_devices(ezkit_early_devices,
2112 ARRAY_SIZE(ezkit_early_devices));
2113}
Linux kernel - Deliverables
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