[deliverable/linux.git] / arch / blackfin / mach-bf609 / pm.c

/*
 * Blackfin bf609 power management
 *
 * Copyright 2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2
 */

#include <linux/suspend.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/syscore_ops.h>

#include <asm/dpmc.h>
#include <asm/pm.h>
#include <mach/pm.h>
#include <asm/blackfin.h>
#include <asm/mem_init.h>

/***********************************************************/
/*                                                         */
/* Wakeup Actions for DPM_RESTORE                          */
/*                                                         */
/***********************************************************/
#define BITP_ROM_WUA_CHKHDR             24
#define BITP_ROM_WUA_DDRLOCK            7
#define BITP_ROM_WUA_DDRDLLEN           6
#define BITP_ROM_WUA_DDR                5
#define BITP_ROM_WUA_CGU                4
#define BITP_ROM_WUA_MEMBOOT            2
#define BITP_ROM_WUA_EN                 1

#define BITM_ROM_WUA_CHKHDR             (0xFF000000)
#define ENUM_ROM_WUA_CHKHDR_AD                  0xAD000000

#define BITM_ROM_WUA_DDRLOCK            (0x00000080)
#define BITM_ROM_WUA_DDRDLLEN           (0x00000040)
#define BITM_ROM_WUA_DDR                (0x00000020)
#define BITM_ROM_WUA_CGU                (0x00000010)
#define BITM_ROM_WUA_MEMBOOT            (0x00000002)
#define BITM_ROM_WUA_EN                 (0x00000001)

/***********************************************************/
/*                                                         */
/* Syscontrol                                              */
/*                                                         */
/***********************************************************/
#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN  28    /* unlocks CGU_CTL register */
#define BITP_ROM_SYSCTRL_WUA_OVERRIDE   24
#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN   20    /* Saves the DDR DLL and PADS registers to the DPM registers */
#define BITP_ROM_SYSCTRL_WUA_DDR        19    /* Saves the DDR registers to the DPM registers */
#define BITP_ROM_SYSCTRL_WUA_CGU        18    /* Saves the CGU registers into DPM registers */
#define BITP_ROM_SYSCTRL_WUA_DPMWRITE   17    /* Saves the Syscontrol structure structure contents into DPM registers */
#define BITP_ROM_SYSCTRL_WUA_EN         16    /* reads current PLL and DDR configuration into structure */
#define BITP_ROM_SYSCTRL_DDR_WRITE      13    /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
#define BITP_ROM_SYSCTRL_DDR_READ       12    /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
#define BITP_ROM_SYSCTRL_CGU_AUTODIS    11    /* Disables auto handling of UPDT and ALGN fields */
#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL  7    /* access CGU_CLKOUTSEL register */
#define BITP_ROM_SYSCTRL_CGU_DIV        6    /* access CGU_DIV register */
#define BITP_ROM_SYSCTRL_CGU_STAT       5    /* access CGU_STAT register */
#define BITP_ROM_SYSCTRL_CGU_CTL        4    /* access CGU_CTL register */
#define BITP_ROM_SYSCTRL_CGU_RTNSTAT    2    /* Update structure STAT field upon error */
#define BITP_ROM_SYSCTRL_WRITE          1    /* write registers */
#define BITP_ROM_SYSCTRL_READ           0    /* read registers */

#define BITM_ROM_SYSCTRL_CGU_READ       (0x00000001)    /* Read CGU registers */
#define BITM_ROM_SYSCTRL_CGU_WRITE      (0x00000002)    /* Write registers */
#define BITM_ROM_SYSCTRL_CGU_RTNSTAT    (0x00000004)    /* Update structure STAT field upon error or after a write operation */
#define BITM_ROM_SYSCTRL_CGU_CTL        (0x00000010)    /* Access CGU_CTL register */
#define BITM_ROM_SYSCTRL_CGU_STAT       (0x00000020)    /* Access CGU_STAT register */
#define BITM_ROM_SYSCTRL_CGU_DIV        (0x00000040)    /* Access CGU_DIV register */
#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL  (0x00000080)    /* Access CGU_CLKOUTSEL register */
#define BITM_ROM_SYSCTRL_CGU_AUTODIS    (0x00000800)    /* Disables auto handling of UPDT and ALGN fields */
#define BITM_ROM_SYSCTRL_DDR_READ       (0x00001000)    /* Reads the contents of the DDR registers and stores them into the structure */
#define BITM_ROM_SYSCTRL_DDR_WRITE      (0x00002000)    /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
#define BITM_ROM_SYSCTRL_WUA_EN         (0x00010000)    /* Wakeup entry or exit opertation enable */
#define BITM_ROM_SYSCTRL_WUA_DPMWRITE   (0x00020000)    /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
#define BITM_ROM_SYSCTRL_WUA_CGU        (0x00040000)    /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
#define BITM_ROM_SYSCTRL_WUA_DDR        (0x00080000)    /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN   (0x00100000)    /* Enables saving/restoring of the DDR DLLCTL register */
#define BITM_ROM_SYSCTRL_WUA_OVERRIDE   (0x01000000)
#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN  (0x10000000)    /* Unlocks the CGU_CTL register */


/* Structures for the syscontrol() function */
struct STRUCT_ROM_SYSCTRL {
	uint32_t ulCGU_CTL;
	uint32_t ulCGU_STAT;
	uint32_t ulCGU_DIV;
	uint32_t ulCGU_CLKOUTSEL;
	uint32_t ulWUA_Flags;
	uint32_t ulWUA_BootAddr;
	uint32_t ulWUA_User;
	uint32_t ulDDR_CTL;
	uint32_t ulDDR_CFG;
	uint32_t ulDDR_TR0;
	uint32_t ulDDR_TR1;
	uint32_t ulDDR_TR2;
	uint32_t ulDDR_MR;
	uint32_t ulDDR_EMR1;
	uint32_t ulDDR_EMR2;
	uint32_t ulDDR_PADCTL;
	uint32_t ulDDR_DLLCTL;
	uint32_t ulReserved;
};

struct bfin_pm_data {
	uint32_t magic;
	uint32_t resume_addr;
	uint32_t sp;
};

struct bfin_pm_data bf609_pm_data;

struct STRUCT_ROM_SYSCTRL configvalues;
uint32_t dactionflags;

#define FUNC_ROM_SYSCONTROL 0xC8000080
__attribute__((l1_data))
static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;

__attribute__((l1_text))
void bfin_cpu_suspend(void)
{
	__asm__ __volatile__( \
			".align 8;" \
			"idle;" \
			: : \
			);
}

__attribute__((l1_text))
void bf609_ddr_sr(void)
{
	dmc_enter_self_refresh();
}

__attribute__((l1_text))
void bf609_ddr_sr_exit(void)
{
	dmc_exit_self_refresh();

	/* After wake up from deep sleep and exit DDR from self refress mode,
	 * should wait till CGU PLL is locked.
	 */
	while (bfin_read32(CGU0_STAT) & CLKSALGN)
		continue;
}

__attribute__((l1_text))
void bf609_resume_ccbuf(void)
{
	bfin_write32(DPM0_CCBF_EN, 3);
	bfin_write32(DPM0_CTL, 2);

	while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
}

__attribute__((l1_text))
void bfin_hibernate_syscontrol(void)
{
	configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
		| BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);

	dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
		| BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
		| BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);

	bfrom_SysControl(dactionflags, &configvalues, NULL);

	bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
}

#ifndef CONFIG_BF60x
# define SIC_SYSIRQ(irq)	(irq - (IRQ_CORETMR + 1))
#else
# define SIC_SYSIRQ(irq)	((irq) - IVG15)
#endif
asmlinkage void enter_deepsleep(void);

__attribute__((l1_text))
void bfin_deepsleep(unsigned long mask)
{
	bfin_write32(DPM0_WAKE_EN, 0x10);
	bfin_write32(DPM0_WAKE_POL, 0x10);
	SSYNC();
	enter_deepsleep();
}

void bfin_hibernate(unsigned long mask)
{
	bfin_write32(DPM0_WAKE_EN, 0x10);
	bfin_write32(DPM0_WAKE_POL, 0x10);
	bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
	bfin_write32(DPM0_HIB_DIS, 0xFFFF);

	bf609_hibernate();
}

void bf609_cpu_pm_enter(suspend_state_t state)
{
	int error;
	unsigned long wakeup = 0;
	unsigned long wakeup_pol = 0;

#ifdef CONFIG_PM_BFIN_WAKE_PA15
	wakeup |= PA15WE;
# if CONFIG_PM_BFIN_WAKE_PA15_POL
	wakeup_pol |= PA15WE;
# endif
#endif

#ifdef CONFIG_PM_BFIN_WAKE_PB15
	wakeup |= PB15WE;
# if CONFIG_PM_BFIN_WAKE_PA15_POL
	wakeup_pol |= PB15WE;
# endif
#endif

#ifdef CONFIG_PM_BFIN_WAKE_PC15
	wakeup |= PC15WE;
# if CONFIG_PM_BFIN_WAKE_PC15_POL
	wakeup_pol |= PC15WE;
# endif
#endif

#ifdef CONFIG_PM_BFIN_WAKE_PD06
	wakeup |= PD06WE;
# if CONFIG_PM_BFIN_WAKE_PD06_POL
	wakeup_pol |= PD06WE;
# endif
#endif

#ifdef CONFIG_PM_BFIN_WAKE_PE12
	wakeup |= PE12WE;
# if CONFIG_PM_BFIN_WAKE_PE12_POL
	wakeup_pol |= PE12WE;
# endif
#endif

#ifdef CONFIG_PM_BFIN_WAKE_PG04
	wakeup |= PG04WE;
# if CONFIG_PM_BFIN_WAKE_PG04_POL
	wakeup_pol |= PG04WE;
# endif
#endif

#ifdef CONFIG_PM_BFIN_WAKE_PG13
	wakeup |= PG13WE;
# if CONFIG_PM_BFIN_WAKE_PG13_POL
	wakeup_pol |= PG13WE;
# endif
#endif

#ifdef CONFIG_PM_BFIN_WAKE_USB
	wakeup |= USBWE;
# if CONFIG_PM_BFIN_WAKE_USB_POL
	wakeup_pol |= USBWE;
# endif
#endif

	error = irq_set_irq_wake(255, 1);
	if(error < 0)
		printk(KERN_DEBUG "Unable to get irq wake\n");
	error = irq_set_irq_wake(231, 1);
	if (error < 0)
		printk(KERN_DEBUG "Unable to get irq wake\n");

	if (state == PM_SUSPEND_STANDBY)
		bfin_deepsleep(wakeup);
	else {
		bfin_hibernate(wakeup);
	}

}

int bf609_cpu_pm_prepare(void)
{
	return 0;
}

void bf609_cpu_pm_finish(void)
{

}

static struct bfin_cpu_pm_fns bf609_cpu_pm = {
	.enter          = bf609_cpu_pm_enter,
	.prepare        = bf609_cpu_pm_prepare,
	.finish         = bf609_cpu_pm_finish,
};

#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static void smc_pm_syscore_suspend(void)
{
	bf609_nor_flash_exit();
}

static void smc_pm_syscore_resume(void)
{
	bf609_nor_flash_init();
}

static struct syscore_ops smc_pm_syscore_ops = {
	.suspend        = smc_pm_syscore_suspend,
	.resume         = smc_pm_syscore_resume,
};
#endif

static irqreturn_t test_isr(int irq, void *dev_id)
{
	printk(KERN_DEBUG "gpio irq %d\n", irq);
	return IRQ_HANDLED;
}

static irqreturn_t dpm0_isr(int irq, void *dev_id)
{
	bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
	bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
	return IRQ_HANDLED;
}
#endif

static int __init bf609_init_pm(void)
{
	int irq;
	int error;

#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
	register_syscore_ops(&smc_pm_syscore_ops);
#endif

#ifdef CONFIG_PM_BFIN_WAKE_PE12
	irq = gpio_to_irq(GPIO_PE12);
	if (irq < 0) {
		error = irq;
		printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
				GPIO_PE12, error);
	}

	error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL);
	if(error < 0)
		printk(KERN_DEBUG "Unable to get irq\n");
#endif

	error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL);
	if(error < 0)
		printk(KERN_DEBUG "Unable to get irq\n");

	error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL);
	if (error < 0)
		printk(KERN_DEBUG "Unable to get irq\n");

	bfin_cpu_pm = &bf609_cpu_pm;
	return 0;
}

late_initcall(bf609_init_pm);
Commit	Line	Data
93f89519 SM	1	/*
	2	* Blackfin bf609 power management
	3	*
	4	* Copyright 2011 Analog Devices Inc.
	5	*
	6	* Licensed under the GPL-2
	7	*/
	8
	9	#include <linux/suspend.h>
	10	#include <linux/io.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/gpio.h>
	13	#include <linux/irq.h>
93f89519	14	#include <linux/delay.h>
923680cb	15	#include <linux/syscore_ops.h>
93f89519 SM	16
	17	#include <asm/dpmc.h>
	18	#include <asm/pm.h>
	19	#include <mach/pm.h>
	20	#include <asm/blackfin.h>
c7e48e1e	21	#include <asm/mem_init.h>
93f89519 SM	22
	23	/***********************************************************/
	24	/* */
	25	/* Wakeup Actions for DPM_RESTORE */
	26	/* */
	27	/***********************************************************/
	28	#define BITP_ROM_WUA_CHKHDR 24
	29	#define BITP_ROM_WUA_DDRLOCK 7
	30	#define BITP_ROM_WUA_DDRDLLEN 6
	31	#define BITP_ROM_WUA_DDR 5
	32	#define BITP_ROM_WUA_CGU 4
	33	#define BITP_ROM_WUA_MEMBOOT 2
	34	#define BITP_ROM_WUA_EN 1
	35
	36	#define BITM_ROM_WUA_CHKHDR (0xFF000000)
	37	#define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000
	38
	39	#define BITM_ROM_WUA_DDRLOCK (0x00000080)
	40	#define BITM_ROM_WUA_DDRDLLEN (0x00000040)
	41	#define BITM_ROM_WUA_DDR (0x00000020)
	42	#define BITM_ROM_WUA_CGU (0x00000010)
	43	#define BITM_ROM_WUA_MEMBOOT (0x00000002)
	44	#define BITM_ROM_WUA_EN (0x00000001)
	45
	46	/***********************************************************/
	47	/* */
	48	/* Syscontrol */
	49	/* */
	50	/***********************************************************/
	51	#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */
	52	#define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24
	53	#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */
	54	#define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */
	55	#define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */
	56	#define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */
	57	#define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */
	58	#define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
	59	#define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
	60	#define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */
	61	#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */
	62	#define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */
	63	#define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */
	64	#define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */
	65	#define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */
	66	#define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */
	67	#define BITP_ROM_SYSCTRL_READ 0 /* read registers */
	68
	69	#define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */
	70	#define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */
	71	#define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */
	72	#define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */
	73	#define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */
	74	#define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */
	75	#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */
	76	#define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */
	77	#define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */
	78	#define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
	79	#define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */
	80	#define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
	81	#define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
	82	#define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
	83	#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */
	84	#define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000)
	85	#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */
86
87
88	/* Structures for the syscontrol() function */
89	struct STRUCT_ROM_SYSCTRL {
90	uint32_t ulCGU_CTL;
91	uint32_t ulCGU_STAT;
92	uint32_t ulCGU_DIV;
93	uint32_t ulCGU_CLKOUTSEL;
94	uint32_t ulWUA_Flags;
95	uint32_t ulWUA_BootAddr;
96	uint32_t ulWUA_User;
97	uint32_t ulDDR_CTL;
98	uint32_t ulDDR_CFG;
99	uint32_t ulDDR_TR0;
100	uint32_t ulDDR_TR1;
101	uint32_t ulDDR_TR2;
102	uint32_t ulDDR_MR;
103	uint32_t ulDDR_EMR1;
104	uint32_t ulDDR_EMR2;
105	uint32_t ulDDR_PADCTL;
106	uint32_t ulDDR_DLLCTL;
107	uint32_t ulReserved;
108	};
109
110	struct bfin_pm_data {
111	uint32_t magic;
112	uint32_t resume_addr;
113	uint32_t sp;
114	};
115
116	struct bfin_pm_data bf609_pm_data;
117
118	struct STRUCT_ROM_SYSCTRL configvalues;
119	uint32_t dactionflags;
120
121	#define FUNC_ROM_SYSCONTROL 0xC8000080
122	__attribute__((l1_data))
123	static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL settings, void reserved) = (void *)FUNC_ROM_SYSCONTROL;
124
125	__attribute__((l1_text))
126	void bfin_cpu_suspend(void)
127	{
128	__asm__ __volatile__( \
129	".align 8;" \
130	"idle;" \
131	: : \
132	);
133	}
134
135	__attribute__((l1_text))
c7e48e1e	136	void bf609_ddr_sr(void)
93f89519	137	{
c7e48e1e	138	dmc_enter_self_refresh();
93f89519 SM	139	}
	140
	141	__attribute__((l1_text))
c7e48e1e	142	void bf609_ddr_sr_exit(void)
93f89519	143	{
c7e48e1e	144	dmc_exit_self_refresh();
93f89519	145
c7e48e1e SZ	146	/* After wake up from deep sleep and exit DDR from self refress mode,
	147	* should wait till CGU PLL is locked.
	148	*/
	149	while (bfin_read32(CGU0_STAT) & CLKSALGN)
93f89519 SM	150	continue;
	151	}
	152
	153	__attribute__((l1_text))
c7e48e1e	154	void bf609_resume_ccbuf(void)
93f89519	155	{
c7e48e1e SZ	156	bfin_write32(DPM0_CCBF_EN, 3);
c7e48e1e SZ	157	bfin_write32(DPM0_CTL, 2);
93f89519	158
c7e48e1e	159	while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
93f89519 SM	160	}
	161
	162	__attribute__((l1_text))
	163	void bfin_hibernate_syscontrol(void)
	164	{
	165	configvalues.ulWUA_Flags = (0xAD000000 \| BITM_ROM_WUA_EN
	166	\| BITM_ROM_WUA_CGU \| BITM_ROM_WUA_DDR \| BITM_ROM_WUA_DDRDLLEN);
	167
	168	dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
	169	\| BITM_ROM_SYSCTRL_WUA_DPMWRITE \| BITM_ROM_SYSCTRL_WUA_CGU
	170	\| BITM_ROM_SYSCTRL_WUA_DDR \| BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
	171
	172	bfrom_SysControl(dactionflags, &configvalues, NULL);
	173
	174	bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) \| 4);
	175	}
	176
	177	#ifndef CONFIG_BF60x
	178	# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
	179	#else
	180	# define SIC_SYSIRQ(irq) ((irq) - IVG15)
	181	#endif
c7e48e1e SZ	182	asmlinkage void enter_deepsleep(void);
	183
	184	__attribute__((l1_text))
	185	void bfin_deepsleep(unsigned long mask)
	186	{
	187	bfin_write32(DPM0_WAKE_EN, 0x10);
	188	bfin_write32(DPM0_WAKE_POL, 0x10);
	189	SSYNC();
	190	enter_deepsleep();
	191	}
	192
93f89519 SM	193	void bfin_hibernate(unsigned long mask)
	194	{
	195	bfin_write32(DPM0_WAKE_EN, 0x10);
	196	bfin_write32(DPM0_WAKE_POL, 0x10);
	197	bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
	198	bfin_write32(DPM0_HIB_DIS, 0xFFFF);
	199
93f89519 SM	200	bf609_hibernate();
	201	}
	202
	203	void bf609_cpu_pm_enter(suspend_state_t state)
	204	{
	205	int error;
0fbd88ca SM	206	unsigned long wakeup = 0;
	207	unsigned long wakeup_pol = 0;
	208
	209	#ifdef CONFIG_PM_BFIN_WAKE_PA15
	210	wakeup \|= PA15WE;
	211	# if CONFIG_PM_BFIN_WAKE_PA15_POL
	212	wakeup_pol \|= PA15WE;
	213	# endif
	214	#endif
	215
	216	#ifdef CONFIG_PM_BFIN_WAKE_PB15
	217	wakeup \|= PB15WE;
	218	# if CONFIG_PM_BFIN_WAKE_PA15_POL
	219	wakeup_pol \|= PB15WE;
	220	# endif
	221	#endif
	222
	223	#ifdef CONFIG_PM_BFIN_WAKE_PC15
	224	wakeup \|= PC15WE;
	225	# if CONFIG_PM_BFIN_WAKE_PC15_POL
	226	wakeup_pol \|= PC15WE;
	227	# endif
	228	#endif
	229
	230	#ifdef CONFIG_PM_BFIN_WAKE_PD06
	231	wakeup \|= PD06WE;
	232	# if CONFIG_PM_BFIN_WAKE_PD06_POL
	233	wakeup_pol \|= PD06WE;
	234	# endif
	235	#endif
	236
	237	#ifdef CONFIG_PM_BFIN_WAKE_PE12
	238	wakeup \|= PE12WE;
	239	# if CONFIG_PM_BFIN_WAKE_PE12_POL
	240	wakeup_pol \|= PE12WE;
	241	# endif
	242	#endif
	243
	244	#ifdef CONFIG_PM_BFIN_WAKE_PG04
	245	wakeup \|= PG04WE;
	246	# if CONFIG_PM_BFIN_WAKE_PG04_POL
	247	wakeup_pol \|= PG04WE;
	248	# endif
	249	#endif
	250
	251	#ifdef CONFIG_PM_BFIN_WAKE_PG13
	252	wakeup \|= PG13WE;
	253	# if CONFIG_PM_BFIN_WAKE_PG13_POL
	254	wakeup_pol \|= PG13WE;
	255	# endif
	256	#endif
	257
	258	#ifdef CONFIG_PM_BFIN_WAKE_USB
	259	wakeup \|= USBWE;
	260	# if CONFIG_PM_BFIN_WAKE_USB_POL
	261	wakeup_pol \|= USBWE;
	262	# endif
	263	#endif
	264
93f89519 SM	265	error = irq_set_irq_wake(255, 1);
	266	if(error < 0)
	267	printk(KERN_DEBUG "Unable to get irq wake\n");
	268	error = irq_set_irq_wake(231, 1);
	269	if (error < 0)
	270	printk(KERN_DEBUG "Unable to get irq wake\n");
	271
	272	if (state == PM_SUSPEND_STANDBY)
0fbd88ca	273	bfin_deepsleep(wakeup);
93f89519	274	else {
0fbd88ca	275	bfin_hibernate(wakeup);
93f89519	276	}
c7e48e1e	277
93f89519 SM	278	}
	279
	280	int bf609_cpu_pm_prepare(void)
	281	{
	282	return 0;
	283	}
	284
	285	void bf609_cpu_pm_finish(void)
	286	{
	287
	288	}
	289
	290	static struct bfin_cpu_pm_fns bf609_cpu_pm = {
	291	.enter = bf609_cpu_pm_enter,
	292	.prepare = bf609_cpu_pm_prepare,
	293	.finish = bf609_cpu_pm_finish,
	294	};
	295
923680cb SM	296	#if defined(CONFIG_MTD_PHYSMAP) \|\| defined(CONFIG_MTD_PHYSMAP_MODULE)
	297	static void smc_pm_syscore_suspend(void)
	298	{
	299	bf609_nor_flash_exit();
	300	}
	301
	302	static void smc_pm_syscore_resume(void)
	303	{
	304	bf609_nor_flash_init();
	305	}
	306
	307	static struct syscore_ops smc_pm_syscore_ops = {
	308	.suspend = smc_pm_syscore_suspend,
	309	.resume = smc_pm_syscore_resume,
	310	};
	311	#endif
	312
93f89519 SM	313	static irqreturn_t test_isr(int irq, void *dev_id)
	314	{
	315	printk(KERN_DEBUG "gpio irq %d\n", irq);
	316	return IRQ_HANDLED;
	317	}
	318
	319	static irqreturn_t dpm0_isr(int irq, void *dev_id)
	320	{
c7e48e1e SZ	321	bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
c7e48e1e SZ	322	bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
93f89519 SM	323	return IRQ_HANDLED;
93f89519 SM	324	}
c7e48e1e	325	#endif
93f89519 SM	326
	327	static int __init bf609_init_pm(void)
	328	{
	329	int irq;
	330	int error;
93f89519	331
923680cb SM	332	#if defined(CONFIG_MTD_PHYSMAP) \|\| defined(CONFIG_MTD_PHYSMAP_MODULE)
	333	register_syscore_ops(&smc_pm_syscore_ops);
	334	#endif
	335
c7e48e1e	336	#ifdef CONFIG_PM_BFIN_WAKE_PE12
93f89519 SM	337	irq = gpio_to_irq(GPIO_PE12);
	338	if (irq < 0) {
	339	error = irq;
	340	printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
	341	GPIO_PE12, error);
	342	}
	343
	344	error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING \| IRQF_NO_SUSPEND, "gpiope12", NULL);
	345	if(error < 0)
	346	printk(KERN_DEBUG "Unable to get irq\n");
	347	#endif
	348
	349	error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL);
	350	if(error < 0)
	351	printk(KERN_DEBUG "Unable to get irq\n");
	352
	353	error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL);
	354	if (error < 0)
	355	printk(KERN_DEBUG "Unable to get irq\n");
	356
	357	bfin_cpu_pm = &bf609_cpu_pm;
	358	return 0;
	359	}
	360
	361	late_initcall(bf609_init_pm);