projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 24a70cf2 SM |
1 | /* |
| 2 | * arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority | |
| 3 | * | |
| 4 | * Copyright 2012 Analog Devices Inc. | |
| 5 | * | |
| 6 | * Licensed under the GPL-2 or later. | |
| 7 | */ | |
| 8 | ||
| 9 | #include <asm/blackfin.h> | |
| 10 | #include <asm/scb.h> | |
| 11 | ||
| 12 | struct scb_mi_prio scb_data[] = { | |
| 13 | #ifdef CONFIG_SCB0_MI0 | |
| 14 | { REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, { | |
| 15 | CONFIG_SCB0_MI0_SLOT0, | |
| 16 | CONFIG_SCB0_MI0_SLOT1, | |
| 17 | CONFIG_SCB0_MI0_SLOT2, | |
| 18 | CONFIG_SCB0_MI0_SLOT3, | |
| 19 | CONFIG_SCB0_MI0_SLOT4, | |
| 20 | CONFIG_SCB0_MI0_SLOT5, | |
| 21 | CONFIG_SCB0_MI0_SLOT6, | |
| 22 | CONFIG_SCB0_MI0_SLOT7, | |
| 23 | CONFIG_SCB0_MI0_SLOT8, | |
| 24 | CONFIG_SCB0_MI0_SLOT9, | |
| 25 | CONFIG_SCB0_MI0_SLOT10, | |
| 26 | CONFIG_SCB0_MI0_SLOT11, | |
| 27 | CONFIG_SCB0_MI0_SLOT12, | |
| 28 | CONFIG_SCB0_MI0_SLOT13, | |
| 29 | CONFIG_SCB0_MI0_SLOT14, | |
| 30 | CONFIG_SCB0_MI0_SLOT15, | |
| 31 | CONFIG_SCB0_MI0_SLOT16, | |
| 32 | CONFIG_SCB0_MI0_SLOT17, | |
| 33 | CONFIG_SCB0_MI0_SLOT18, | |
| 34 | CONFIG_SCB0_MI0_SLOT19, | |
| 35 | CONFIG_SCB0_MI0_SLOT20, | |
| 36 | CONFIG_SCB0_MI0_SLOT21, | |
| 37 | CONFIG_SCB0_MI0_SLOT22, | |
| 38 | CONFIG_SCB0_MI0_SLOT23, | |
| 39 | CONFIG_SCB0_MI0_SLOT24, | |
| 40 | CONFIG_SCB0_MI0_SLOT25, | |
| 41 | CONFIG_SCB0_MI0_SLOT26, | |
| 42 | CONFIG_SCB0_MI0_SLOT27, | |
| 43 | CONFIG_SCB0_MI0_SLOT28, | |
| 44 | CONFIG_SCB0_MI0_SLOT29, | |
| 45 | CONFIG_SCB0_MI0_SLOT30, | |
| 46 | CONFIG_SCB0_MI0_SLOT31 | |
| 47 | }, | |
| 48 | }, | |
| 49 | #endif | |
| 50 | #ifdef CONFIG_SCB0_MI1 | |
| 51 | { REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, { | |
| 52 | CONFIG_SCB0_MI1_SLOT0, | |
| 53 | CONFIG_SCB0_MI1_SLOT1, | |
| 54 | CONFIG_SCB0_MI1_SLOT2, | |
| 55 | CONFIG_SCB0_MI1_SLOT3, | |
| 56 | CONFIG_SCB0_MI1_SLOT4, | |
| 57 | CONFIG_SCB0_MI1_SLOT5, | |
| 58 | CONFIG_SCB0_MI1_SLOT6, | |
| 59 | CONFIG_SCB0_MI1_SLOT7, | |
| 60 | CONFIG_SCB0_MI1_SLOT8, | |
| 61 | CONFIG_SCB0_MI1_SLOT9, | |
| 62 | CONFIG_SCB0_MI1_SLOT10, | |
| 63 | CONFIG_SCB0_MI1_SLOT11, | |
| 64 | CONFIG_SCB0_MI1_SLOT12, | |
| 65 | CONFIG_SCB0_MI1_SLOT13, | |
| 66 | CONFIG_SCB0_MI1_SLOT14, | |
| 67 | CONFIG_SCB0_MI1_SLOT15, | |
| 68 | CONFIG_SCB0_MI1_SLOT16, | |
| 69 | CONFIG_SCB0_MI1_SLOT17, | |
| 70 | CONFIG_SCB0_MI1_SLOT18, | |
| 71 | CONFIG_SCB0_MI1_SLOT19, | |
| 72 | CONFIG_SCB0_MI1_SLOT20, | |
| 73 | CONFIG_SCB0_MI1_SLOT21, | |
| 74 | CONFIG_SCB0_MI1_SLOT22, | |
| 75 | CONFIG_SCB0_MI1_SLOT23, | |
| 76 | CONFIG_SCB0_MI1_SLOT24, | |
| 77 | CONFIG_SCB0_MI1_SLOT25, | |
| 78 | CONFIG_SCB0_MI1_SLOT26, | |
| 79 | CONFIG_SCB0_MI1_SLOT27, | |
| 80 | CONFIG_SCB0_MI1_SLOT28, | |
| 81 | CONFIG_SCB0_MI1_SLOT29, | |
| 82 | CONFIG_SCB0_MI1_SLOT30, | |
| 83 | CONFIG_SCB0_MI1_SLOT31 | |
| 84 | }, | |
| 85 | }, | |
| 86 | #endif | |
| 87 | #ifdef CONFIG_SCB0_MI2 | |
| 88 | { REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, { | |
| 89 | CONFIG_SCB0_MI2_SLOT0, | |
| 90 | CONFIG_SCB0_MI2_SLOT1, | |
| 91 | CONFIG_SCB0_MI2_SLOT2, | |
| 92 | CONFIG_SCB0_MI2_SLOT3, | |
| 93 | CONFIG_SCB0_MI2_SLOT4, | |
| 94 | CONFIG_SCB0_MI2_SLOT5, | |
| 95 | CONFIG_SCB0_MI2_SLOT6, | |
| 96 | CONFIG_SCB0_MI2_SLOT7, | |
| 97 | CONFIG_SCB0_MI2_SLOT8, | |
| 98 | CONFIG_SCB0_MI2_SLOT9, | |
| 99 | CONFIG_SCB0_MI2_SLOT10, | |
| 100 | CONFIG_SCB0_MI2_SLOT11, | |
| 101 | CONFIG_SCB0_MI2_SLOT12, | |
| 102 | CONFIG_SCB0_MI2_SLOT13, | |
| 103 | CONFIG_SCB0_MI2_SLOT14, | |
| 104 | CONFIG_SCB0_MI2_SLOT15, | |
| 105 | CONFIG_SCB0_MI2_SLOT16, | |
| 106 | CONFIG_SCB0_MI2_SLOT17, | |
| 107 | CONFIG_SCB0_MI2_SLOT18, | |
| 108 | CONFIG_SCB0_MI2_SLOT19, | |
| 109 | CONFIG_SCB0_MI2_SLOT20, | |
| 110 | CONFIG_SCB0_MI2_SLOT21, | |
| 111 | CONFIG_SCB0_MI2_SLOT22, | |
| 112 | CONFIG_SCB0_MI2_SLOT23, | |
| 113 | CONFIG_SCB0_MI2_SLOT24, | |
| 114 | CONFIG_SCB0_MI2_SLOT25, | |
| 115 | CONFIG_SCB0_MI2_SLOT26, | |
| 116 | CONFIG_SCB0_MI2_SLOT27, | |
| 117 | CONFIG_SCB0_MI2_SLOT28, | |
| 118 | CONFIG_SCB0_MI2_SLOT29, | |
| 119 | CONFIG_SCB0_MI2_SLOT30, | |
| 120 | CONFIG_SCB0_MI2_SLOT31 | |
| 121 | }, | |
| 122 | }, | |
| 123 | #endif | |
| 124 | #ifdef CONFIG_SCB0_MI3 | |
| 125 | { REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, { | |
| 126 | CONFIG_SCB0_MI3_SLOT0, | |
| 127 | CONFIG_SCB0_MI3_SLOT1, | |
| 128 | CONFIG_SCB0_MI3_SLOT2, | |
| 129 | CONFIG_SCB0_MI3_SLOT3, | |
| 130 | CONFIG_SCB0_MI3_SLOT4, | |
| 131 | CONFIG_SCB0_MI3_SLOT5, | |
| 132 | CONFIG_SCB0_MI3_SLOT6, | |
| 133 | CONFIG_SCB0_MI3_SLOT7, | |
| 134 | CONFIG_SCB0_MI3_SLOT8, | |
| 135 | CONFIG_SCB0_MI3_SLOT9, | |
| 136 | CONFIG_SCB0_MI3_SLOT10, | |
| 137 | CONFIG_SCB0_MI3_SLOT11, | |
| 138 | CONFIG_SCB0_MI3_SLOT12, | |
| 139 | CONFIG_SCB0_MI3_SLOT13, | |
| 140 | CONFIG_SCB0_MI3_SLOT14, | |
| 141 | CONFIG_SCB0_MI3_SLOT15, | |
| 142 | CONFIG_SCB0_MI3_SLOT16, | |
| 143 | CONFIG_SCB0_MI3_SLOT17, | |
| 144 | CONFIG_SCB0_MI3_SLOT18, | |
| 145 | CONFIG_SCB0_MI3_SLOT19, | |
| 146 | CONFIG_SCB0_MI3_SLOT20, | |
| 147 | CONFIG_SCB0_MI3_SLOT21, | |
| 148 | CONFIG_SCB0_MI3_SLOT22, | |
| 149 | CONFIG_SCB0_MI3_SLOT23, | |
| 150 | CONFIG_SCB0_MI3_SLOT24, | |
| 151 | CONFIG_SCB0_MI3_SLOT25, | |
| 152 | CONFIG_SCB0_MI3_SLOT26, | |
| 153 | CONFIG_SCB0_MI3_SLOT27, | |
| 154 | CONFIG_SCB0_MI3_SLOT28, | |
| 155 | CONFIG_SCB0_MI3_SLOT29, | |
| 156 | CONFIG_SCB0_MI3_SLOT30, | |
| 157 | CONFIG_SCB0_MI3_SLOT31 | |
| 158 | }, | |
| 159 | }, | |
| 160 | #endif | |
| 161 | #ifdef CONFIG_SCB0_MI4 | |
| 162 | { REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, { | |
| 163 | CONFIG_SCB0_MI4_SLOT0, | |
| 164 | CONFIG_SCB0_MI4_SLOT1, | |
| 165 | CONFIG_SCB0_MI4_SLOT2, | |
| 166 | CONFIG_SCB0_MI4_SLOT3, | |
| 167 | CONFIG_SCB0_MI4_SLOT4, | |
| 168 | CONFIG_SCB0_MI4_SLOT5, | |
| 169 | CONFIG_SCB0_MI4_SLOT6, | |
| 170 | CONFIG_SCB0_MI4_SLOT7, | |
| 171 | CONFIG_SCB0_MI4_SLOT8, | |
| 172 | CONFIG_SCB0_MI4_SLOT9, | |
| 173 | CONFIG_SCB0_MI4_SLOT10, | |
| 174 | CONFIG_SCB0_MI4_SLOT11, | |
| 175 | CONFIG_SCB0_MI4_SLOT12, | |
| 176 | CONFIG_SCB0_MI4_SLOT13, | |
| 177 | CONFIG_SCB0_MI4_SLOT14, | |
| 178 | CONFIG_SCB0_MI4_SLOT15, | |
| 179 | CONFIG_SCB0_MI4_SLOT16, | |
| 180 | CONFIG_SCB0_MI4_SLOT17, | |
| 181 | CONFIG_SCB0_MI4_SLOT18, | |
| 182 | CONFIG_SCB0_MI4_SLOT19, | |
| 183 | CONFIG_SCB0_MI4_SLOT20, | |
| 184 | CONFIG_SCB0_MI4_SLOT21, | |
| 185 | CONFIG_SCB0_MI4_SLOT22, | |
| 186 | CONFIG_SCB0_MI4_SLOT23, | |
| 187 | CONFIG_SCB0_MI4_SLOT24, | |
| 188 | CONFIG_SCB0_MI4_SLOT25, | |
| 189 | CONFIG_SCB0_MI4_SLOT26, | |
| 190 | CONFIG_SCB0_MI4_SLOT27, | |
| 191 | CONFIG_SCB0_MI4_SLOT28, | |
| 192 | CONFIG_SCB0_MI4_SLOT29, | |
| 193 | CONFIG_SCB0_MI4_SLOT30, | |
| 194 | CONFIG_SCB0_MI4_SLOT31 | |
| 195 | }, | |
| 196 | }, | |
| 197 | #endif | |
| 198 | #ifdef CONFIG_SCB0_MI5 | |
| 199 | { REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, { | |
| 200 | CONFIG_SCB0_MI5_SLOT0, | |
| 201 | CONFIG_SCB0_MI5_SLOT1, | |
| 202 | CONFIG_SCB0_MI5_SLOT2, | |
| 203 | CONFIG_SCB0_MI5_SLOT3, | |
| 204 | CONFIG_SCB0_MI5_SLOT4, | |
| 205 | CONFIG_SCB0_MI5_SLOT5, | |
| 206 | CONFIG_SCB0_MI5_SLOT6, | |
| 207 | CONFIG_SCB0_MI5_SLOT7, | |
| 208 | CONFIG_SCB0_MI5_SLOT8, | |
| 209 | CONFIG_SCB0_MI5_SLOT9, | |
| 210 | CONFIG_SCB0_MI5_SLOT10, | |
| 211 | CONFIG_SCB0_MI5_SLOT11, | |
| 212 | CONFIG_SCB0_MI5_SLOT12, | |
| 213 | CONFIG_SCB0_MI5_SLOT13, | |
| 214 | CONFIG_SCB0_MI5_SLOT14, | |
| 215 | CONFIG_SCB0_MI5_SLOT15, | |
| 216 | }, | |
| 217 | }, | |
| 218 | #endif | |
| 219 | /* | |
| 220 | { REG_SCB1_ARBR0, REG_SCB1_ARBW0, scb1_mi0, 20 }, | |
| 221 | { REG_SCB2_ARBR0, REG_SCB2_ARBW0, scb2_mi0, 10 }, | |
| 222 | { REG_SCB3_ARBR0, REG_SCB3_ARBW0, scb3_mi0, 16 }, | |
| 223 | { REG_SCB4_ARBR0, REG_SCB4_ARBW0, scb4_mi0, 16 }, | |
| 224 | { REG_SCB5_ARBR0, REG_SCB5_ARBW0, scb5_mi0, 8 }, | |
| 225 | { REG_SCB6_ARBR0, REG_SCB6_ARBW0, scb6_mi0, 4 }, | |
| 226 | { REG_SCB7_ARBR0, REG_SCB7_ARBW0, scb7_mi0, 6 }, | |
| 227 | { REG_SCB8_ARBR0, REG_SCB8_ARBW0, scb8_mi0, 8 }, | |
| 228 | { REG_SCB9_ARBR0, REG_SCB9_ARBW0, scb9_mi0, 10 }, | |
| 229 | { REG_SCB10_ARBR0, REG_SCB10_ARBW0, scb20_mi0, 16 }, | |
| 230 | */ | |
| 231 | { 0, } | |
| 232 | }; |