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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / arch / blackfin / mach-common / ints-priority.c
CommitLineData
1394f032 1/*
cfefe3c6 2 * File: arch/blackfin/mach-common/ints-priority.c
1394f032
BW		 3 * Based on:
4 * Author:
5 *
6 * Created: ?
d2d50aa9 7 * Description: Set up the interrupt priorities
1394f032
BW		 8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
cfefe3c6 16 * Copyright 2004-2008 Analog Devices Inc.
1394f032
BW		 17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36#include <linux/module.h>
37#include <linux/kernel_stat.h>
38#include <linux/seq_file.h>
39#include <linux/irq.h>
40#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
48#ifdef BF537_FAMILY
49# define BF537_GENERIC_ERROR_INT_DEMUX
50#else
51# undef BF537_GENERIC_ERROR_INT_DEMUX
52#endif
53
54/*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
a99bbccd
MF		 61/* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67unsigned long irq_flags = 0x1f;
1394f032
BW		 68
69/* The number of spurious interrupts */
70atomic_t num_spurious;
71
cfefe3c6
MH		 72#ifdef CONFIG_PM
73unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74#endif
75
1394f032 76struct ivgx {
464abc5d 77 /* irq number for request_irq, available in mach-bf5xx/irq.h */
24a07a12 78 unsigned int irqno;
1394f032 79 /* corresponding bit in the SIC_ISR register */
24a07a12 80 unsigned int isrflag;
1394f032
BW		 81} ivg_table[NR_PERI_INTS];
82
83struct ivg_slice {
84 /* position of first irq in ivg_table for given ivg */
85 struct ivgx *ifirst;
86 struct ivgx *istop;
87} ivg7_13[IVG13 - IVG7 + 1];
88
1394f032
BW		 89
90/*
91 * Search SIC_IAR and fill tables with the irqvalues
92 * and their positions in the SIC_ISR register.
93 */
94static void __init search_IAR(void)
95{
96 unsigned ivg, irq_pos = 0;
97 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
98 int irqn;
99
34e0fc89 100 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
1394f032
BW		 101
102 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
103 int iar_shift = (irqn & 7) * 4;
2c4f829b 104 if (ivg == (0xf &
59003145 105#ifndef CONFIG_BF52x
34e0fc89 106 bfin_read32((unsigned long *)SIC_IAR0 +
1394f032 107 (irqn >> 3)) >> iar_shift)) {
59003145
MH		 108#else
109 bfin_read32((unsigned long *)SIC_IAR0 +
110 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
111#endif
1394f032 112 ivg_table[irq_pos].irqno = IVG7 + irqn;
24a07a12 113 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
1394f032
BW		 114 ivg7_13[ivg].istop++;
115 irq_pos++;
116 }
117 }
118 }
119}
120
121/*
464abc5d 122 * This is for core internal IRQs
1394f032
BW		 123 */
124
464abc5d 125static void bfin_ack_noop(unsigned int irq)
1394f032
BW		 126{
127 /* Dummy function. */
128}
129
130static void bfin_core_mask_irq(unsigned int irq)
131{
132 irq_flags &= ~(1 << irq);
133 if (!irqs_disabled())
134 local_irq_enable();
135}
136
137static void bfin_core_unmask_irq(unsigned int irq)
138{
139 irq_flags |= 1 << irq;
140 /*
141 * If interrupts are enabled, IMASK must contain the same value
142 * as irq_flags. Make sure that invariant holds. If interrupts
143 * are currently disabled we need not do anything; one of the
144 * callers will take care of setting IMASK to the proper value
145 * when reenabling interrupts.
146 * local_irq_enable just does "STI irq_flags", so it's exactly
147 * what we need.
148 */
149 if (!irqs_disabled())
150 local_irq_enable();
151 return;
152}
153
154static void bfin_internal_mask_irq(unsigned int irq)
155{
59003145 156#ifdef CONFIG_BF53x
1394f032 157 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
464abc5d 158 ~(1 << SIC_SYSIRQ(irq)));
24a07a12
RH		 159#else
160 unsigned mask_bank, mask_bit;
464abc5d
MH		 161 mask_bank = SIC_SYSIRQ(irq) / 32;
162 mask_bit = SIC_SYSIRQ(irq) % 32;
c04d66bb
BW		 163 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
164 ~(1 << mask_bit));
24a07a12 165#endif
1394f032
BW		 166 SSYNC();
167}
168
169static void bfin_internal_unmask_irq(unsigned int irq)
170{
59003145 171#ifdef CONFIG_BF53x
1394f032 172 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
464abc5d 173 (1 << SIC_SYSIRQ(irq)));
24a07a12
RH		 174#else
175 unsigned mask_bank, mask_bit;
464abc5d
MH		 176 mask_bank = SIC_SYSIRQ(irq) / 32;
177 mask_bit = SIC_SYSIRQ(irq) % 32;
c04d66bb
BW		 178 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
179 (1 << mask_bit));
24a07a12 180#endif
1394f032
BW		 181 SSYNC();
182}
183
cfefe3c6
MH		 184#ifdef CONFIG_PM
185int bfin_internal_set_wake(unsigned int irq, unsigned int state)
186{
187 unsigned bank, bit;
188 unsigned long flags;
464abc5d
MH		 189 bank = SIC_SYSIRQ(irq) / 32;
190 bit = SIC_SYSIRQ(irq) % 32;
cfefe3c6
MH		 191
192 local_irq_save(flags);
193
194 if (state)
195 bfin_sic_iwr[bank] |= (1 << bit);
196 else
197 bfin_sic_iwr[bank] &= ~(1 << bit);
198
199 local_irq_restore(flags);
200
201 return 0;
202}
203#endif
204
1394f032 205static struct irq_chip bfin_core_irqchip = {
464abc5d 206 .ack = bfin_ack_noop,
1394f032
BW		 207 .mask = bfin_core_mask_irq,
208 .unmask = bfin_core_unmask_irq,
209};
210
211static struct irq_chip bfin_internal_irqchip = {
464abc5d 212 .ack = bfin_ack_noop,
1394f032
BW		 213 .mask = bfin_internal_mask_irq,
214 .unmask = bfin_internal_unmask_irq,
ce3b7bb6
MH		 215 .mask_ack = bfin_internal_mask_irq,
216 .disable = bfin_internal_mask_irq,
217 .enable = bfin_internal_unmask_irq,
cfefe3c6
MH		 218#ifdef CONFIG_PM
219 .set_wake = bfin_internal_set_wake,
220#endif
1394f032
BW		 221};
222
223#ifdef BF537_GENERIC_ERROR_INT_DEMUX
224static int error_int_mask;
225
1394f032
BW		 226static void bfin_generic_error_mask_irq(unsigned int irq)
227{
228 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
229
464abc5d
MH		 230 if (!error_int_mask)
231 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
1394f032
BW		 232}
233
234static void bfin_generic_error_unmask_irq(unsigned int irq)
235{
464abc5d 236 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
1394f032
BW		 237 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
238}
239
240static struct irq_chip bfin_generic_error_irqchip = {
464abc5d
MH		 241 .ack = bfin_ack_noop,
242 .mask_ack = bfin_generic_error_mask_irq,
1394f032
BW		 243 .mask = bfin_generic_error_mask_irq,
244 .unmask = bfin_generic_error_unmask_irq,
245};
246
247static void bfin_demux_error_irq(unsigned int int_err_irq,
2c4f829b 248 struct irq_desc *inta_desc)
1394f032
BW		 249{
250 int irq = 0;
251
252 SSYNC();
253
254#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
255 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
256 irq = IRQ_MAC_ERROR;
257 else
258#endif
259 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
260 irq = IRQ_SPORT0_ERROR;
261 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
262 irq = IRQ_SPORT1_ERROR;
263 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
264 irq = IRQ_PPI_ERROR;
265 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
266 irq = IRQ_CAN_ERROR;
267 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
268 irq = IRQ_SPI_ERROR;
269 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
270 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
271 irq = IRQ_UART0_ERROR;
272 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
273 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
274 irq = IRQ_UART1_ERROR;
275
276 if (irq) {
277 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
278 struct irq_desc *desc = irq_desc + irq;
279 desc->handle_irq(irq, desc);
280 } else {
281
282 switch (irq) {
283 case IRQ_PPI_ERROR:
284 bfin_write_PPI_STATUS(PPI_ERR_MASK);
285 break;
286#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
287 case IRQ_MAC_ERROR:
288 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
289 break;
290#endif
291 case IRQ_SPORT0_ERROR:
292 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
293 break;
294
295 case IRQ_SPORT1_ERROR:
296 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
297 break;
298
299 case IRQ_CAN_ERROR:
300 bfin_write_CAN_GIS(CAN_ERR_MASK);
301 break;
302
303 case IRQ_SPI_ERROR:
304 bfin_write_SPI_STAT(SPI_ERR_MASK);
305 break;
306
307 default:
308 break;
309 }
310
311 pr_debug("IRQ %d:"
34e0fc89
MH		 312 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
313 irq);
1394f032
BW		 314 }
315 } else
316 printk(KERN_ERR
317 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
318 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
319 __FUNCTION__, __FILE__, __LINE__);
320
1394f032
BW		 321}
322#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
323
a055b2b4 324#if !defined(CONFIG_BF54x)
1394f032
BW		 325
326static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
327static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
328
6fce6a8d 329
1394f032
BW		 330static void bfin_gpio_ack_irq(unsigned int irq)
331{
332 u16 gpionr = irq - IRQ_PF0;
333
334 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
335 set_gpio_data(gpionr, 0);
336 SSYNC();
337 }
338}
339
340static void bfin_gpio_mask_ack_irq(unsigned int irq)
341{
342 u16 gpionr = irq - IRQ_PF0;
343
344 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
345 set_gpio_data(gpionr, 0);
346 SSYNC();
347 }
348
349 set_gpio_maska(gpionr, 0);
350 SSYNC();
351}
352
353static void bfin_gpio_mask_irq(unsigned int irq)
354{
355 set_gpio_maska(irq - IRQ_PF0, 0);
356 SSYNC();
357}
358
359static void bfin_gpio_unmask_irq(unsigned int irq)
360{
361 set_gpio_maska(irq - IRQ_PF0, 1);
362 SSYNC();
363}
364
365static unsigned int bfin_gpio_irq_startup(unsigned int irq)
366{
367 unsigned int ret;
368 u16 gpionr = irq - IRQ_PF0;
6fce6a8d 369 char buf[8];
1394f032
BW		 370
371 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 372 snprintf(buf, sizeof buf, "IRQ %d", irq);
373 ret = gpio_request(gpionr, buf);
1394f032
BW		 374 if (ret)
375 return ret;
376 }
377
378 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
379 bfin_gpio_unmask_irq(irq);
380
381 return ret;
382}
383
384static void bfin_gpio_irq_shutdown(unsigned int irq)
385{
386 bfin_gpio_mask_irq(irq);
387 gpio_free(irq - IRQ_PF0);
388 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
389}
390
391static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
392{
393
394 unsigned int ret;
6fce6a8d 395 char buf[8];
1394f032
BW		 396 u16 gpionr = irq - IRQ_PF0;
397
398 if (type == IRQ_TYPE_PROBE) {
399 /* only probe unenabled GPIO interrupt lines */
400 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
401 return 0;
402 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
403 }
404
405 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
34e0fc89 406 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1394f032 407 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 408 snprintf(buf, sizeof buf, "IRQ %d", irq);
409 ret = gpio_request(gpionr, buf);
1394f032
BW		 410 if (ret)
411 return ret;
412 }
413
414 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
415 } else {
416 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
417 return 0;
418 }
419
f1bceb47 420 set_gpio_inen(gpionr, 0);
1394f032 421 set_gpio_dir(gpionr, 0);
1394f032
BW		 422
423 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
424 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
425 set_gpio_both(gpionr, 1);
426 else
427 set_gpio_both(gpionr, 0);
428
429 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
430 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
431 else
432 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
433
f1bceb47
MH		 434 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
435 set_gpio_edge(gpionr, 1);
436 set_gpio_inen(gpionr, 1);
437 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
438 set_gpio_data(gpionr, 0);
439
440 } else {
441 set_gpio_edge(gpionr, 0);
442 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
443 set_gpio_inen(gpionr, 1);
444 }
445
1394f032
BW		 446 SSYNC();
447
448 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
449 set_irq_handler(irq, handle_edge_irq);
450 else
451 set_irq_handler(irq, handle_level_irq);
452
453 return 0;
454}
455
cfefe3c6
MH		 456#ifdef CONFIG_PM
457int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
458{
459 unsigned gpio = irq_to_gpio(irq);
460
461 if (state)
462 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
463 else
464 gpio_pm_wakeup_free(gpio);
465
466 return 0;
467}
468#endif
469
1394f032
BW		 470static struct irq_chip bfin_gpio_irqchip = {
471 .ack = bfin_gpio_ack_irq,
472 .mask = bfin_gpio_mask_irq,
473 .mask_ack = bfin_gpio_mask_ack_irq,
474 .unmask = bfin_gpio_unmask_irq,
475 .set_type = bfin_gpio_irq_type,
476 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 477 .shutdown = bfin_gpio_irq_shutdown,
478#ifdef CONFIG_PM
479 .set_wake = bfin_gpio_set_wake,
480#endif
1394f032
BW		 481};
482
2c4f829b
MH		 483static void bfin_demux_gpio_irq(unsigned int inta_irq,
484 struct irq_desc *desc)
1394f032 485{
2c4f829b
MH		 486 unsigned int i, gpio, mask, irq, search = 0;
487
488 switch (inta_irq) {
489#if defined(CONFIG_BF53x)
490 case IRQ_PROG_INTA:
491 irq = IRQ_PF0;
492 search = 1;
493 break;
494# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
495 case IRQ_MAC_RX:
496 irq = IRQ_PH0;
497 break;
498# endif
499#elif defined(CONFIG_BF52x)
500 case IRQ_PORTF_INTA:
501 irq = IRQ_PF0;
502 break;
503 case IRQ_PORTG_INTA:
504 irq = IRQ_PG0;
505 break;
506 case IRQ_PORTH_INTA:
507 irq = IRQ_PH0;
508 break;
509#elif defined(CONFIG_BF561)
510 case IRQ_PROG0_INTA:
511 irq = IRQ_PF0;
512 break;
513 case IRQ_PROG1_INTA:
514 irq = IRQ_PF16;
515 break;
516 case IRQ_PROG2_INTA:
517 irq = IRQ_PF32;
518 break;
519#endif
520 default:
521 BUG();
522 return;
523 }
524
525 if (search) {
cfefe3c6 526 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
2c4f829b
MH		 527 irq += i;
528
529 mask = get_gpiop_data(i) &
530 (gpio_enabled[gpio_bank(i)] &
531 get_gpiop_maska(i));
532
533 while (mask) {
534 if (mask & 1) {
535 desc = irq_desc + irq;
536 desc->handle_irq(irq, desc);
537 }
538 irq++;
539 mask >>= 1;
1394f032 540 }
1394f032 541 }
2c4f829b
MH		 542 } else {
543 gpio = irq_to_gpio(irq);
544 mask = get_gpiop_data(gpio) &
545 (gpio_enabled[gpio_bank(gpio)] &
546 get_gpiop_maska(gpio));
547
548 do {
549 if (mask & 1) {
550 desc = irq_desc + irq;
551 desc->handle_irq(irq, desc);
552 }
553 irq++;
554 mask >>= 1;
555 } while (mask);
1394f032 556 }
2c4f829b 557
1394f032
BW		 558}
559
a055b2b4 560#else /* CONFIG_BF54x */
34e0fc89
MH		 561
562#define NR_PINT_SYS_IRQS 4
563#define NR_PINT_BITS 32
564#define NR_PINTS 160
565#define IRQ_NOT_AVAIL 0xFF
566
567#define PINT_2_BANK(x) ((x) >> 5)
568#define PINT_2_BIT(x) ((x) & 0x1F)
569#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
570
571static unsigned char irq2pint_lut[NR_PINTS];
e3f23000 572static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
34e0fc89 573
8baf560b
MH		 574static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
575static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
576
577
34e0fc89
MH		 578struct pin_int_t {
579 unsigned int mask_set;
580 unsigned int mask_clear;
581 unsigned int request;
582 unsigned int assign;
583 unsigned int edge_set;
584 unsigned int edge_clear;
585 unsigned int invert_set;
586 unsigned int invert_clear;
587 unsigned int pinstate;
588 unsigned int latch;
589};
590
591static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
592 (struct pin_int_t *)PINT0_MASK_SET,
593 (struct pin_int_t *)PINT1_MASK_SET,
594 (struct pin_int_t *)PINT2_MASK_SET,
595 (struct pin_int_t *)PINT3_MASK_SET,
596};
597
464abc5d 598inline unsigned short get_irq_base(u8 bank, u8 bmap)
34e0fc89
MH		 599{
600
601 u16 irq_base;
602
603 if (bank < 2) { /*PA-PB */
604 irq_base = IRQ_PA0 + bmap * 16;
605 } else { /*PC-PJ */
606 irq_base = IRQ_PC0 + bmap * 16;
607 }
608
609 return irq_base;
610
611}
612
613 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
614void init_pint_lut(void)
615{
616 u16 bank, bit, irq_base, bit_pos;
617 u32 pint_assign;
618 u8 bmap;
619
620 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
621
622 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
623
624 pint_assign = pint[bank]->assign;
625
626 for (bit = 0; bit < NR_PINT_BITS; bit++) {
627
628 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
629
630 irq_base = get_irq_base(bank, bmap);
631
632 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
633 bit_pos = bit + bank * NR_PINT_BITS;
634
e3f23000 635 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
34e0fc89
MH		 636 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
637
638 }
639
640 }
641
642}
643
34e0fc89
MH		 644static void bfin_gpio_ack_irq(unsigned int irq)
645{
646 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
8baf560b
MH		 647 u32 pintbit = PINT_BIT(pint_val);
648 u8 bank = PINT_2_BANK(pint_val);
649
650 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
651 if (pint[bank]->invert_set & pintbit)
652 pint[bank]->invert_clear = pintbit;
653 else
654 pint[bank]->invert_set = pintbit;
655 }
656 pint[bank]->request = pintbit;
34e0fc89 657
34e0fc89
MH		 658 SSYNC();
659}
660
661static void bfin_gpio_mask_ack_irq(unsigned int irq)
662{
663 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 664 u32 pintbit = PINT_BIT(pint_val);
665 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 666
8baf560b
MH		 667 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
668 if (pint[bank]->invert_set & pintbit)
669 pint[bank]->invert_clear = pintbit;
670 else
671 pint[bank]->invert_set = pintbit;
672 }
673
e3f23000
MH		 674 pint[bank]->request = pintbit;
675 pint[bank]->mask_clear = pintbit;
34e0fc89
MH		 676 SSYNC();
677}
678
679static void bfin_gpio_mask_irq(unsigned int irq)
680{
681 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
682
683 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
684 SSYNC();
685}
686
687static void bfin_gpio_unmask_irq(unsigned int irq)
688{
689 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 690 u32 pintbit = PINT_BIT(pint_val);
691 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 692
e3f23000
MH		 693 pint[bank]->request = pintbit;
694 pint[bank]->mask_set = pintbit;
34e0fc89
MH		 695 SSYNC();
696}
697
698static unsigned int bfin_gpio_irq_startup(unsigned int irq)
699{
700 unsigned int ret;
6fce6a8d 701 char buf[8];
8baf560b 702 u16 gpionr = irq_to_gpio(irq);
34e0fc89
MH		 703 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
704
50e163ce
MH		 705 if (pint_val == IRQ_NOT_AVAIL) {
706 printk(KERN_ERR
707 "GPIO IRQ %d :Not in PINT Assign table "
708 "Reconfigure Interrupt to Port Assignemt\n", irq);
34e0fc89 709 return -ENODEV;
50e163ce 710 }
34e0fc89
MH		 711
712 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 713 snprintf(buf, sizeof buf, "IRQ %d", irq);
714 ret = gpio_request(gpionr, buf);
34e0fc89
MH		 715 if (ret)
716 return ret;
717 }
718
719 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
720 bfin_gpio_unmask_irq(irq);
721
722 return ret;
723}
724
725static void bfin_gpio_irq_shutdown(unsigned int irq)
726{
8baf560b
MH		 727 u16 gpionr = irq_to_gpio(irq);
728
34e0fc89 729 bfin_gpio_mask_irq(irq);
8baf560b
MH		 730 gpio_free(gpionr);
731 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
34e0fc89
MH		 732}
733
734static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
735{
736
737 unsigned int ret;
6fce6a8d 738 char buf[8];
8baf560b 739 u16 gpionr = irq_to_gpio(irq);
34e0fc89 740 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 741 u32 pintbit = PINT_BIT(pint_val);
742 u8 bank = PINT_2_BANK(pint_val);
34e0fc89
MH		 743
744 if (pint_val == IRQ_NOT_AVAIL)
745 return -ENODEV;
746
747 if (type == IRQ_TYPE_PROBE) {
748 /* only probe unenabled GPIO interrupt lines */
749 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
750 return 0;
751 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
752 }
753
754 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
755 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
756 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 757 snprintf(buf, sizeof buf, "IRQ %d", irq);
758 ret = gpio_request(gpionr, buf);
34e0fc89
MH		 759 if (ret)
760 return ret;
761 }
762
763 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
764 } else {
765 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
766 return 0;
767 }
768
769 gpio_direction_input(gpionr);
770
34e0fc89 771 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
e3f23000 772 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
34e0fc89 773 else
8baf560b 774 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
34e0fc89 775
8baf560b
MH		 776 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
777 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
34e0fc89 778
8baf560b 779 gpio_both_edge_triggered[bank] |= pintbit;
34e0fc89 780
8baf560b
MH		 781 if (gpio_get_value(gpionr))
782 pint[bank]->invert_set = pintbit;
783 else
784 pint[bank]->invert_clear = pintbit;
785 } else {
786 gpio_both_edge_triggered[bank] &= ~pintbit;
787 }
788
789 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
790 pint[bank]->edge_set = pintbit;
34e0fc89 791 set_irq_handler(irq, handle_edge_irq);
8baf560b
MH		 792 } else {
793 pint[bank]->edge_clear = pintbit;
34e0fc89 794 set_irq_handler(irq, handle_level_irq);
8baf560b
MH		 795 }
796
797 SSYNC();
34e0fc89
MH		 798
799 return 0;
800}
801
cfefe3c6
MH		 802#ifdef CONFIG_PM
803u32 pint_saved_masks[NR_PINT_SYS_IRQS];
804u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
805
806int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
807{
808 u32 pint_irq;
809 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
810 u32 bank = PINT_2_BANK(pint_val);
811 u32 pintbit = PINT_BIT(pint_val);
812
813 switch (bank) {
814 case 0:
815 pint_irq = IRQ_PINT0;
816 break;
817 case 2:
818 pint_irq = IRQ_PINT2;
819 break;
820 case 3:
821 pint_irq = IRQ_PINT3;
822 break;
823 case 1:
824 pint_irq = IRQ_PINT1;
825 break;
826 default:
827 return -EINVAL;
828 }
829
830 bfin_internal_set_wake(pint_irq, state);
831
832 if (state)
833 pint_wakeup_masks[bank] |= pintbit;
834 else
835 pint_wakeup_masks[bank] &= ~pintbit;
836
837 return 0;
838}
839
840u32 bfin_pm_setup(void)
841{
842 u32 val, i;
843
844 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
845 val = pint[i]->mask_clear;
846 pint_saved_masks[i] = val;
847 if (val ^ pint_wakeup_masks[i]) {
848 pint[i]->mask_clear = val;
849 pint[i]->mask_set = pint_wakeup_masks[i];
850 }
851 }
852
853 return 0;
854}
855
856void bfin_pm_restore(void)
857{
858 u32 i, val;
859
860 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
861 val = pint_saved_masks[i];
862 if (val ^ pint_wakeup_masks[i]) {
863 pint[i]->mask_clear = pint[i]->mask_clear;
864 pint[i]->mask_set = val;
865 }
866 }
867}
868#endif
869
34e0fc89
MH		 870static struct irq_chip bfin_gpio_irqchip = {
871 .ack = bfin_gpio_ack_irq,
872 .mask = bfin_gpio_mask_irq,
873 .mask_ack = bfin_gpio_mask_ack_irq,
874 .unmask = bfin_gpio_unmask_irq,
875 .set_type = bfin_gpio_irq_type,
876 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 877 .shutdown = bfin_gpio_irq_shutdown,
878#ifdef CONFIG_PM
879 .set_wake = bfin_gpio_set_wake,
880#endif
34e0fc89
MH		 881};
882
2c4f829b
MH		 883static void bfin_demux_gpio_irq(unsigned int inta_irq,
884 struct irq_desc *desc)
34e0fc89
MH		 885{
886 u8 bank, pint_val;
887 u32 request, irq;
888
2c4f829b 889 switch (inta_irq) {
34e0fc89
MH		 890 case IRQ_PINT0:
891 bank = 0;
892 break;
893 case IRQ_PINT2:
894 bank = 2;
895 break;
896 case IRQ_PINT3:
897 bank = 3;
898 break;
899 case IRQ_PINT1:
900 bank = 1;
901 break;
e3f23000
MH		 902 default:
903 return;
34e0fc89
MH		 904 }
905
906 pint_val = bank * NR_PINT_BITS;
907
908 request = pint[bank]->request;
909
910 while (request) {
911 if (request & 1) {
e3f23000
MH		 912 irq = pint2irq_lut[pint_val] + SYS_IRQS;
913 desc = irq_desc + irq;
34e0fc89
MH		 914 desc->handle_irq(irq, desc);
915 }
916 pint_val++;
917 request >>= 1;
918 }
919
920}
a055b2b4 921#endif
1394f032 922
8be80ed3
BS		 923void __init init_exception_vectors(void)
924{
925 SSYNC();
926
f0b5d12f
MF		 927 /* cannot program in software:
928 * evt0 - emulation (jtag)
929 * evt1 - reset
930 */
931 bfin_write_EVT2(evt_nmi);
8be80ed3
BS		 932 bfin_write_EVT3(trap);
933 bfin_write_EVT5(evt_ivhw);
934 bfin_write_EVT6(evt_timer);
935 bfin_write_EVT7(evt_evt7);
936 bfin_write_EVT8(evt_evt8);
937 bfin_write_EVT9(evt_evt9);
938 bfin_write_EVT10(evt_evt10);
939 bfin_write_EVT11(evt_evt11);
940 bfin_write_EVT12(evt_evt12);
941 bfin_write_EVT13(evt_evt13);
942 bfin_write_EVT14(evt14_softirq);
943 bfin_write_EVT15(evt_system_call);
944 CSYNC();
945}
946
1394f032
BW		 947/*
948 * This function should be called during kernel startup to initialize
949 * the BFin IRQ handling routines.
950 */
951int __init init_arch_irq(void)
952{
953 int irq;
954 unsigned long ilat = 0;
955 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
2c4f829b 956#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
24a07a12
RH		 957 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
958 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
a055b2b4 959# ifdef CONFIG_BF54x
59003145 960 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
a055b2b4 961# endif
24a07a12 962#else
1394f032 963 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
24a07a12 964#endif
1394f032
BW		 965
966 local_irq_disable();
967
2c4f829b
MH		 968 init_exception_buff();
969
a055b2b4
MF		 970#ifdef CONFIG_BF54x
971# ifdef CONFIG_PINTx_REASSIGN
34e0fc89
MH		 972 pint[0]->assign = CONFIG_PINT0_ASSIGN;
973 pint[1]->assign = CONFIG_PINT1_ASSIGN;
974 pint[2]->assign = CONFIG_PINT2_ASSIGN;
975 pint[3]->assign = CONFIG_PINT3_ASSIGN;
a055b2b4 976# endif
34e0fc89
MH		 977 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
978 init_pint_lut();
979#endif
980
981 for (irq = 0; irq <= SYS_IRQS; irq++) {
1394f032
BW		 982 if (irq <= IRQ_CORETMR)
983 set_irq_chip(irq, &bfin_core_irqchip);
984 else
985 set_irq_chip(irq, &bfin_internal_irqchip);
1394f032 986
464abc5d 987 switch (irq) {
59003145 988#if defined(CONFIG_BF53x)
464abc5d 989 case IRQ_PROG_INTA:
a055b2b4 990# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
464abc5d 991 case IRQ_MAC_RX:
a055b2b4 992# endif
59003145 993#elif defined(CONFIG_BF54x)
464abc5d
MH		 994 case IRQ_PINT0:
995 case IRQ_PINT1:
996 case IRQ_PINT2:
997 case IRQ_PINT3:
59003145 998#elif defined(CONFIG_BF52x)
464abc5d
MH		 999 case IRQ_PORTF_INTA:
1000 case IRQ_PORTG_INTA:
1001 case IRQ_PORTH_INTA:
2c4f829b 1002#elif defined(CONFIG_BF561)
464abc5d
MH		 1003 case IRQ_PROG0_INTA:
1004 case IRQ_PROG1_INTA:
1005 case IRQ_PROG2_INTA:
1394f032 1006#endif
464abc5d
MH		 1007 set_irq_chained_handler(irq,
1008 bfin_demux_gpio_irq);
1009 break;
1394f032 1010#ifdef BF537_GENERIC_ERROR_INT_DEMUX
464abc5d 1011 case IRQ_GENERIC_ERROR:
1394f032 1012 set_irq_handler(irq, bfin_demux_error_irq);
464abc5d
MH		 1013
1014 break;
1394f032 1015#endif
464abc5d
MH		 1016 default:
1017 set_irq_handler(irq, handle_simple_irq);
1018 break;
1019 }
1394f032 1020 }
464abc5d 1021
1394f032 1022#ifdef BF537_GENERIC_ERROR_INT_DEMUX
464abc5d
MH		 1023 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1024 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1025 handle_level_irq);
1394f032
BW		 1026#endif
1027
464abc5d
MH		 1028 /* if configured as edge, then will be changed to do_edge_IRQ */
1029 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1030 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1031 handle_level_irq);
2c4f829b 1032
a055b2b4 1033
1394f032
BW		 1034 bfin_write_IMASK(0);
1035 CSYNC();
1036 ilat = bfin_read_ILAT();
1037 CSYNC();
1038 bfin_write_ILAT(ilat);
1039 CSYNC();
1040
34e0fc89 1041 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1394f032
BW		 1042 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1043 * local_irq_enable()
1044 */
1045 program_IAR();
1046 /* Therefore it's better to setup IARs before interrupts enabled */
1047 search_IAR();
1048
1049 /* Enable interrupts IVG7-15 */
1050 irq_flags = irq_flags | IMASK_IVG15 |
1051 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
34e0fc89 1052 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1394f032 1053
fe9ec9b9
MH		 1054#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1055 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
1056 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
1057# ifdef CONFIG_BF54x
1058 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
1059# endif
1060#else
1061 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
1062#endif
1063
1394f032
BW		 1064 return 0;
1065}
1066
1067#ifdef CONFIG_DO_IRQ_L1
a055b2b4 1068__attribute__((l1_text))
1394f032 1069#endif
1394f032
BW		 1070void do_irq(int vec, struct pt_regs *fp)
1071{
1072 if (vec == EVT_IVTMR_P) {
1073 vec = IRQ_CORETMR;
1074 } else {
1075 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1076 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
2c4f829b 1077#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
24a07a12 1078 unsigned long sic_status[3];
1394f032 1079
4fb45241
MH		 1080 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1081 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
59003145 1082#ifdef CONFIG_BF54x
4fb45241 1083 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
59003145 1084#endif
1f83b8f1 1085 for (;; ivg++) {
24a07a12
RH		 1086 if (ivg >= ivg_stop) {
1087 atomic_inc(&num_spurious);
1088 return;
1089 }
34e0fc89 1090 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
24a07a12
RH		 1091 break;
1092 }
1093#else
1094 unsigned long sic_status;
464abc5d 1095
1394f032
BW		 1096 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1097
1098 for (;; ivg++) {
1099 if (ivg >= ivg_stop) {
1100 atomic_inc(&num_spurious);
1101 return;
1102 } else if (sic_status & ivg->isrflag)
1103 break;
1104 }
24a07a12 1105#endif
1394f032
BW		 1106 vec = ivg->irqno;
1107 }
1108 asm_do_IRQ(vec, fp);
1109
1110#ifdef CONFIG_KGDB
1111 kgdb_process_breakpoint();
1112#endif
1113}
Linux kernel - Deliverables
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