projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Blackfin arch: Add code to free gpio when shutdown irq
[deliverable/linux.git] / arch / blackfin / mach-common / ints-priority.c
CommitLineData
1394f032 1/*
cfefe3c6 2 * File: arch/blackfin/mach-common/ints-priority.c
1394f032 3 *
d2d50aa9 4 * Description: Set up the interrupt priorities
1394f032
BW		 5 *
6 * Modified:
7 * 1996 Roman Zippel
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
10 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
11 * 2003 Metrowerks/Motorola
12 * 2003 Bas Vermeulen <bas@buyways.nl>
cfefe3c6 13 * Copyright 2004-2008 Analog Devices Inc.
1394f032
BW		 14 *
15 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, see the file COPYING, or write
29 * to the Free Software Foundation, Inc.,
30 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 */
32
33#include <linux/module.h>
34#include <linux/kernel_stat.h>
35#include <linux/seq_file.h>
36#include <linux/irq.h>
37#ifdef CONFIG_KGDB
38#include <linux/kgdb.h>
39#endif
40#include <asm/traps.h>
41#include <asm/blackfin.h>
42#include <asm/gpio.h>
43#include <asm/irq_handler.h>
44
7beb7439
MF		 45#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
46
1394f032
BW		 47#ifdef BF537_FAMILY
48# define BF537_GENERIC_ERROR_INT_DEMUX
49#else
50# undef BF537_GENERIC_ERROR_INT_DEMUX
51#endif
52
53/*
54 * NOTES:
55 * - we have separated the physical Hardware interrupt from the
56 * levels that the LINUX kernel sees (see the description in irq.h)
57 * -
58 */
59
6b3087c6 60#ifndef CONFIG_SMP
a99bbccd
MF		 61/* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
40059784
MF		 67unsigned long bfin_irq_flags = 0x1f;
68EXPORT_SYMBOL(bfin_irq_flags);
6b3087c6 69#endif
1394f032
BW		 70
71/* The number of spurious interrupts */
72atomic_t num_spurious;
73
cfefe3c6
MH		 74#ifdef CONFIG_PM
75unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
4a88d0ce 76unsigned vr_wakeup;
cfefe3c6
MH		 77#endif
78
1394f032 79struct ivgx {
464abc5d 80 /* irq number for request_irq, available in mach-bf5xx/irq.h */
24a07a12 81 unsigned int irqno;
1394f032 82 /* corresponding bit in the SIC_ISR register */
24a07a12 83 unsigned int isrflag;
1394f032
BW		 84} ivg_table[NR_PERI_INTS];
85
86struct ivg_slice {
87 /* position of first irq in ivg_table for given ivg */
88 struct ivgx *ifirst;
89 struct ivgx *istop;
90} ivg7_13[IVG13 - IVG7 + 1];
91
1394f032
BW		 92
93/*
94 * Search SIC_IAR and fill tables with the irqvalues
95 * and their positions in the SIC_ISR register.
96 */
97static void __init search_IAR(void)
98{
99 unsigned ivg, irq_pos = 0;
100 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
101 int irqn;
102
34e0fc89 103 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
1394f032
BW		 104
105 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
106 int iar_shift = (irqn & 7) * 4;
2c4f829b 107 if (ivg == (0xf &
2f6f4bcd
BW		 108#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
109 || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
34e0fc89 110 bfin_read32((unsigned long *)SIC_IAR0 +
dc26aec2
MH		 111 ((irqn % 32) >> 3) + ((irqn / 32) *
112 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
59003145
MH		 113#else
114 bfin_read32((unsigned long *)SIC_IAR0 +
dc26aec2 115 (irqn >> 3)) >> iar_shift)) {
59003145 116#endif
1394f032 117 ivg_table[irq_pos].irqno = IVG7 + irqn;
24a07a12 118 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
1394f032
BW		 119 ivg7_13[ivg].istop++;
120 irq_pos++;
121 }
122 }
123 }
124}
125
126/*
464abc5d 127 * This is for core internal IRQs
1394f032
BW		 128 */
129
464abc5d 130static void bfin_ack_noop(unsigned int irq)
1394f032
BW		 131{
132 /* Dummy function. */
133}
134
135static void bfin_core_mask_irq(unsigned int irq)
136{
40059784 137 bfin_irq_flags &= ~(1 << irq);
1394f032
BW		 138 if (!irqs_disabled())
139 local_irq_enable();
140}
141
142static void bfin_core_unmask_irq(unsigned int irq)
143{
40059784 144 bfin_irq_flags |= 1 << irq;
1394f032
BW		 145 /*
146 * If interrupts are enabled, IMASK must contain the same value
40059784 147 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
1394f032
BW		 148 * are currently disabled we need not do anything; one of the
149 * callers will take care of setting IMASK to the proper value
150 * when reenabling interrupts.
40059784 151 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
1394f032
BW		 152 * what we need.
153 */
154 if (!irqs_disabled())
155 local_irq_enable();
156 return;
157}
158
159static void bfin_internal_mask_irq(unsigned int irq)
160{
59003145 161#ifdef CONFIG_BF53x
1394f032 162 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
464abc5d 163 ~(1 << SIC_SYSIRQ(irq)));
24a07a12
RH		 164#else
165 unsigned mask_bank, mask_bit;
464abc5d
MH		 166 mask_bank = SIC_SYSIRQ(irq) / 32;
167 mask_bit = SIC_SYSIRQ(irq) % 32;
c04d66bb
BW		 168 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
169 ~(1 << mask_bit));
6b3087c6
GY		 170#ifdef CONFIG_SMP
171 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
172 ~(1 << mask_bit));
173#endif
24a07a12 174#endif
1394f032
BW		 175}
176
177static void bfin_internal_unmask_irq(unsigned int irq)
178{
59003145 179#ifdef CONFIG_BF53x
1394f032 180 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
464abc5d 181 (1 << SIC_SYSIRQ(irq)));
24a07a12
RH		 182#else
183 unsigned mask_bank, mask_bit;
464abc5d
MH		 184 mask_bank = SIC_SYSIRQ(irq) / 32;
185 mask_bit = SIC_SYSIRQ(irq) % 32;
c04d66bb
BW		 186 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
187 (1 << mask_bit));
6b3087c6
GY		 188#ifdef CONFIG_SMP
189 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
190 (1 << mask_bit));
191#endif
24a07a12 192#endif
1394f032
BW		 193}
194
cfefe3c6
MH		 195#ifdef CONFIG_PM
196int bfin_internal_set_wake(unsigned int irq, unsigned int state)
197{
8d022374 198 u32 bank, bit, wakeup = 0;
cfefe3c6 199 unsigned long flags;
464abc5d
MH		 200 bank = SIC_SYSIRQ(irq) / 32;
201 bit = SIC_SYSIRQ(irq) % 32;
cfefe3c6 202
4a88d0ce
MH		 203 switch (irq) {
204#ifdef IRQ_RTC
205 case IRQ_RTC:
206 wakeup |= WAKE;
207 break;
208#endif
209#ifdef IRQ_CAN0_RX
210 case IRQ_CAN0_RX:
211 wakeup |= CANWE;
212 break;
213#endif
214#ifdef IRQ_CAN1_RX
215 case IRQ_CAN1_RX:
216 wakeup |= CANWE;
217 break;
218#endif
219#ifdef IRQ_USB_INT0
220 case IRQ_USB_INT0:
221 wakeup |= USBWE;
222 break;
223#endif
224#ifdef IRQ_KEY
225 case IRQ_KEY:
226 wakeup |= KPADWE;
227 break;
228#endif
d310fb4b 229#ifdef CONFIG_BF54x
4a88d0ce
MH		 230 case IRQ_CNT:
231 wakeup |= ROTWE;
232 break;
233#endif
234 default:
235 break;
236 }
237
cfefe3c6
MH		 238 local_irq_save(flags);
239
4a88d0ce 240 if (state) {
cfefe3c6 241 bfin_sic_iwr[bank] |= (1 << bit);
4a88d0ce
MH		 242 vr_wakeup |= wakeup;
243
244 } else {
cfefe3c6 245 bfin_sic_iwr[bank] &= ~(1 << bit);
4a88d0ce
MH		 246 vr_wakeup &= ~wakeup;
247 }
cfefe3c6
MH		 248
249 local_irq_restore(flags);
250
251 return 0;
252}
253#endif
254
1394f032 255static struct irq_chip bfin_core_irqchip = {
763e63c6 256 .name = "CORE",
464abc5d 257 .ack = bfin_ack_noop,
1394f032
BW		 258 .mask = bfin_core_mask_irq,
259 .unmask = bfin_core_unmask_irq,
260};
261
262static struct irq_chip bfin_internal_irqchip = {
763e63c6 263 .name = "INTN",
464abc5d 264 .ack = bfin_ack_noop,
1394f032
BW		 265 .mask = bfin_internal_mask_irq,
266 .unmask = bfin_internal_unmask_irq,
ce3b7bb6
MH		 267 .mask_ack = bfin_internal_mask_irq,
268 .disable = bfin_internal_mask_irq,
269 .enable = bfin_internal_unmask_irq,
cfefe3c6
MH		 270#ifdef CONFIG_PM
271 .set_wake = bfin_internal_set_wake,
272#endif
1394f032
BW		 273};
274
275#ifdef BF537_GENERIC_ERROR_INT_DEMUX
276static int error_int_mask;
277
1394f032
BW		 278static void bfin_generic_error_mask_irq(unsigned int irq)
279{
280 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
281
464abc5d
MH		 282 if (!error_int_mask)
283 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
1394f032
BW		 284}
285
286static void bfin_generic_error_unmask_irq(unsigned int irq)
287{
464abc5d 288 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
1394f032
BW		 289 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
290}
291
292static struct irq_chip bfin_generic_error_irqchip = {
763e63c6 293 .name = "ERROR",
464abc5d
MH		 294 .ack = bfin_ack_noop,
295 .mask_ack = bfin_generic_error_mask_irq,
1394f032
BW		 296 .mask = bfin_generic_error_mask_irq,
297 .unmask = bfin_generic_error_unmask_irq,
298};
299
300static void bfin_demux_error_irq(unsigned int int_err_irq,
2c4f829b 301 struct irq_desc *inta_desc)
1394f032
BW		 302{
303 int irq = 0;
304
1394f032
BW		 305#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
306 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
307 irq = IRQ_MAC_ERROR;
308 else
309#endif
310 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
311 irq = IRQ_SPORT0_ERROR;
312 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
313 irq = IRQ_SPORT1_ERROR;
314 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
315 irq = IRQ_PPI_ERROR;
316 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
317 irq = IRQ_CAN_ERROR;
318 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
319 irq = IRQ_SPI_ERROR;
320 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
321 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
322 irq = IRQ_UART0_ERROR;
323 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
324 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
325 irq = IRQ_UART1_ERROR;
326
327 if (irq) {
328 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
329 struct irq_desc *desc = irq_desc + irq;
330 desc->handle_irq(irq, desc);
331 } else {
332
333 switch (irq) {
334 case IRQ_PPI_ERROR:
335 bfin_write_PPI_STATUS(PPI_ERR_MASK);
336 break;
337#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
338 case IRQ_MAC_ERROR:
339 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
340 break;
341#endif
342 case IRQ_SPORT0_ERROR:
343 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
344 break;
345
346 case IRQ_SPORT1_ERROR:
347 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
348 break;
349
350 case IRQ_CAN_ERROR:
351 bfin_write_CAN_GIS(CAN_ERR_MASK);
352 break;
353
354 case IRQ_SPI_ERROR:
355 bfin_write_SPI_STAT(SPI_ERR_MASK);
356 break;
357
358 default:
359 break;
360 }
361
362 pr_debug("IRQ %d:"
34e0fc89
MH		 363 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
364 irq);
1394f032
BW		 365 }
366 } else
367 printk(KERN_ERR
368 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
369 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
b85d858b 370 __func__, __FILE__, __LINE__);
1394f032 371
1394f032
BW		 372}
373#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
374
bfd15117
GY		 375static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
376{
377 struct irq_desc *desc = irq_desc + irq;
378 /* May not call generic set_irq_handler() due to spinlock
379 recursion. */
380 desc->handle_irq = handle;
381}
382
8d022374 383static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
affee2b2 384extern void bfin_gpio_irq_prepare(unsigned gpio);
6fce6a8d 385
8d022374
MH		 386#if !defined(CONFIG_BF54x)
387
1394f032
BW		 388static void bfin_gpio_ack_irq(unsigned int irq)
389{
8d022374
MH		 390 /* AFAIK ack_irq in case mask_ack is provided
391 * get's only called for edge sense irqs
392 */
393 set_gpio_data(irq_to_gpio(irq), 0);
1394f032
BW		 394}
395
396static void bfin_gpio_mask_ack_irq(unsigned int irq)
397{
8d022374
MH		 398 struct irq_desc *desc = irq_desc + irq;
399 u32 gpionr = irq_to_gpio(irq);
1394f032 400
8d022374 401 if (desc->handle_irq == handle_edge_irq)
1394f032 402 set_gpio_data(gpionr, 0);
1394f032
BW		 403
404 set_gpio_maska(gpionr, 0);
1394f032
BW		 405}
406
407static void bfin_gpio_mask_irq(unsigned int irq)
408{
8d022374 409 set_gpio_maska(irq_to_gpio(irq), 0);
1394f032
BW		 410}
411
412static void bfin_gpio_unmask_irq(unsigned int irq)
413{
8d022374 414 set_gpio_maska(irq_to_gpio(irq), 1);
1394f032
BW		 415}
416
417static unsigned int bfin_gpio_irq_startup(unsigned int irq)
418{
8d022374 419 u32 gpionr = irq_to_gpio(irq);
1394f032 420
8d022374 421 if (__test_and_set_bit(gpionr, gpio_enabled))
affee2b2 422 bfin_gpio_irq_prepare(gpionr);
1394f032 423
1394f032
BW		 424 bfin_gpio_unmask_irq(irq);
425
affee2b2 426 return 0;
1394f032
BW		 427}
428
429static void bfin_gpio_irq_shutdown(unsigned int irq)
430{
30af6d49
GY		 431 u32 gpionr = irq_to_gpio(irq);
432
1394f032 433 bfin_gpio_mask_irq(irq);
30af6d49
GY		 434 __clear_bit(gpionr, gpio_enabled);
435 bfin_gpio_free(gpionr);
1394f032
BW		 436}
437
438static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
439{
8d022374 440 u32 gpionr = irq_to_gpio(irq);
1394f032
BW		 441
442 if (type == IRQ_TYPE_PROBE) {
443 /* only probe unenabled GPIO interrupt lines */
8d022374 444 if (__test_bit(gpionr, gpio_enabled))
1394f032
BW		 445 return 0;
446 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
447 }
448
449 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
34e0fc89 450 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
8d022374
MH		 451
452 if (__test_and_set_bit(gpionr, gpio_enabled))
affee2b2 453 bfin_gpio_irq_prepare(gpionr);
1394f032 454
1394f032 455 } else {
8d022374 456 __clear_bit(gpionr, gpio_enabled);
1394f032
BW		 457 return 0;
458 }
459
f1bceb47 460 set_gpio_inen(gpionr, 0);
1394f032 461 set_gpio_dir(gpionr, 0);
1394f032
BW		 462
463 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
464 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
465 set_gpio_both(gpionr, 1);
466 else
467 set_gpio_both(gpionr, 0);
468
469 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
470 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
471 else
472 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
473
f1bceb47
MH		 474 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
475 set_gpio_edge(gpionr, 1);
476 set_gpio_inen(gpionr, 1);
f1bceb47
MH		 477 set_gpio_data(gpionr, 0);
478
479 } else {
480 set_gpio_edge(gpionr, 0);
f1bceb47
MH		 481 set_gpio_inen(gpionr, 1);
482 }
483
1394f032 484 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
bfd15117 485 bfin_set_irq_handler(irq, handle_edge_irq);
1394f032 486 else
bfd15117 487 bfin_set_irq_handler(irq, handle_level_irq);
1394f032
BW		 488
489 return 0;
490}
491
cfefe3c6
MH		 492#ifdef CONFIG_PM
493int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
494{
495 unsigned gpio = irq_to_gpio(irq);
496
497 if (state)
498 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
499 else
500 gpio_pm_wakeup_free(gpio);
501
502 return 0;
503}
504#endif
505
2c4f829b
MH		 506static void bfin_demux_gpio_irq(unsigned int inta_irq,
507 struct irq_desc *desc)
1394f032 508{
2c4f829b
MH		 509 unsigned int i, gpio, mask, irq, search = 0;
510
511 switch (inta_irq) {
512#if defined(CONFIG_BF53x)
513 case IRQ_PROG_INTA:
514 irq = IRQ_PF0;
515 search = 1;
516 break;
517# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
518 case IRQ_MAC_RX:
519 irq = IRQ_PH0;
520 break;
521# endif
dc26aec2
MH		 522#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
523 case IRQ_PORTF_INTA:
524 irq = IRQ_PF0;
525 break;
2f6f4bcd 526#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
2c4f829b
MH		 527 case IRQ_PORTF_INTA:
528 irq = IRQ_PF0;
529 break;
530 case IRQ_PORTG_INTA:
531 irq = IRQ_PG0;
532 break;
533 case IRQ_PORTH_INTA:
534 irq = IRQ_PH0;
535 break;
536#elif defined(CONFIG_BF561)
537 case IRQ_PROG0_INTA:
538 irq = IRQ_PF0;
539 break;
540 case IRQ_PROG1_INTA:
541 irq = IRQ_PF16;
542 break;
543 case IRQ_PROG2_INTA:
544 irq = IRQ_PF32;
545 break;
546#endif
547 default:
548 BUG();
549 return;
550 }
551
552 if (search) {
cfefe3c6 553 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
2c4f829b
MH		 554 irq += i;
555
8d022374 556 mask = get_gpiop_data(i) & get_gpiop_maska(i);
2c4f829b
MH		 557
558 while (mask) {
559 if (mask & 1) {
560 desc = irq_desc + irq;
561 desc->handle_irq(irq, desc);
562 }
563 irq++;
564 mask >>= 1;
1394f032 565 }
1394f032 566 }
2c4f829b
MH		 567 } else {
568 gpio = irq_to_gpio(irq);
8d022374 569 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
2c4f829b
MH		 570
571 do {
572 if (mask & 1) {
573 desc = irq_desc + irq;
574 desc->handle_irq(irq, desc);
575 }
576 irq++;
577 mask >>= 1;
578 } while (mask);
1394f032 579 }
2c4f829b 580
1394f032
BW		 581}
582
a055b2b4 583#else /* CONFIG_BF54x */
34e0fc89
MH		 584
585#define NR_PINT_SYS_IRQS 4
586#define NR_PINT_BITS 32
587#define NR_PINTS 160
588#define IRQ_NOT_AVAIL 0xFF
589
590#define PINT_2_BANK(x) ((x) >> 5)
591#define PINT_2_BIT(x) ((x) & 0x1F)
592#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
593
594static unsigned char irq2pint_lut[NR_PINTS];
e3f23000 595static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
34e0fc89
MH		 596
597struct pin_int_t {
598 unsigned int mask_set;
599 unsigned int mask_clear;
600 unsigned int request;
601 unsigned int assign;
602 unsigned int edge_set;
603 unsigned int edge_clear;
604 unsigned int invert_set;
605 unsigned int invert_clear;
606 unsigned int pinstate;
607 unsigned int latch;
608};
609
610static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
611 (struct pin_int_t *)PINT0_MASK_SET,
612 (struct pin_int_t *)PINT1_MASK_SET,
613 (struct pin_int_t *)PINT2_MASK_SET,
614 (struct pin_int_t *)PINT3_MASK_SET,
615};
616
8d022374 617inline unsigned int get_irq_base(u32 bank, u8 bmap)
34e0fc89 618{
8d022374 619 unsigned int irq_base;
34e0fc89
MH		 620
621 if (bank < 2) { /*PA-PB */
622 irq_base = IRQ_PA0 + bmap * 16;
623 } else { /*PC-PJ */
624 irq_base = IRQ_PC0 + bmap * 16;
625 }
626
627 return irq_base;
34e0fc89
MH		 628}
629
630 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
631void init_pint_lut(void)
632{
633 u16 bank, bit, irq_base, bit_pos;
634 u32 pint_assign;
635 u8 bmap;
636
637 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
638
639 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
640
641 pint_assign = pint[bank]->assign;
642
643 for (bit = 0; bit < NR_PINT_BITS; bit++) {
644
645 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
646
647 irq_base = get_irq_base(bank, bmap);
648
649 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
650 bit_pos = bit + bank * NR_PINT_BITS;
651
e3f23000 652 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
34e0fc89 653 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
34e0fc89 654 }
34e0fc89 655 }
34e0fc89
MH		 656}
657
34e0fc89
MH		 658static void bfin_gpio_ack_irq(unsigned int irq)
659{
8d022374
MH		 660 struct irq_desc *desc = irq_desc + irq;
661 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
8baf560b 662 u32 pintbit = PINT_BIT(pint_val);
8d022374 663 u32 bank = PINT_2_BANK(pint_val);
8baf560b 664
8d022374 665 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
8baf560b
MH		 666 if (pint[bank]->invert_set & pintbit)
667 pint[bank]->invert_clear = pintbit;
668 else
669 pint[bank]->invert_set = pintbit;
670 }
671 pint[bank]->request = pintbit;
34e0fc89 672
34e0fc89
MH		 673}
674
675static void bfin_gpio_mask_ack_irq(unsigned int irq)
676{
8d022374
MH		 677 struct irq_desc *desc = irq_desc + irq;
678 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000 679 u32 pintbit = PINT_BIT(pint_val);
8d022374 680 u32 bank = PINT_2_BANK(pint_val);
34e0fc89 681
8d022374 682 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
8baf560b
MH		 683 if (pint[bank]->invert_set & pintbit)
684 pint[bank]->invert_clear = pintbit;
685 else
686 pint[bank]->invert_set = pintbit;
687 }
688
e3f23000
MH		 689 pint[bank]->request = pintbit;
690 pint[bank]->mask_clear = pintbit;
34e0fc89
MH		 691}
692
693static void bfin_gpio_mask_irq(unsigned int irq)
694{
8d022374 695 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
34e0fc89
MH		 696
697 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
34e0fc89
MH		 698}
699
700static void bfin_gpio_unmask_irq(unsigned int irq)
701{
8d022374 702 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000 703 u32 pintbit = PINT_BIT(pint_val);
8d022374 704 u32 bank = PINT_2_BANK(pint_val);
34e0fc89 705
e3f23000
MH		 706 pint[bank]->request = pintbit;
707 pint[bank]->mask_set = pintbit;
34e0fc89
MH		 708}
709
710static unsigned int bfin_gpio_irq_startup(unsigned int irq)
711{
8d022374
MH		 712 u32 gpionr = irq_to_gpio(irq);
713 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
34e0fc89 714
50e163ce
MH		 715 if (pint_val == IRQ_NOT_AVAIL) {
716 printk(KERN_ERR
717 "GPIO IRQ %d :Not in PINT Assign table "
718 "Reconfigure Interrupt to Port Assignemt\n", irq);
34e0fc89 719 return -ENODEV;
50e163ce 720 }
34e0fc89 721
8d022374 722 if (__test_and_set_bit(gpionr, gpio_enabled))
affee2b2 723 bfin_gpio_irq_prepare(gpionr);
34e0fc89 724
34e0fc89
MH		 725 bfin_gpio_unmask_irq(irq);
726
affee2b2 727 return 0;
34e0fc89
MH		 728}
729
730static void bfin_gpio_irq_shutdown(unsigned int irq)
731{
8d022374 732 u32 gpionr = irq_to_gpio(irq);
8baf560b 733
34e0fc89 734 bfin_gpio_mask_irq(irq);
8d022374 735 __clear_bit(gpionr, gpio_enabled);
30af6d49 736 bfin_gpio_free(gpionr);
34e0fc89
MH		 737}
738
739static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
740{
741
8d022374
MH		 742 u32 gpionr = irq_to_gpio(irq);
743 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000 744 u32 pintbit = PINT_BIT(pint_val);
8d022374 745 u32 bank = PINT_2_BANK(pint_val);
34e0fc89
MH		 746
747 if (pint_val == IRQ_NOT_AVAIL)
748 return -ENODEV;
749
750 if (type == IRQ_TYPE_PROBE) {
751 /* only probe unenabled GPIO interrupt lines */
8d022374 752 if (__test_bit(gpionr, gpio_enabled))
34e0fc89
MH		 753 return 0;
754 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
755 }
756
757 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
758 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
8d022374 759 if (__test_and_set_bit(gpionr, gpio_enabled))
affee2b2 760 bfin_gpio_irq_prepare(gpionr);
34e0fc89 761
34e0fc89 762 } else {
8d022374 763 __clear_bit(gpionr, gpio_enabled);
34e0fc89
MH		 764 return 0;
765 }
766
34e0fc89 767 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
e3f23000 768 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
34e0fc89 769 else
8baf560b 770 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
34e0fc89 771
8baf560b
MH		 772 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
773 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
8baf560b
MH		 774 if (gpio_get_value(gpionr))
775 pint[bank]->invert_set = pintbit;
776 else
777 pint[bank]->invert_clear = pintbit;
8baf560b
MH		 778 }
779
780 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
781 pint[bank]->edge_set = pintbit;
bfd15117 782 bfin_set_irq_handler(irq, handle_edge_irq);
8baf560b
MH		 783 } else {
784 pint[bank]->edge_clear = pintbit;
bfd15117 785 bfin_set_irq_handler(irq, handle_level_irq);
8baf560b
MH		 786 }
787
34e0fc89
MH		 788 return 0;
789}
790
cfefe3c6
MH		 791#ifdef CONFIG_PM
792u32 pint_saved_masks[NR_PINT_SYS_IRQS];
793u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
794
795int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
796{
797 u32 pint_irq;
8d022374 798 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
cfefe3c6
MH		 799 u32 bank = PINT_2_BANK(pint_val);
800 u32 pintbit = PINT_BIT(pint_val);
801
802 switch (bank) {
803 case 0:
804 pint_irq = IRQ_PINT0;
805 break;
806 case 2:
807 pint_irq = IRQ_PINT2;
808 break;
809 case 3:
810 pint_irq = IRQ_PINT3;
811 break;
812 case 1:
813 pint_irq = IRQ_PINT1;
814 break;
815 default:
816 return -EINVAL;
817 }
818
819 bfin_internal_set_wake(pint_irq, state);
820
821 if (state)
822 pint_wakeup_masks[bank] |= pintbit;
823 else
824 pint_wakeup_masks[bank] &= ~pintbit;
825
826 return 0;
827}
828
829u32 bfin_pm_setup(void)
830{
831 u32 val, i;
832
833 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
834 val = pint[i]->mask_clear;
835 pint_saved_masks[i] = val;
836 if (val ^ pint_wakeup_masks[i]) {
837 pint[i]->mask_clear = val;
838 pint[i]->mask_set = pint_wakeup_masks[i];
839 }
840 }
841
842 return 0;
843}
844
845void bfin_pm_restore(void)
846{
847 u32 i, val;
848
849 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
850 val = pint_saved_masks[i];
851 if (val ^ pint_wakeup_masks[i]) {
852 pint[i]->mask_clear = pint[i]->mask_clear;
853 pint[i]->mask_set = val;
854 }
855 }
856}
857#endif
858
2c4f829b
MH		 859static void bfin_demux_gpio_irq(unsigned int inta_irq,
860 struct irq_desc *desc)
34e0fc89 861{
8d022374 862 u32 bank, pint_val;
34e0fc89
MH		 863 u32 request, irq;
864
2c4f829b 865 switch (inta_irq) {
34e0fc89
MH		 866 case IRQ_PINT0:
867 bank = 0;
868 break;
869 case IRQ_PINT2:
870 bank = 2;
871 break;
872 case IRQ_PINT3:
873 bank = 3;
874 break;
875 case IRQ_PINT1:
876 bank = 1;
877 break;
e3f23000
MH		 878 default:
879 return;
34e0fc89
MH		 880 }
881
882 pint_val = bank * NR_PINT_BITS;
883
884 request = pint[bank]->request;
885
886 while (request) {
887 if (request & 1) {
e3f23000
MH		 888 irq = pint2irq_lut[pint_val] + SYS_IRQS;
889 desc = irq_desc + irq;
34e0fc89
MH		 890 desc->handle_irq(irq, desc);
891 }
892 pint_val++;
893 request >>= 1;
894 }
895
896}
a055b2b4 897#endif
1394f032 898
8d022374
MH		 899static struct irq_chip bfin_gpio_irqchip = {
900 .name = "GPIO",
901 .ack = bfin_gpio_ack_irq,
902 .mask = bfin_gpio_mask_irq,
903 .mask_ack = bfin_gpio_mask_ack_irq,
904 .unmask = bfin_gpio_unmask_irq,
905 .disable = bfin_gpio_mask_irq,
906 .enable = bfin_gpio_unmask_irq,
907 .set_type = bfin_gpio_irq_type,
908 .startup = bfin_gpio_irq_startup,
909 .shutdown = bfin_gpio_irq_shutdown,
910#ifdef CONFIG_PM
911 .set_wake = bfin_gpio_set_wake,
912#endif
913};
914
6b3087c6 915void __cpuinit init_exception_vectors(void)
8be80ed3 916{
f0b5d12f
MF		 917 /* cannot program in software:
918 * evt0 - emulation (jtag)
919 * evt1 - reset
920 */
921 bfin_write_EVT2(evt_nmi);
8be80ed3
BS		 922 bfin_write_EVT3(trap);
923 bfin_write_EVT5(evt_ivhw);
924 bfin_write_EVT6(evt_timer);
925 bfin_write_EVT7(evt_evt7);
926 bfin_write_EVT8(evt_evt8);
927 bfin_write_EVT9(evt_evt9);
928 bfin_write_EVT10(evt_evt10);
929 bfin_write_EVT11(evt_evt11);
930 bfin_write_EVT12(evt_evt12);
931 bfin_write_EVT13(evt_evt13);
932 bfin_write_EVT14(evt14_softirq);
933 bfin_write_EVT15(evt_system_call);
934 CSYNC();
935}
936
1394f032
BW		 937/*
938 * This function should be called during kernel startup to initialize
939 * the BFin IRQ handling routines.
940 */
8d022374 941
1394f032
BW		 942int __init init_arch_irq(void)
943{
944 int irq;
945 unsigned long ilat = 0;
946 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
2f6f4bcd
BW		 947#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
948 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
24a07a12
RH		 949 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
950 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
a055b2b4 951# ifdef CONFIG_BF54x
59003145 952 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
a055b2b4 953# endif
6b3087c6
GY		 954# ifdef CONFIG_SMP
955 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
956 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
957# endif
24a07a12 958#else
1394f032 959 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
24a07a12 960#endif
1394f032
BW		 961
962 local_irq_disable();
963
d70536ec 964#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
95a86b5e
MF		 965 /* Clear EMAC Interrupt Status bits so we can demux it later */
966 bfin_write_EMAC_SYSTAT(-1);
967#endif
968
a055b2b4
MF		 969#ifdef CONFIG_BF54x
970# ifdef CONFIG_PINTx_REASSIGN
34e0fc89
MH		 971 pint[0]->assign = CONFIG_PINT0_ASSIGN;
972 pint[1]->assign = CONFIG_PINT1_ASSIGN;
973 pint[2]->assign = CONFIG_PINT2_ASSIGN;
974 pint[3]->assign = CONFIG_PINT3_ASSIGN;
a055b2b4 975# endif
34e0fc89
MH		 976 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
977 init_pint_lut();
978#endif
979
980 for (irq = 0; irq <= SYS_IRQS; irq++) {
1394f032
BW		 981 if (irq <= IRQ_CORETMR)
982 set_irq_chip(irq, &bfin_core_irqchip);
983 else
984 set_irq_chip(irq, &bfin_internal_irqchip);
1394f032 985
464abc5d 986 switch (irq) {
59003145 987#if defined(CONFIG_BF53x)
464abc5d 988 case IRQ_PROG_INTA:
a055b2b4 989# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
464abc5d 990 case IRQ_MAC_RX:
a055b2b4 991# endif
59003145 992#elif defined(CONFIG_BF54x)
464abc5d
MH		 993 case IRQ_PINT0:
994 case IRQ_PINT1:
995 case IRQ_PINT2:
996 case IRQ_PINT3:
2f6f4bcd 997#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
464abc5d
MH		 998 case IRQ_PORTF_INTA:
999 case IRQ_PORTG_INTA:
1000 case IRQ_PORTH_INTA:
2c4f829b 1001#elif defined(CONFIG_BF561)
464abc5d
MH		 1002 case IRQ_PROG0_INTA:
1003 case IRQ_PROG1_INTA:
1004 case IRQ_PROG2_INTA:
dc26aec2
MH		 1005#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1006 case IRQ_PORTF_INTA:
1394f032 1007#endif
dc26aec2 1008
464abc5d
MH		 1009 set_irq_chained_handler(irq,
1010 bfin_demux_gpio_irq);
1011 break;
1394f032 1012#ifdef BF537_GENERIC_ERROR_INT_DEMUX
464abc5d 1013 case IRQ_GENERIC_ERROR:
1394f032 1014 set_irq_handler(irq, bfin_demux_error_irq);
464abc5d
MH		 1015
1016 break;
1394f032 1017#endif
6b3087c6
GY		 1018#ifdef CONFIG_TICK_SOURCE_SYSTMR0
1019 case IRQ_TIMER0:
1020 set_irq_handler(irq, handle_percpu_irq);
1021 break;
1022#endif
1023#ifdef CONFIG_SMP
1024 case IRQ_SUPPLE_0:
1025 case IRQ_SUPPLE_1:
1026 set_irq_handler(irq, handle_percpu_irq);
1027 break;
1028#endif
464abc5d
MH		 1029 default:
1030 set_irq_handler(irq, handle_simple_irq);
1031 break;
1032 }
1394f032 1033 }
464abc5d 1034
1394f032 1035#ifdef BF537_GENERIC_ERROR_INT_DEMUX
464abc5d
MH		 1036 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1037 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1038 handle_level_irq);
1394f032
BW		 1039#endif
1040
464abc5d
MH		 1041 /* if configured as edge, then will be changed to do_edge_IRQ */
1042 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1043 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1044 handle_level_irq);
2c4f829b 1045
a055b2b4 1046
1394f032
BW		 1047 bfin_write_IMASK(0);
1048 CSYNC();
1049 ilat = bfin_read_ILAT();
1050 CSYNC();
1051 bfin_write_ILAT(ilat);
1052 CSYNC();
1053
34e0fc89 1054 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
40059784 1055 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1394f032
BW		 1056 * local_irq_enable()
1057 */
1058 program_IAR();
1059 /* Therefore it's better to setup IARs before interrupts enabled */
1060 search_IAR();
1061
1062 /* Enable interrupts IVG7-15 */
40059784 1063 bfin_irq_flags |= IMASK_IVG15 |
1394f032 1064 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
34e0fc89 1065 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1394f032 1066
2f6f4bcd
BW		 1067#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1068 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
56f5f590 1069 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
2f6f4bcd
BW		 1070#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1071 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
55546ac4
MH		 1072 * will screw up the bootrom as it relies on MDMA0/1 waking it
1073 * up from IDLE instructions. See this report for more info:
1074 * http://blackfin.uclinux.org/gf/tracker/4323
1075 */
b7e11293
MF		 1076 if (ANOMALY_05000435)
1077 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1078 else
1079 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
55546ac4 1080#else
56f5f590 1081 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
55546ac4 1082#endif
fe9ec9b9 1083# ifdef CONFIG_BF54x
56f5f590 1084 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
fe9ec9b9
MH		 1085# endif
1086#else
56f5f590 1087 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
fe9ec9b9
MH		 1088#endif
1089
1394f032
BW		 1090 return 0;
1091}
1092
1093#ifdef CONFIG_DO_IRQ_L1
a055b2b4 1094__attribute__((l1_text))
1394f032 1095#endif
1394f032
BW		 1096void do_irq(int vec, struct pt_regs *fp)
1097{
1098 if (vec == EVT_IVTMR_P) {
1099 vec = IRQ_CORETMR;
1100 } else {
1101 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1102 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
2f6f4bcd
BW		 1103#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1104 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
24a07a12 1105 unsigned long sic_status[3];
1394f032 1106
6b3087c6
GY		 1107 if (smp_processor_id()) {
1108#ifdef CONFIG_SMP
1109 /* This will be optimized out in UP mode. */
1110 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1111 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1112#endif
1113 } else {
1114 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1115 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1116 }
59003145 1117#ifdef CONFIG_BF54x
4fb45241 1118 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
59003145 1119#endif
1f83b8f1 1120 for (;; ivg++) {
24a07a12
RH		 1121 if (ivg >= ivg_stop) {
1122 atomic_inc(&num_spurious);
1123 return;
1124 }
34e0fc89 1125 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
24a07a12
RH		 1126 break;
1127 }
1128#else
1129 unsigned long sic_status;
464abc5d 1130
1394f032
BW		 1131 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1132
1133 for (;; ivg++) {
1134 if (ivg >= ivg_stop) {
1135 atomic_inc(&num_spurious);
1136 return;
1137 } else if (sic_status & ivg->isrflag)
1138 break;
1139 }
24a07a12 1140#endif
1394f032
BW		 1141 vec = ivg->irqno;
1142 }
1143 asm_do_IRQ(vec, fp);
1394f032 1144}
Linux kernel - Deliverables
This page took 0.236907 seconds and 5 git commands to generate.