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[Blackfin] arch: remove duplicated definitions of the line discipline numbers N_...
[deliverable/linux.git] / arch / blackfin / mach-common / ints-priority.c
CommitLineData
1394f032 1/*
cfefe3c6 2 * File: arch/blackfin/mach-common/ints-priority.c
1394f032
BW		 3 * Based on:
4 * Author:
5 *
6 * Created: ?
d2d50aa9 7 * Description: Set up the interrupt priorities
1394f032
BW		 8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
cfefe3c6 16 * Copyright 2004-2008 Analog Devices Inc.
1394f032
BW		 17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36#include <linux/module.h>
37#include <linux/kernel_stat.h>
38#include <linux/seq_file.h>
39#include <linux/irq.h>
40#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
48#ifdef BF537_FAMILY
49# define BF537_GENERIC_ERROR_INT_DEMUX
50#else
51# undef BF537_GENERIC_ERROR_INT_DEMUX
52#endif
53
54/*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
a99bbccd
MF		 61/* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67unsigned long irq_flags = 0x1f;
1394f032
BW		 68
69/* The number of spurious interrupts */
70atomic_t num_spurious;
71
cfefe3c6
MH		 72#ifdef CONFIG_PM
73unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74#endif
75
1394f032
BW		 76struct ivgx {
77 /* irq number for request_irq, available in mach-bf533/irq.h */
24a07a12 78 unsigned int irqno;
1394f032 79 /* corresponding bit in the SIC_ISR register */
24a07a12 80 unsigned int isrflag;
1394f032
BW		 81} ivg_table[NR_PERI_INTS];
82
83struct ivg_slice {
84 /* position of first irq in ivg_table for given ivg */
85 struct ivgx *ifirst;
86 struct ivgx *istop;
87} ivg7_13[IVG13 - IVG7 + 1];
88
89static void search_IAR(void);
90
91/*
92 * Search SIC_IAR and fill tables with the irqvalues
93 * and their positions in the SIC_ISR register.
94 */
95static void __init search_IAR(void)
96{
97 unsigned ivg, irq_pos = 0;
98 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
99 int irqn;
100
34e0fc89 101 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
1394f032
BW		 102
103 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
104 int iar_shift = (irqn & 7) * 4;
2c4f829b 105 if (ivg == (0xf &
59003145 106#ifndef CONFIG_BF52x
34e0fc89 107 bfin_read32((unsigned long *)SIC_IAR0 +
1394f032 108 (irqn >> 3)) >> iar_shift)) {
59003145
MH		 109#else
110 bfin_read32((unsigned long *)SIC_IAR0 +
111 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
112#endif
1394f032 113 ivg_table[irq_pos].irqno = IVG7 + irqn;
24a07a12 114 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
1394f032
BW		 115 ivg7_13[ivg].istop++;
116 irq_pos++;
117 }
118 }
119 }
120}
121
122/*
123 * This is for BF533 internal IRQs
124 */
125
126static void ack_noop(unsigned int irq)
127{
128 /* Dummy function. */
129}
130
131static void bfin_core_mask_irq(unsigned int irq)
132{
133 irq_flags &= ~(1 << irq);
134 if (!irqs_disabled())
135 local_irq_enable();
136}
137
138static void bfin_core_unmask_irq(unsigned int irq)
139{
140 irq_flags |= 1 << irq;
141 /*
142 * If interrupts are enabled, IMASK must contain the same value
143 * as irq_flags. Make sure that invariant holds. If interrupts
144 * are currently disabled we need not do anything; one of the
145 * callers will take care of setting IMASK to the proper value
146 * when reenabling interrupts.
147 * local_irq_enable just does "STI irq_flags", so it's exactly
148 * what we need.
149 */
150 if (!irqs_disabled())
151 local_irq_enable();
152 return;
153}
154
155static void bfin_internal_mask_irq(unsigned int irq)
156{
59003145 157#ifdef CONFIG_BF53x
1394f032
BW		 158 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
159 ~(1 << (irq - (IRQ_CORETMR + 1))));
24a07a12
RH		 160#else
161 unsigned mask_bank, mask_bit;
1f83b8f1
MF		 162 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
163 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
c04d66bb
BW		 164 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
165 ~(1 << mask_bit));
24a07a12 166#endif
1394f032
BW		 167 SSYNC();
168}
169
170static void bfin_internal_unmask_irq(unsigned int irq)
171{
59003145 172#ifdef CONFIG_BF53x
1394f032
BW		 173 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
174 (1 << (irq - (IRQ_CORETMR + 1))));
24a07a12
RH		 175#else
176 unsigned mask_bank, mask_bit;
1f83b8f1 177 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
c04d66bb
BW		 178 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
179 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
180 (1 << mask_bit));
24a07a12 181#endif
1394f032
BW		 182 SSYNC();
183}
184
cfefe3c6
MH		 185#ifdef CONFIG_PM
186int bfin_internal_set_wake(unsigned int irq, unsigned int state)
187{
188 unsigned bank, bit;
189 unsigned long flags;
190 bank = (irq - (IRQ_CORETMR + 1)) / 32;
191 bit = (irq - (IRQ_CORETMR + 1)) % 32;
192
193 local_irq_save(flags);
194
195 if (state)
196 bfin_sic_iwr[bank] |= (1 << bit);
197 else
198 bfin_sic_iwr[bank] &= ~(1 << bit);
199
200 local_irq_restore(flags);
201
202 return 0;
203}
204#endif
205
1394f032
BW		 206static struct irq_chip bfin_core_irqchip = {
207 .ack = ack_noop,
208 .mask = bfin_core_mask_irq,
209 .unmask = bfin_core_unmask_irq,
210};
211
212static struct irq_chip bfin_internal_irqchip = {
213 .ack = ack_noop,
214 .mask = bfin_internal_mask_irq,
215 .unmask = bfin_internal_unmask_irq,
cfefe3c6
MH		 216#ifdef CONFIG_PM
217 .set_wake = bfin_internal_set_wake,
218#endif
1394f032
BW		 219};
220
221#ifdef BF537_GENERIC_ERROR_INT_DEMUX
222static int error_int_mask;
223
224static void bfin_generic_error_ack_irq(unsigned int irq)
225{
226
227}
228
229static void bfin_generic_error_mask_irq(unsigned int irq)
230{
231 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
232
233 if (!error_int_mask) {
234 local_irq_disable();
235 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
2c4f829b 236 ~(1 << (IRQ_GENERIC_ERROR -
1394f032
BW		 237 (IRQ_CORETMR + 1))));
238 SSYNC();
239 local_irq_enable();
240 }
241}
242
243static void bfin_generic_error_unmask_irq(unsigned int irq)
244{
245 local_irq_disable();
246 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
247 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
248 SSYNC();
249 local_irq_enable();
250
251 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
252}
253
254static struct irq_chip bfin_generic_error_irqchip = {
255 .ack = bfin_generic_error_ack_irq,
256 .mask = bfin_generic_error_mask_irq,
257 .unmask = bfin_generic_error_unmask_irq,
258};
259
260static void bfin_demux_error_irq(unsigned int int_err_irq,
2c4f829b 261 struct irq_desc *inta_desc)
1394f032
BW		 262{
263 int irq = 0;
264
265 SSYNC();
266
267#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
268 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
269 irq = IRQ_MAC_ERROR;
270 else
271#endif
272 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
273 irq = IRQ_SPORT0_ERROR;
274 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
275 irq = IRQ_SPORT1_ERROR;
276 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
277 irq = IRQ_PPI_ERROR;
278 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
279 irq = IRQ_CAN_ERROR;
280 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
281 irq = IRQ_SPI_ERROR;
282 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
283 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
284 irq = IRQ_UART0_ERROR;
285 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
286 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
287 irq = IRQ_UART1_ERROR;
288
289 if (irq) {
290 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
291 struct irq_desc *desc = irq_desc + irq;
292 desc->handle_irq(irq, desc);
293 } else {
294
295 switch (irq) {
296 case IRQ_PPI_ERROR:
297 bfin_write_PPI_STATUS(PPI_ERR_MASK);
298 break;
299#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
300 case IRQ_MAC_ERROR:
301 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
302 break;
303#endif
304 case IRQ_SPORT0_ERROR:
305 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
306 break;
307
308 case IRQ_SPORT1_ERROR:
309 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
310 break;
311
312 case IRQ_CAN_ERROR:
313 bfin_write_CAN_GIS(CAN_ERR_MASK);
314 break;
315
316 case IRQ_SPI_ERROR:
317 bfin_write_SPI_STAT(SPI_ERR_MASK);
318 break;
319
320 default:
321 break;
322 }
323
324 pr_debug("IRQ %d:"
34e0fc89
MH		 325 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
326 irq);
1394f032
BW		 327 }
328 } else
329 printk(KERN_ERR
330 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
331 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
332 __FUNCTION__, __FILE__, __LINE__);
333
1394f032
BW		 334}
335#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
336
a055b2b4 337#if !defined(CONFIG_BF54x)
1394f032
BW		 338
339static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
340static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
341
6fce6a8d 342
1394f032
BW		 343static void bfin_gpio_ack_irq(unsigned int irq)
344{
345 u16 gpionr = irq - IRQ_PF0;
346
347 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
348 set_gpio_data(gpionr, 0);
349 SSYNC();
350 }
351}
352
353static void bfin_gpio_mask_ack_irq(unsigned int irq)
354{
355 u16 gpionr = irq - IRQ_PF0;
356
357 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
358 set_gpio_data(gpionr, 0);
359 SSYNC();
360 }
361
362 set_gpio_maska(gpionr, 0);
363 SSYNC();
364}
365
366static void bfin_gpio_mask_irq(unsigned int irq)
367{
368 set_gpio_maska(irq - IRQ_PF0, 0);
369 SSYNC();
370}
371
372static void bfin_gpio_unmask_irq(unsigned int irq)
373{
374 set_gpio_maska(irq - IRQ_PF0, 1);
375 SSYNC();
376}
377
378static unsigned int bfin_gpio_irq_startup(unsigned int irq)
379{
380 unsigned int ret;
381 u16 gpionr = irq - IRQ_PF0;
6fce6a8d 382 char buf[8];
1394f032
BW		 383
384 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 385 snprintf(buf, sizeof buf, "IRQ %d", irq);
386 ret = gpio_request(gpionr, buf);
1394f032
BW		 387 if (ret)
388 return ret;
389 }
390
391 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
392 bfin_gpio_unmask_irq(irq);
393
394 return ret;
395}
396
397static void bfin_gpio_irq_shutdown(unsigned int irq)
398{
399 bfin_gpio_mask_irq(irq);
400 gpio_free(irq - IRQ_PF0);
401 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
402}
403
404static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
405{
406
407 unsigned int ret;
6fce6a8d 408 char buf[8];
1394f032
BW		 409 u16 gpionr = irq - IRQ_PF0;
410
411 if (type == IRQ_TYPE_PROBE) {
412 /* only probe unenabled GPIO interrupt lines */
413 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
414 return 0;
415 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
416 }
417
418 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
34e0fc89 419 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
1394f032 420 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 421 snprintf(buf, sizeof buf, "IRQ %d", irq);
422 ret = gpio_request(gpionr, buf);
1394f032
BW		 423 if (ret)
424 return ret;
425 }
426
427 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
428 } else {
429 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
430 return 0;
431 }
432
433 set_gpio_dir(gpionr, 0);
434 set_gpio_inen(gpionr, 1);
435
436 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
437 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
438 set_gpio_edge(gpionr, 1);
439 } else {
440 set_gpio_edge(gpionr, 0);
441 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
442 }
443
444 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
445 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
446 set_gpio_both(gpionr, 1);
447 else
448 set_gpio_both(gpionr, 0);
449
450 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
451 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
452 else
453 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
454
455 SSYNC();
456
457 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
458 set_irq_handler(irq, handle_edge_irq);
459 else
460 set_irq_handler(irq, handle_level_irq);
461
462 return 0;
463}
464
cfefe3c6
MH		 465#ifdef CONFIG_PM
466int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
467{
468 unsigned gpio = irq_to_gpio(irq);
469
470 if (state)
471 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
472 else
473 gpio_pm_wakeup_free(gpio);
474
475 return 0;
476}
477#endif
478
1394f032
BW		 479static struct irq_chip bfin_gpio_irqchip = {
480 .ack = bfin_gpio_ack_irq,
481 .mask = bfin_gpio_mask_irq,
482 .mask_ack = bfin_gpio_mask_ack_irq,
483 .unmask = bfin_gpio_unmask_irq,
484 .set_type = bfin_gpio_irq_type,
485 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 486 .shutdown = bfin_gpio_irq_shutdown,
487#ifdef CONFIG_PM
488 .set_wake = bfin_gpio_set_wake,
489#endif
1394f032
BW		 490};
491
2c4f829b
MH		 492static void bfin_demux_gpio_irq(unsigned int inta_irq,
493 struct irq_desc *desc)
1394f032 494{
2c4f829b
MH		 495 unsigned int i, gpio, mask, irq, search = 0;
496
497 switch (inta_irq) {
498#if defined(CONFIG_BF53x)
499 case IRQ_PROG_INTA:
500 irq = IRQ_PF0;
501 search = 1;
502 break;
503# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
504 case IRQ_MAC_RX:
505 irq = IRQ_PH0;
506 break;
507# endif
508#elif defined(CONFIG_BF52x)
509 case IRQ_PORTF_INTA:
510 irq = IRQ_PF0;
511 break;
512 case IRQ_PORTG_INTA:
513 irq = IRQ_PG0;
514 break;
515 case IRQ_PORTH_INTA:
516 irq = IRQ_PH0;
517 break;
518#elif defined(CONFIG_BF561)
519 case IRQ_PROG0_INTA:
520 irq = IRQ_PF0;
521 break;
522 case IRQ_PROG1_INTA:
523 irq = IRQ_PF16;
524 break;
525 case IRQ_PROG2_INTA:
526 irq = IRQ_PF32;
527 break;
528#endif
529 default:
530 BUG();
531 return;
532 }
533
534 if (search) {
cfefe3c6 535 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
2c4f829b
MH		 536 irq += i;
537
538 mask = get_gpiop_data(i) &
539 (gpio_enabled[gpio_bank(i)] &
540 get_gpiop_maska(i));
541
542 while (mask) {
543 if (mask & 1) {
544 desc = irq_desc + irq;
545 desc->handle_irq(irq, desc);
546 }
547 irq++;
548 mask >>= 1;
1394f032 549 }
1394f032 550 }
2c4f829b
MH		 551 } else {
552 gpio = irq_to_gpio(irq);
553 mask = get_gpiop_data(gpio) &
554 (gpio_enabled[gpio_bank(gpio)] &
555 get_gpiop_maska(gpio));
556
557 do {
558 if (mask & 1) {
559 desc = irq_desc + irq;
560 desc->handle_irq(irq, desc);
561 }
562 irq++;
563 mask >>= 1;
564 } while (mask);
1394f032 565 }
2c4f829b 566
1394f032
BW		 567}
568
a055b2b4 569#else /* CONFIG_BF54x */
34e0fc89
MH		 570
571#define NR_PINT_SYS_IRQS 4
572#define NR_PINT_BITS 32
573#define NR_PINTS 160
574#define IRQ_NOT_AVAIL 0xFF
575
576#define PINT_2_BANK(x) ((x) >> 5)
577#define PINT_2_BIT(x) ((x) & 0x1F)
578#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
579
580static unsigned char irq2pint_lut[NR_PINTS];
e3f23000 581static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
34e0fc89 582
8baf560b
MH		 583static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
584static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
585
586
34e0fc89
MH		 587struct pin_int_t {
588 unsigned int mask_set;
589 unsigned int mask_clear;
590 unsigned int request;
591 unsigned int assign;
592 unsigned int edge_set;
593 unsigned int edge_clear;
594 unsigned int invert_set;
595 unsigned int invert_clear;
596 unsigned int pinstate;
597 unsigned int latch;
598};
599
600static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
601 (struct pin_int_t *)PINT0_MASK_SET,
602 (struct pin_int_t *)PINT1_MASK_SET,
603 (struct pin_int_t *)PINT2_MASK_SET,
604 (struct pin_int_t *)PINT3_MASK_SET,
605};
606
607unsigned short get_irq_base(u8 bank, u8 bmap)
608{
609
610 u16 irq_base;
611
612 if (bank < 2) { /*PA-PB */
613 irq_base = IRQ_PA0 + bmap * 16;
614 } else { /*PC-PJ */
615 irq_base = IRQ_PC0 + bmap * 16;
616 }
617
618 return irq_base;
619
620}
621
622 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
623void init_pint_lut(void)
624{
625 u16 bank, bit, irq_base, bit_pos;
626 u32 pint_assign;
627 u8 bmap;
628
629 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
630
631 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
632
633 pint_assign = pint[bank]->assign;
634
635 for (bit = 0; bit < NR_PINT_BITS; bit++) {
636
637 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
638
639 irq_base = get_irq_base(bank, bmap);
640
641 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
642 bit_pos = bit + bank * NR_PINT_BITS;
643
e3f23000 644 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
34e0fc89
MH		 645 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
646
647 }
648
649 }
650
651}
652
34e0fc89
MH		 653static void bfin_gpio_ack_irq(unsigned int irq)
654{
655 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
8baf560b
MH		 656 u32 pintbit = PINT_BIT(pint_val);
657 u8 bank = PINT_2_BANK(pint_val);
658
659 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
660 if (pint[bank]->invert_set & pintbit)
661 pint[bank]->invert_clear = pintbit;
662 else
663 pint[bank]->invert_set = pintbit;
664 }
665 pint[bank]->request = pintbit;
34e0fc89 666
34e0fc89
MH		 667 SSYNC();
668}
669
670static void bfin_gpio_mask_ack_irq(unsigned int irq)
671{
672 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 673 u32 pintbit = PINT_BIT(pint_val);
674 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 675
8baf560b
MH		 676 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
677 if (pint[bank]->invert_set & pintbit)
678 pint[bank]->invert_clear = pintbit;
679 else
680 pint[bank]->invert_set = pintbit;
681 }
682
e3f23000
MH		 683 pint[bank]->request = pintbit;
684 pint[bank]->mask_clear = pintbit;
34e0fc89
MH		 685 SSYNC();
686}
687
688static void bfin_gpio_mask_irq(unsigned int irq)
689{
690 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
691
692 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
693 SSYNC();
694}
695
696static void bfin_gpio_unmask_irq(unsigned int irq)
697{
698 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 699 u32 pintbit = PINT_BIT(pint_val);
700 u8 bank = PINT_2_BANK(pint_val);
34e0fc89 701
e3f23000
MH		 702 pint[bank]->request = pintbit;
703 pint[bank]->mask_set = pintbit;
34e0fc89
MH		 704 SSYNC();
705}
706
707static unsigned int bfin_gpio_irq_startup(unsigned int irq)
708{
709 unsigned int ret;
6fce6a8d 710 char buf[8];
8baf560b 711 u16 gpionr = irq_to_gpio(irq);
34e0fc89
MH		 712 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
713
50e163ce
MH		 714 if (pint_val == IRQ_NOT_AVAIL) {
715 printk(KERN_ERR
716 "GPIO IRQ %d :Not in PINT Assign table "
717 "Reconfigure Interrupt to Port Assignemt\n", irq);
34e0fc89 718 return -ENODEV;
50e163ce 719 }
34e0fc89
MH		 720
721 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 722 snprintf(buf, sizeof buf, "IRQ %d", irq);
723 ret = gpio_request(gpionr, buf);
34e0fc89
MH		 724 if (ret)
725 return ret;
726 }
727
728 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
729 bfin_gpio_unmask_irq(irq);
730
731 return ret;
732}
733
734static void bfin_gpio_irq_shutdown(unsigned int irq)
735{
8baf560b
MH		 736 u16 gpionr = irq_to_gpio(irq);
737
34e0fc89 738 bfin_gpio_mask_irq(irq);
8baf560b
MH		 739 gpio_free(gpionr);
740 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
34e0fc89
MH		 741}
742
743static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
744{
745
746 unsigned int ret;
6fce6a8d 747 char buf[8];
8baf560b 748 u16 gpionr = irq_to_gpio(irq);
34e0fc89 749 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
e3f23000
MH		 750 u32 pintbit = PINT_BIT(pint_val);
751 u8 bank = PINT_2_BANK(pint_val);
34e0fc89
MH		 752
753 if (pint_val == IRQ_NOT_AVAIL)
754 return -ENODEV;
755
756 if (type == IRQ_TYPE_PROBE) {
757 /* only probe unenabled GPIO interrupt lines */
758 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
759 return 0;
760 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
761 }
762
763 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
764 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
765 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
6fce6a8d
MH		 766 snprintf(buf, sizeof buf, "IRQ %d", irq);
767 ret = gpio_request(gpionr, buf);
34e0fc89
MH		 768 if (ret)
769 return ret;
770 }
771
772 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
773 } else {
774 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
775 return 0;
776 }
777
778 gpio_direction_input(gpionr);
779
34e0fc89 780 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
e3f23000 781 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
34e0fc89 782 else
8baf560b 783 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
34e0fc89 784
8baf560b
MH		 785 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
786 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
34e0fc89 787
8baf560b 788 gpio_both_edge_triggered[bank] |= pintbit;
34e0fc89 789
8baf560b
MH		 790 if (gpio_get_value(gpionr))
791 pint[bank]->invert_set = pintbit;
792 else
793 pint[bank]->invert_clear = pintbit;
794 } else {
795 gpio_both_edge_triggered[bank] &= ~pintbit;
796 }
797
798 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
799 pint[bank]->edge_set = pintbit;
34e0fc89 800 set_irq_handler(irq, handle_edge_irq);
8baf560b
MH		 801 } else {
802 pint[bank]->edge_clear = pintbit;
34e0fc89 803 set_irq_handler(irq, handle_level_irq);
8baf560b
MH		 804 }
805
806 SSYNC();
34e0fc89
MH		 807
808 return 0;
809}
810
cfefe3c6
MH		 811#ifdef CONFIG_PM
812u32 pint_saved_masks[NR_PINT_SYS_IRQS];
813u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
814
815int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
816{
817 u32 pint_irq;
818 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
819 u32 bank = PINT_2_BANK(pint_val);
820 u32 pintbit = PINT_BIT(pint_val);
821
822 switch (bank) {
823 case 0:
824 pint_irq = IRQ_PINT0;
825 break;
826 case 2:
827 pint_irq = IRQ_PINT2;
828 break;
829 case 3:
830 pint_irq = IRQ_PINT3;
831 break;
832 case 1:
833 pint_irq = IRQ_PINT1;
834 break;
835 default:
836 return -EINVAL;
837 }
838
839 bfin_internal_set_wake(pint_irq, state);
840
841 if (state)
842 pint_wakeup_masks[bank] |= pintbit;
843 else
844 pint_wakeup_masks[bank] &= ~pintbit;
845
846 return 0;
847}
848
849u32 bfin_pm_setup(void)
850{
851 u32 val, i;
852
853 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
854 val = pint[i]->mask_clear;
855 pint_saved_masks[i] = val;
856 if (val ^ pint_wakeup_masks[i]) {
857 pint[i]->mask_clear = val;
858 pint[i]->mask_set = pint_wakeup_masks[i];
859 }
860 }
861
862 return 0;
863}
864
865void bfin_pm_restore(void)
866{
867 u32 i, val;
868
869 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
870 val = pint_saved_masks[i];
871 if (val ^ pint_wakeup_masks[i]) {
872 pint[i]->mask_clear = pint[i]->mask_clear;
873 pint[i]->mask_set = val;
874 }
875 }
876}
877#endif
878
34e0fc89
MH		 879static struct irq_chip bfin_gpio_irqchip = {
880 .ack = bfin_gpio_ack_irq,
881 .mask = bfin_gpio_mask_irq,
882 .mask_ack = bfin_gpio_mask_ack_irq,
883 .unmask = bfin_gpio_unmask_irq,
884 .set_type = bfin_gpio_irq_type,
885 .startup = bfin_gpio_irq_startup,
cfefe3c6
MH		 886 .shutdown = bfin_gpio_irq_shutdown,
887#ifdef CONFIG_PM
888 .set_wake = bfin_gpio_set_wake,
889#endif
34e0fc89
MH		 890};
891
2c4f829b
MH		 892static void bfin_demux_gpio_irq(unsigned int inta_irq,
893 struct irq_desc *desc)
34e0fc89
MH		 894{
895 u8 bank, pint_val;
896 u32 request, irq;
897
2c4f829b 898 switch (inta_irq) {
34e0fc89
MH		 899 case IRQ_PINT0:
900 bank = 0;
901 break;
902 case IRQ_PINT2:
903 bank = 2;
904 break;
905 case IRQ_PINT3:
906 bank = 3;
907 break;
908 case IRQ_PINT1:
909 bank = 1;
910 break;
e3f23000
MH		 911 default:
912 return;
34e0fc89
MH		 913 }
914
915 pint_val = bank * NR_PINT_BITS;
916
917 request = pint[bank]->request;
918
919 while (request) {
920 if (request & 1) {
e3f23000
MH		 921 irq = pint2irq_lut[pint_val] + SYS_IRQS;
922 desc = irq_desc + irq;
34e0fc89
MH		 923 desc->handle_irq(irq, desc);
924 }
925 pint_val++;
926 request >>= 1;
927 }
928
929}
a055b2b4 930#endif
1394f032 931
8be80ed3
BS		 932void __init init_exception_vectors(void)
933{
934 SSYNC();
935
f0b5d12f
MF		 936 /* cannot program in software:
937 * evt0 - emulation (jtag)
938 * evt1 - reset
939 */
940 bfin_write_EVT2(evt_nmi);
8be80ed3
BS		 941 bfin_write_EVT3(trap);
942 bfin_write_EVT5(evt_ivhw);
943 bfin_write_EVT6(evt_timer);
944 bfin_write_EVT7(evt_evt7);
945 bfin_write_EVT8(evt_evt8);
946 bfin_write_EVT9(evt_evt9);
947 bfin_write_EVT10(evt_evt10);
948 bfin_write_EVT11(evt_evt11);
949 bfin_write_EVT12(evt_evt12);
950 bfin_write_EVT13(evt_evt13);
951 bfin_write_EVT14(evt14_softirq);
952 bfin_write_EVT15(evt_system_call);
953 CSYNC();
954}
955
1394f032
BW		 956/*
957 * This function should be called during kernel startup to initialize
958 * the BFin IRQ handling routines.
959 */
960int __init init_arch_irq(void)
961{
962 int irq;
963 unsigned long ilat = 0;
964 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
2c4f829b 965#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
24a07a12
RH		 966 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
967 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1c5d2265
MH		 968 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
969 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
a055b2b4 970# ifdef CONFIG_BF54x
59003145 971 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
c04d66bb 972 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
a055b2b4 973# endif
24a07a12 974#else
1394f032 975 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1c5d2265 976 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
24a07a12 977#endif
1394f032
BW		 978 SSYNC();
979
980 local_irq_disable();
981
2c4f829b
MH		 982 init_exception_buff();
983
a055b2b4
MF		 984#ifdef CONFIG_BF54x
985# ifdef CONFIG_PINTx_REASSIGN
34e0fc89
MH		 986 pint[0]->assign = CONFIG_PINT0_ASSIGN;
987 pint[1]->assign = CONFIG_PINT1_ASSIGN;
988 pint[2]->assign = CONFIG_PINT2_ASSIGN;
989 pint[3]->assign = CONFIG_PINT3_ASSIGN;
a055b2b4 990# endif
34e0fc89
MH		 991 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
992 init_pint_lut();
993#endif
994
995 for (irq = 0; irq <= SYS_IRQS; irq++) {
1394f032
BW		 996 if (irq <= IRQ_CORETMR)
997 set_irq_chip(irq, &bfin_core_irqchip);
998 else
999 set_irq_chip(irq, &bfin_internal_irqchip);
1000#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1001 if (irq != IRQ_GENERIC_ERROR) {
1002#endif
1003
34e0fc89 1004 switch (irq) {
59003145 1005#if defined(CONFIG_BF53x)
34e0fc89
MH		 1006 case IRQ_PROG_INTA:
1007 set_irq_chained_handler(irq,
1008 bfin_demux_gpio_irq);
1009 break;
a055b2b4 1010# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
34e0fc89
MH		 1011 case IRQ_MAC_RX:
1012 set_irq_chained_handler(irq,
1013 bfin_demux_gpio_irq);
1014 break;
a055b2b4 1015# endif
59003145 1016#elif defined(CONFIG_BF54x)
34e0fc89 1017 case IRQ_PINT0:
1394f032
BW		 1018 set_irq_chained_handler(irq,
1019 bfin_demux_gpio_irq);
34e0fc89
MH		 1020 break;
1021 case IRQ_PINT1:
1022 set_irq_chained_handler(irq,
1023 bfin_demux_gpio_irq);
1024 break;
1025 case IRQ_PINT2:
1026 set_irq_chained_handler(irq,
1027 bfin_demux_gpio_irq);
1028 break;
1029 case IRQ_PINT3:
1030 set_irq_chained_handler(irq,
1031 bfin_demux_gpio_irq);
1032 break;
59003145
MH		 1033#elif defined(CONFIG_BF52x)
1034 case IRQ_PORTF_INTA:
1035 set_irq_chained_handler(irq,
1036 bfin_demux_gpio_irq);
1037 break;
1038 case IRQ_PORTG_INTA:
1039 set_irq_chained_handler(irq,
1040 bfin_demux_gpio_irq);
1041 break;
1042 case IRQ_PORTH_INTA:
1043 set_irq_chained_handler(irq,
1044 bfin_demux_gpio_irq);
1045 break;
2c4f829b
MH		 1046#elif defined(CONFIG_BF561)
1047 case IRQ_PROG0_INTA:
1048 set_irq_chained_handler(irq,
1049 bfin_demux_gpio_irq);
1050 break;
1051 case IRQ_PROG1_INTA:
1052 set_irq_chained_handler(irq,
1053 bfin_demux_gpio_irq);
1054 break;
1055 case IRQ_PROG2_INTA:
1056 set_irq_chained_handler(irq,
1057 bfin_demux_gpio_irq);
1058 break;
1394f032 1059#endif
34e0fc89
MH		 1060 default:
1061 set_irq_handler(irq, handle_simple_irq);
1062 break;
1063 }
1394f032
BW		 1064
1065#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1066 } else {
1067 set_irq_handler(irq, bfin_demux_error_irq);
1068 }
1069#endif
1070 }
1071#ifdef BF537_GENERIC_ERROR_INT_DEMUX
1072 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
1073 set_irq_chip(irq, &bfin_generic_error_irqchip);
1074 set_irq_handler(irq, handle_level_irq);
1075 }
1076#endif
1077
2c4f829b
MH		 1078 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) {
1079
1394f032
BW		 1080 set_irq_chip(irq, &bfin_gpio_irqchip);
1081 /* if configured as edge, then will be changed to do_edge_IRQ */
1082 set_irq_handler(irq, handle_level_irq);
1083 }
a055b2b4 1084
1394f032
BW		 1085 bfin_write_IMASK(0);
1086 CSYNC();
1087 ilat = bfin_read_ILAT();
1088 CSYNC();
1089 bfin_write_ILAT(ilat);
1090 CSYNC();
1091
34e0fc89 1092 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1394f032
BW		 1093 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1094 * local_irq_enable()
1095 */
1096 program_IAR();
1097 /* Therefore it's better to setup IARs before interrupts enabled */
1098 search_IAR();
1099
1100 /* Enable interrupts IVG7-15 */
1101 irq_flags = irq_flags | IMASK_IVG15 |
1102 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
34e0fc89 1103 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1394f032
BW		 1104
1105 return 0;
1106}
1107
1108#ifdef CONFIG_DO_IRQ_L1
a055b2b4 1109__attribute__((l1_text))
1394f032 1110#endif
1394f032
BW		 1111void do_irq(int vec, struct pt_regs *fp)
1112{
1113 if (vec == EVT_IVTMR_P) {
1114 vec = IRQ_CORETMR;
1115 } else {
1116 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1117 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
2c4f829b 1118#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
24a07a12 1119 unsigned long sic_status[3];
1394f032 1120
24a07a12 1121 SSYNC();
4fb45241
MH		 1122 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1123 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
59003145 1124#ifdef CONFIG_BF54x
4fb45241 1125 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
59003145 1126#endif
1f83b8f1 1127 for (;; ivg++) {
24a07a12
RH		 1128 if (ivg >= ivg_stop) {
1129 atomic_inc(&num_spurious);
1130 return;
1131 }
34e0fc89 1132 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
24a07a12
RH		 1133 break;
1134 }
1135#else
1136 unsigned long sic_status;
1394f032
BW		 1137 SSYNC();
1138 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1139
1140 for (;; ivg++) {
1141 if (ivg >= ivg_stop) {
1142 atomic_inc(&num_spurious);
1143 return;
1144 } else if (sic_status & ivg->isrflag)
1145 break;
1146 }
24a07a12 1147#endif
1394f032
BW		 1148 vec = ivg->irqno;
1149 }
1150 asm_do_IRQ(vec, fp);
1151
1152#ifdef CONFIG_KGDB
1153 kgdb_process_breakpoint();
1154#endif
1155}
Linux kernel - Deliverables
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