[deliverable/linux.git] / arch / blackfin / mach-common / smp.c

/*
 * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
 *
 * Copyright 2007-2009 Analog Devices Inc.
 *                         Philippe Gerum <rpm@xenomai.org>
 *
 * Licensed under the GPL-2.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/cache.h>
#include <linux/profile.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/cpu.h>
#include <linux/smp.h>
#include <linux/cpumask.h>
#include <linux/seq_file.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/cpu.h>
#include <asm/time.h>
#include <linux/err.h>

/*
 * Anomaly notes:
 * 05000120 - we always define corelock as 32-bit integer in L2
 */
struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));

#ifdef CONFIG_ICACHE_FLUSH_L1
unsigned long blackfin_iflush_l1_entry[NR_CPUS];
#endif

void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
	*init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
	*init_saved_dcplb_fault_addr_coreb;

#define BFIN_IPI_RESCHEDULE   0
#define BFIN_IPI_CALL_FUNC    1
#define BFIN_IPI_CPU_STOP     2

struct blackfin_flush_data {
	unsigned long start;
	unsigned long end;
};

void *secondary_stack;


struct smp_call_struct {
	void (*func)(void *info);
	void *info;
	int wait;
	cpumask_t *waitmask;
};

static struct blackfin_flush_data smp_flush_data;

static DEFINE_SPINLOCK(stop_lock);

struct ipi_message {
	unsigned long type;
	struct smp_call_struct call_struct;
};

/* A magic number - stress test shows this is safe for common cases */
#define BFIN_IPI_MSGQ_LEN 5

/* Simple FIFO buffer, overflow leads to panic */
struct ipi_message_queue {
	spinlock_t lock;
	unsigned long count;
	unsigned long head; /* head of the queue */
	struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
};

static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);

static void ipi_cpu_stop(unsigned int cpu)
{
	spin_lock(&stop_lock);
	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	dump_stack();
	spin_unlock(&stop_lock);

	cpu_clear(cpu, cpu_online_map);

	local_irq_disable();

	while (1)
		SSYNC();
}

static void ipi_flush_icache(void *info)
{
	struct blackfin_flush_data *fdata = info;

	/* Invalidate the memory holding the bounds of the flushed region. */
	invalidate_dcache_range((unsigned long)fdata,
		(unsigned long)fdata + sizeof(*fdata));

	flush_icache_range(fdata->start, fdata->end);
}

static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
{
	int wait;
	void (*func)(void *info);
	void *info;
	func = msg->call_struct.func;
	info = msg->call_struct.info;
	wait = msg->call_struct.wait;
	func(info);
	if (wait) {
#ifdef __ARCH_SYNC_CORE_DCACHE
		/*
		 * 'wait' usually means synchronization between CPUs.
		 * Invalidate D cache in case shared data was changed
		 * by func() to ensure cache coherence.
		 */
		resync_core_dcache();
#endif
		cpu_clear(cpu, *msg->call_struct.waitmask);
	}
}

/* Use IRQ_SUPPLE_0 to request reschedule.
 * When returning from interrupt to user space,
 * there is chance to reschedule */
static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
{
	unsigned int cpu = smp_processor_id();

	platform_clear_ipi(cpu, IRQ_SUPPLE_0);
	return IRQ_HANDLED;
}

static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
{
	struct ipi_message *msg;
	struct ipi_message_queue *msg_queue;
	unsigned int cpu = smp_processor_id();
	unsigned long flags;

	platform_clear_ipi(cpu, IRQ_SUPPLE_1);

	msg_queue = &__get_cpu_var(ipi_msg_queue);

	spin_lock_irqsave(&msg_queue->lock, flags);

	while (msg_queue->count) {
		msg = &msg_queue->ipi_message[msg_queue->head];
		switch (msg->type) {
		case BFIN_IPI_CALL_FUNC:
			spin_unlock_irqrestore(&msg_queue->lock, flags);
			ipi_call_function(cpu, msg);
			spin_lock_irqsave(&msg_queue->lock, flags);
			break;
		case BFIN_IPI_CPU_STOP:
			spin_unlock_irqrestore(&msg_queue->lock, flags);
			ipi_cpu_stop(cpu);
			spin_lock_irqsave(&msg_queue->lock, flags);
			break;
		default:
			printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
			       cpu, msg->type);
			break;
		}
		msg_queue->head++;
		msg_queue->head %= BFIN_IPI_MSGQ_LEN;
		msg_queue->count--;
	}
	spin_unlock_irqrestore(&msg_queue->lock, flags);
	return IRQ_HANDLED;
}

static void ipi_queue_init(void)
{
	unsigned int cpu;
	struct ipi_message_queue *msg_queue;
	for_each_possible_cpu(cpu) {
		msg_queue = &per_cpu(ipi_msg_queue, cpu);
		spin_lock_init(&msg_queue->lock);
		msg_queue->count = 0;
		msg_queue->head = 0;
	}
}

static inline void smp_send_message(cpumask_t callmap, unsigned long type,
					void (*func) (void *info), void *info, int wait)
{
	unsigned int cpu;
	struct ipi_message_queue *msg_queue;
	struct ipi_message *msg;
	unsigned long flags, next_msg;
	cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */

	for_each_cpu_mask(cpu, callmap) {
		msg_queue = &per_cpu(ipi_msg_queue, cpu);
		spin_lock_irqsave(&msg_queue->lock, flags);
		if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
			next_msg = (msg_queue->head + msg_queue->count)
					% BFIN_IPI_MSGQ_LEN;
			msg = &msg_queue->ipi_message[next_msg];
			msg->type = type;
			if (type == BFIN_IPI_CALL_FUNC) {
				msg->call_struct.func = func;
				msg->call_struct.info = info;
				msg->call_struct.wait = wait;
				msg->call_struct.waitmask = &waitmask;
			}
			msg_queue->count++;
		} else
			panic("IPI message queue overflow\n");
		spin_unlock_irqrestore(&msg_queue->lock, flags);
		platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
	}

	if (wait) {
		while (!cpus_empty(waitmask))
			blackfin_dcache_invalidate_range(
				(unsigned long)(&waitmask),
				(unsigned long)(&waitmask));
#ifdef __ARCH_SYNC_CORE_DCACHE
		/*
		 * Invalidate D cache in case shared data was changed by
		 * other processors to ensure cache coherence.
		 */
		resync_core_dcache();
#endif
	}
}

int smp_call_function(void (*func)(void *info), void *info, int wait)
{
	cpumask_t callmap;

	preempt_disable();
	callmap = cpu_online_map;
	cpu_clear(smp_processor_id(), callmap);
	if (!cpus_empty(callmap))
		smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);

	preempt_enable();

	return 0;
}
EXPORT_SYMBOL_GPL(smp_call_function);

int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
				int wait)
{
	unsigned int cpu = cpuid;
	cpumask_t callmap;

	if (cpu_is_offline(cpu))
		return 0;
	cpus_clear(callmap);
	cpu_set(cpu, callmap);

	smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);

	return 0;
}
EXPORT_SYMBOL_GPL(smp_call_function_single);

void smp_send_reschedule(int cpu)
{
	/* simply trigger an ipi */
	if (cpu_is_offline(cpu))
		return;
	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);

	return;
}

void smp_send_stop(void)
{
	cpumask_t callmap;

	preempt_disable();
	callmap = cpu_online_map;
	cpu_clear(smp_processor_id(), callmap);
	if (!cpus_empty(callmap))
		smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);

	preempt_enable();

	return;
}

int __cpuinit __cpu_up(unsigned int cpu)
{
	int ret;
	static struct task_struct *idle;

	if (idle)
		free_task(idle);

	idle = fork_idle(cpu);
	if (IS_ERR(idle)) {
		printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
		return PTR_ERR(idle);
	}

	secondary_stack = task_stack_page(idle) + THREAD_SIZE;

	ret = platform_boot_secondary(cpu, idle);

	secondary_stack = NULL;

	return ret;
}

static void __cpuinit setup_secondary(unsigned int cpu)
{
	unsigned long ilat;

	bfin_write_IMASK(0);
	CSYNC();
	ilat = bfin_read_ILAT();
	CSYNC();
	bfin_write_ILAT(ilat);
	CSYNC();

	/* Enable interrupt levels IVG7-15. IARs have been already
	 * programmed by the boot CPU.  */
	bfin_irq_flags |= IMASK_IVG15 |
	    IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
	    IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
}

void __cpuinit secondary_start_kernel(void)
{
	unsigned int cpu = smp_processor_id();
	struct mm_struct *mm = &init_mm;

	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
		printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
#ifdef CONFIG_DEBUG_DOUBLEFAULT
		printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
			(int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
		printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
		printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
#endif
		printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
			init_retx_coreb);
	}

	/*
	 * We want the D-cache to be enabled early, in case the atomic
	 * support code emulates cache coherence (see
	 * __ARCH_SYNC_CORE_DCACHE).
	 */
	init_exception_vectors();

	local_irq_disable();

	/* Attach the new idle task to the global mm. */
	atomic_inc(&mm->mm_users);
	atomic_inc(&mm->mm_count);
	current->active_mm = mm;

	preempt_disable();

	setup_secondary(cpu);

	platform_secondary_init(cpu);

	/* setup local core timer */
	bfin_local_timer_setup();

	local_irq_enable();

	bfin_setup_caches(cpu);

	/*
	 * Calibrate loops per jiffy value.
	 * IRQs need to be enabled here - D-cache can be invalidated
	 * in timer irq handler, so core B can read correct jiffies.
	 */
	calibrate_delay();

	cpu_idle();
}

void __init smp_prepare_boot_cpu(void)
{
}

void __init smp_prepare_cpus(unsigned int max_cpus)
{
	platform_prepare_cpus(max_cpus);
	ipi_queue_init();
	platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
	platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
}

void __init smp_cpus_done(unsigned int max_cpus)
{
	unsigned long bogosum = 0;
	unsigned int cpu;

	for_each_online_cpu(cpu)
		bogosum += loops_per_jiffy;

	printk(KERN_INFO "SMP: Total of %d processors activated "
	       "(%lu.%02lu BogoMIPS).\n",
	       num_online_cpus(),
	       bogosum / (500000/HZ),
	       (bogosum / (5000/HZ)) % 100);
}

void smp_icache_flush_range_others(unsigned long start, unsigned long end)
{
	smp_flush_data.start = start;
	smp_flush_data.end = end;

	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
		printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
}
EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);

#ifdef __ARCH_SYNC_CORE_ICACHE
unsigned long icache_invld_count[NR_CPUS];
void resync_core_icache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_icache();
	icache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_icache);
#endif

#ifdef __ARCH_SYNC_CORE_DCACHE
unsigned long dcache_invld_count[NR_CPUS];
unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));

void resync_core_dcache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_dcache();
	dcache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_dcache);
#endif

#ifdef CONFIG_HOTPLUG_CPU
int __cpuexit __cpu_disable(void)
{
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EPERM;

	set_cpu_online(cpu, false);
	return 0;
}

static DECLARE_COMPLETION(cpu_killed);

int __cpuexit __cpu_die(unsigned int cpu)
{
	return wait_for_completion_timeout(&cpu_killed, 5000);
}

void cpu_die(void)
{
	complete(&cpu_killed);

	atomic_dec(&init_mm.mm_users);
	atomic_dec(&init_mm.mm_count);

	local_irq_disable();
	platform_cpu_die();
}
#endif
Commit	Line	Data
6b3087c6	1	/*
96f1050d	2	* IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
6b3087c6	3	*
96f1050d RG	4	* Copyright 2007-2009 Analog Devices Inc.
96f1050d RG	5	* Philippe Gerum <rpm@xenomai.org>
6b3087c6	6	*
96f1050d	7	* Licensed under the GPL-2.
6b3087c6 GY	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/sched.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/cache.h>
	17	#include <linux/profile.h>
	18	#include <linux/errno.h>
	19	#include <linux/mm.h>
	20	#include <linux/cpu.h>
	21	#include <linux/smp.h>
9c199b59	22	#include <linux/cpumask.h>
6b3087c6 GY	23	#include <linux/seq_file.h>
6b3087c6 GY	24	#include <linux/irq.h>
5a0e3ad6	25	#include <linux/slab.h>
6b3087c6 GY	26	#include <asm/atomic.h>
	27	#include <asm/cacheflush.h>
	28	#include <asm/mmu_context.h>
	29	#include <asm/pgtable.h>
	30	#include <asm/pgalloc.h>
	31	#include <asm/processor.h>
	32	#include <asm/ptrace.h>
	33	#include <asm/cpu.h>
1fa9be72	34	#include <asm/time.h>
6b3087c6 GY	35	#include <linux/err.h>
6b3087c6 GY	36
555487bb GY	37	/*
	38	* Anomaly notes:
	39	* 05000120 - we always define corelock as 32-bit integer in L2
	40	*/
6b3087c6 GY	41	struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
6b3087c6 GY	42
c6345ab1 SZ	43	#ifdef CONFIG_ICACHE_FLUSH_L1
	44	unsigned long blackfin_iflush_l1_entry[NR_CPUS];
	45	#endif
	46
6b3087c6 GY	47	void __cpuinitdata init_retx_coreb, init_saved_retx_coreb,
	48	init_saved_seqstat_coreb, init_saved_icplb_fault_addr_coreb,
	49	*init_saved_dcplb_fault_addr_coreb;
	50
6b3087c6 GY	51	#define BFIN_IPI_RESCHEDULE 0
	52	#define BFIN_IPI_CALL_FUNC 1
	53	#define BFIN_IPI_CPU_STOP 2
	54
	55	struct blackfin_flush_data {
	56	unsigned long start;
	57	unsigned long end;
	58	};
	59
	60	void *secondary_stack;
	61
	62
	63	struct smp_call_struct {
	64	void (func)(void info);
	65	void *info;
	66	int wait;
73a40064	67	cpumask_t *waitmask;
6b3087c6 GY	68	};
	69
	70	static struct blackfin_flush_data smp_flush_data;
	71
	72	static DEFINE_SPINLOCK(stop_lock);
	73
	74	struct ipi_message {
6b3087c6 GY	75	unsigned long type;
	76	struct smp_call_struct call_struct;
	77	};
	78
73a40064 YL	79	/* A magic number - stress test shows this is safe for common cases */
	80	#define BFIN_IPI_MSGQ_LEN 5
	81
	82	/* Simple FIFO buffer, overflow leads to panic */
6b3087c6	83	struct ipi_message_queue {
6b3087c6 GY	84	spinlock_t lock;
6b3087c6 GY	85	unsigned long count;
73a40064 YL	86	unsigned long head; /* head of the queue */
73a40064 YL	87	struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
6b3087c6 GY	88	};
	89
	90	static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
	91
	92	static void ipi_cpu_stop(unsigned int cpu)
	93	{
	94	spin_lock(&stop_lock);
	95	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	96	dump_stack();
	97	spin_unlock(&stop_lock);
	98
	99	cpu_clear(cpu, cpu_online_map);
	100
	101	local_irq_disable();
	102
	103	while (1)
	104	SSYNC();
	105	}
	106
	107	static void ipi_flush_icache(void *info)
	108	{
	109	struct blackfin_flush_data *fdata = info;
	110
	111	/* Invalidate the memory holding the bounds of the flushed region. */
5f362c91 MF	112	invalidate_dcache_range((unsigned long)fdata,
5f362c91 MF	113	(unsigned long)fdata + sizeof(*fdata));
6b3087c6	114
5f362c91	115	flush_icache_range(fdata->start, fdata->end);
6b3087c6 GY	116	}
	117
	118	static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
	119	{
	120	int wait;
	121	void (func)(void info);
	122	void *info;
	123	func = msg->call_struct.func;
	124	info = msg->call_struct.info;
	125	wait = msg->call_struct.wait;
6b3087c6	126	func(info);
c9784ebb YL	127	if (wait) {
	128	#ifdef __ARCH_SYNC_CORE_DCACHE
	129	/*
	130	* 'wait' usually means synchronization between CPUs.
	131	* Invalidate D cache in case shared data was changed
	132	* by func() to ensure cache coherence.
	133	*/
	134	resync_core_dcache();
	135	#endif
73a40064 YL	136	cpu_clear(cpu, *msg->call_struct.waitmask);
73a40064 YL	137	}
6b3087c6 GY	138	}
6b3087c6 GY	139
73a40064 YL	140	/* Use IRQ_SUPPLE_0 to request reschedule.
	141	* When returning from interrupt to user space,
	142	* there is chance to reschedule */
	143	static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
	144	{
	145	unsigned int cpu = smp_processor_id();
	146
	147	platform_clear_ipi(cpu, IRQ_SUPPLE_0);
	148	return IRQ_HANDLED;
	149	}
	150
	151	static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
6b3087c6	152	{
86f2008b	153	struct ipi_message *msg;
6b3087c6 GY	154	struct ipi_message_queue *msg_queue;
6b3087c6 GY	155	unsigned int cpu = smp_processor_id();
73a40064	156	unsigned long flags;
6b3087c6	157
73a40064	158	platform_clear_ipi(cpu, IRQ_SUPPLE_1);
6b3087c6 GY	159
6b3087c6 GY	160	msg_queue = &__get_cpu_var(ipi_msg_queue);
6b3087c6	161
73a40064 YL	162	spin_lock_irqsave(&msg_queue->lock, flags);
	163
	164	while (msg_queue->count) {
	165	msg = &msg_queue->ipi_message[msg_queue->head];
6b3087c6	166	switch (msg->type) {
6b3087c6	167	case BFIN_IPI_CALL_FUNC:
73a40064	168	spin_unlock_irqrestore(&msg_queue->lock, flags);
6b3087c6	169	ipi_call_function(cpu, msg);
73a40064	170	spin_lock_irqsave(&msg_queue->lock, flags);
6b3087c6 GY	171	break;
6b3087c6 GY	172	case BFIN_IPI_CPU_STOP:
73a40064	173	spin_unlock_irqrestore(&msg_queue->lock, flags);
6b3087c6	174	ipi_cpu_stop(cpu);
73a40064	175	spin_lock_irqsave(&msg_queue->lock, flags);
6b3087c6 GY	176	break;
6b3087c6 GY	177	default:
db52ecc2 JP	178	printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
db52ecc2 JP	179	cpu, msg->type);
6b3087c6 GY	180	break;
6b3087c6 GY	181	}
73a40064 YL	182	msg_queue->head++;
	183	msg_queue->head %= BFIN_IPI_MSGQ_LEN;
	184	msg_queue->count--;
6b3087c6	185	}
73a40064	186	spin_unlock_irqrestore(&msg_queue->lock, flags);
6b3087c6 GY	187	return IRQ_HANDLED;
	188	}
	189
	190	static void ipi_queue_init(void)
	191	{
	192	unsigned int cpu;
	193	struct ipi_message_queue *msg_queue;
	194	for_each_possible_cpu(cpu) {
	195	msg_queue = &per_cpu(ipi_msg_queue, cpu);
6b3087c6 GY	196	spin_lock_init(&msg_queue->lock);
6b3087c6 GY	197	msg_queue->count = 0;
73a40064	198	msg_queue->head = 0;
6b3087c6 GY	199	}
	200	}
	201
73a40064 YL	202	static inline void smp_send_message(cpumask_t callmap, unsigned long type,
73a40064 YL	203	void (func) (void info), void *info, int wait)
6b3087c6 GY	204	{
6b3087c6 GY	205	unsigned int cpu;
6b3087c6 GY	206	struct ipi_message_queue *msg_queue;
6b3087c6 GY	207	struct ipi_message *msg;
73a40064 YL	208	unsigned long flags, next_msg;
73a40064 YL	209	cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
6b3087c6 GY	210
	211	for_each_cpu_mask(cpu, callmap) {
	212	msg_queue = &per_cpu(ipi_msg_queue, cpu);
	213	spin_lock_irqsave(&msg_queue->lock, flags);
73a40064 YL	214	if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
	215	next_msg = (msg_queue->head + msg_queue->count)
	216	% BFIN_IPI_MSGQ_LEN;
	217	msg = &msg_queue->ipi_message[next_msg];
	218	msg->type = type;
	219	if (type == BFIN_IPI_CALL_FUNC) {
	220	msg->call_struct.func = func;
	221	msg->call_struct.info = info;
	222	msg->call_struct.wait = wait;
	223	msg->call_struct.waitmask = &waitmask;
	224	}
	225	msg_queue->count++;
	226	} else
	227	panic("IPI message queue overflow\n");
6b3087c6	228	spin_unlock_irqrestore(&msg_queue->lock, flags);
73a40064	229	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
6b3087c6	230	}
73a40064	231
6b3087c6	232	if (wait) {
73a40064	233	while (!cpus_empty(waitmask))
6b3087c6	234	blackfin_dcache_invalidate_range(
73a40064 YL	235	(unsigned long)(&waitmask),
73a40064 YL	236	(unsigned long)(&waitmask));
c9784ebb YL	237	#ifdef __ARCH_SYNC_CORE_DCACHE
	238	/*
	239	* Invalidate D cache in case shared data was changed by
	240	* other processors to ensure cache coherence.
	241	*/
	242	resync_core_dcache();
	243	#endif
6b3087c6	244	}
73a40064 YL	245	}
	246
	247	int smp_call_function(void (func)(void info), void *info, int wait)
	248	{
	249	cpumask_t callmap;
	250
567ebfc9	251	preempt_disable();
73a40064 YL	252	callmap = cpu_online_map;
73a40064 YL	253	cpu_clear(smp_processor_id(), callmap);
567ebfc9 SZ	254	if (!cpus_empty(callmap))
567ebfc9 SZ	255	smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
73a40064	256
567ebfc9	257	preempt_enable();
73a40064	258
6b3087c6 GY	259	return 0;
	260	}
	261	EXPORT_SYMBOL_GPL(smp_call_function);
	262
	263	int smp_call_function_single(int cpuid, void (func) (void info), void *info,
	264	int wait)
	265	{
	266	unsigned int cpu = cpuid;
	267	cpumask_t callmap;
6b3087c6 GY	268
	269	if (cpu_is_offline(cpu))
	270	return 0;
	271	cpus_clear(callmap);
	272	cpu_set(cpu, callmap);
	273
73a40064	274	smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
6b3087c6	275
6b3087c6 GY	276	return 0;
	277	}
	278	EXPORT_SYMBOL_GPL(smp_call_function_single);
	279
	280	void smp_send_reschedule(int cpu)
	281	{
73a40064	282	/* simply trigger an ipi */
6b3087c6 GY	283	if (cpu_is_offline(cpu))
6b3087c6 GY	284	return;
73a40064	285	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
6b3087c6 GY	286
	287	return;
	288	}
	289
	290	void smp_send_stop(void)
	291	{
6b3087c6	292	cpumask_t callmap;
6b3087c6	293
567ebfc9	294	preempt_disable();
6b3087c6 GY	295	callmap = cpu_online_map;
6b3087c6 GY	296	cpu_clear(smp_processor_id(), callmap);
567ebfc9 SZ	297	if (!cpus_empty(callmap))
567ebfc9 SZ	298	smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
6b3087c6	299
567ebfc9	300	preempt_enable();
6b3087c6	301
6b3087c6 GY	302	return;
	303	}
	304
	305	int __cpuinit __cpu_up(unsigned int cpu)
	306	{
6b3087c6	307	int ret;
0b39db28 GY	308	static struct task_struct *idle;
	309
	310	if (idle)
	311	free_task(idle);
6b3087c6 GY	312
	313	idle = fork_idle(cpu);
	314	if (IS_ERR(idle)) {
	315	printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
	316	return PTR_ERR(idle);
	317	}
	318
	319	secondary_stack = task_stack_page(idle) + THREAD_SIZE;
6b3087c6 GY	320
	321	ret = platform_boot_secondary(cpu, idle);
	322
6b3087c6 GY	323	secondary_stack = NULL;
	324
	325	return ret;
	326	}
	327
	328	static void __cpuinit setup_secondary(unsigned int cpu)
	329	{
6b3087c6 GY	330	unsigned long ilat;
	331
	332	bfin_write_IMASK(0);
	333	CSYNC();
	334	ilat = bfin_read_ILAT();
	335	CSYNC();
	336	bfin_write_ILAT(ilat);
	337	CSYNC();
	338
6b3087c6 GY	339	/* Enable interrupt levels IVG7-15. IARs have been already
6b3087c6 GY	340	* programmed by the boot CPU. */
40059784	341	bfin_irq_flags \|= IMASK_IVG15 \|
6b3087c6 GY	342	IMASK_IVG14 \| IMASK_IVG13 \| IMASK_IVG12 \| IMASK_IVG11 \|
6b3087c6 GY	343	IMASK_IVG10 \| IMASK_IVG9 \| IMASK_IVG8 \| IMASK_IVG7 \| IMASK_IVGHW;
6b3087c6 GY	344	}
	345
	346	void __cpuinit secondary_start_kernel(void)
	347	{
	348	unsigned int cpu = smp_processor_id();
	349	struct mm_struct *mm = &init_mm;
	350
	351	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
	352	printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
	353	#ifdef CONFIG_DEBUG_DOUBLEFAULT
	354	printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
	355	(int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
	356	printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
	357	printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
	358	#endif
	359	printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
	360	init_retx_coreb);
	361	}
	362
	363	/*
	364	* We want the D-cache to be enabled early, in case the atomic
	365	* support code emulates cache coherence (see
	366	* __ARCH_SYNC_CORE_DCACHE).
	367	*/
	368	init_exception_vectors();
	369
6b3087c6 GY	370	local_irq_disable();
	371
	372	/* Attach the new idle task to the global mm. */
	373	atomic_inc(&mm->mm_users);
	374	atomic_inc(&mm->mm_count);
	375	current->active_mm = mm;
6b3087c6 GY	376
	377	preempt_disable();
	378
	379	setup_secondary(cpu);
	380
578d36f5 YL	381	platform_secondary_init(cpu);
578d36f5 YL	382
0d152c27 YL	383	/* setup local core timer */
	384	bfin_local_timer_setup();
	385
6b3087c6 GY	386	local_irq_enable();
6b3087c6 GY	387
ab61d2ac	388	bfin_setup_caches(cpu);
ab61d2ac	389
578d36f5 YL	390	/*
	391	* Calibrate loops per jiffy value.
	392	* IRQs need to be enabled here - D-cache can be invalidated
	393	* in timer irq handler, so core B can read correct jiffies.
	394	*/
	395	calibrate_delay();
6b3087c6 GY	396
	397	cpu_idle();
	398	}
	399
	400	void __init smp_prepare_boot_cpu(void)
	401	{
	402	}
	403
	404	void __init smp_prepare_cpus(unsigned int max_cpus)
	405	{
	406	platform_prepare_cpus(max_cpus);
	407	ipi_queue_init();
73a40064 YL	408	platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
73a40064 YL	409	platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
6b3087c6 GY	410	}
	411
	412	void __init smp_cpus_done(unsigned int max_cpus)
	413	{
	414	unsigned long bogosum = 0;
	415	unsigned int cpu;
	416
	417	for_each_online_cpu(cpu)
c70c754f	418	bogosum += loops_per_jiffy;
6b3087c6 GY	419
	420	printk(KERN_INFO "SMP: Total of %d processors activated "
	421	"(%lu.%02lu BogoMIPS).\n",
	422	num_online_cpus(),
	423	bogosum / (500000/HZ),
	424	(bogosum / (5000/HZ)) % 100);
	425	}
	426
	427	void smp_icache_flush_range_others(unsigned long start, unsigned long end)
	428	{
	429	smp_flush_data.start = start;
	430	smp_flush_data.end = end;
	431
0bf3d933	432	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
6b3087c6 GY	433	printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
	434	}
	435	EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
	436
47e9dedb	437	#ifdef __ARCH_SYNC_CORE_ICACHE
718340f6	438	unsigned long icache_invld_count[NR_CPUS];
47e9dedb SZ	439	void resync_core_icache(void)
	440	{
	441	unsigned int cpu = get_cpu();
	442	blackfin_invalidate_entire_icache();
718340f6	443	icache_invld_count[cpu]++;
47e9dedb SZ	444	put_cpu();
	445	}
	446	EXPORT_SYMBOL(resync_core_icache);
	447	#endif
	448
6b3087c6	449	#ifdef __ARCH_SYNC_CORE_DCACHE
718340f6	450	unsigned long dcache_invld_count[NR_CPUS];
6b3087c6 GY	451	unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
	452
	453	void resync_core_dcache(void)
	454	{
	455	unsigned int cpu = get_cpu();
	456	blackfin_invalidate_entire_dcache();
718340f6	457	dcache_invld_count[cpu]++;
6b3087c6 GY	458	put_cpu();
	459	}
	460	EXPORT_SYMBOL(resync_core_dcache);
	461	#endif
0b39db28 GY	462
	463	#ifdef CONFIG_HOTPLUG_CPU
	464	int __cpuexit __cpu_disable(void)
	465	{
	466	unsigned int cpu = smp_processor_id();
	467
	468	if (cpu == 0)
	469	return -EPERM;
	470
	471	set_cpu_online(cpu, false);
	472	return 0;
	473	}
	474
	475	static DECLARE_COMPLETION(cpu_killed);
	476
	477	int __cpuexit __cpu_die(unsigned int cpu)
	478	{
	479	return wait_for_completion_timeout(&cpu_killed, 5000);
	480	}
	481
	482	void cpu_die(void)
	483	{
	484	complete(&cpu_killed);
	485
	486	atomic_dec(&init_mm.mm_users);
	487	atomic_dec(&init_mm.mm_count);
	488
	489	local_irq_disable();
	490	platform_cpu_die();
	491	}
	492	#endif