[deliverable/linux.git] / arch / blackfin / mach-common / smp.c

/*
 * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
 *
 * Copyright 2007-2009 Analog Devices Inc.
 *                         Philippe Gerum <rpm@xenomai.org>
 *
 * Licensed under the GPL-2.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/cache.h>
#include <linux/profile.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/cpu.h>
#include <linux/smp.h>
#include <linux/cpumask.h>
#include <linux/seq_file.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/cpu.h>
#include <asm/time.h>
#include <linux/err.h>

/*
 * Anomaly notes:
 * 05000120 - we always define corelock as 32-bit integer in L2
 */
struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));

#ifdef CONFIG_ICACHE_FLUSH_L1
unsigned long blackfin_iflush_l1_entry[NR_CPUS];
#endif

void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
	*init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
	*init_saved_dcplb_fault_addr_coreb;

#define BFIN_IPI_RESCHEDULE   0
#define BFIN_IPI_CALL_FUNC    1
#define BFIN_IPI_CPU_STOP     2

struct blackfin_flush_data {
	unsigned long start;
	unsigned long end;
};

void *secondary_stack;


struct smp_call_struct {
	void (*func)(void *info);
	void *info;
	int wait;
	cpumask_t *waitmask;
};

static struct blackfin_flush_data smp_flush_data;

static DEFINE_SPINLOCK(stop_lock);

struct ipi_message {
	unsigned long type;
	struct smp_call_struct call_struct;
};

/* A magic number - stress test shows this is safe for common cases */
#define BFIN_IPI_MSGQ_LEN 5

/* Simple FIFO buffer, overflow leads to panic */
struct ipi_message_queue {
	spinlock_t lock;
	unsigned long count;
	unsigned long head; /* head of the queue */
	struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
};

static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);

static void ipi_cpu_stop(unsigned int cpu)
{
	spin_lock(&stop_lock);
	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	dump_stack();
	spin_unlock(&stop_lock);

	cpu_clear(cpu, cpu_online_map);

	local_irq_disable();

	while (1)
		SSYNC();
}

static void ipi_flush_icache(void *info)
{
	struct blackfin_flush_data *fdata = info;

	/* Invalidate the memory holding the bounds of the flushed region. */
	blackfin_dcache_invalidate_range((unsigned long)fdata,
					 (unsigned long)fdata + sizeof(*fdata));

	/* Make sure all write buffers in the data side of the core
	 * are flushed before trying to invalidate the icache.  This
	 * needs to be after the data flush and before the icache
	 * flush so that the SSYNC does the right thing in preventing
	 * the instruction prefetcher from hitting things in cached
	 * memory at the wrong time -- it runs much further ahead than
	 * the pipeline.
	 */
	SSYNC();

	/* ipi_flaush_icache is invoked by generic flush_icache_range,
	 * so call blackfin arch icache flush directly here.
	 */
	blackfin_icache_flush_range(fdata->start, fdata->end);
}

static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
{
	int wait;
	void (*func)(void *info);
	void *info;
	func = msg->call_struct.func;
	info = msg->call_struct.info;
	wait = msg->call_struct.wait;
	func(info);
	if (wait) {
#ifdef __ARCH_SYNC_CORE_DCACHE
		/*
		 * 'wait' usually means synchronization between CPUs.
		 * Invalidate D cache in case shared data was changed
		 * by func() to ensure cache coherence.
		 */
		resync_core_dcache();
#endif
		cpu_clear(cpu, *msg->call_struct.waitmask);
	}
}

/* Use IRQ_SUPPLE_0 to request reschedule.
 * When returning from interrupt to user space,
 * there is chance to reschedule */
static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
{
	unsigned int cpu = smp_processor_id();

	platform_clear_ipi(cpu, IRQ_SUPPLE_0);
	return IRQ_HANDLED;
}

static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
{
	struct ipi_message *msg;
	struct ipi_message_queue *msg_queue;
	unsigned int cpu = smp_processor_id();
	unsigned long flags;

	platform_clear_ipi(cpu, IRQ_SUPPLE_1);

	msg_queue = &__get_cpu_var(ipi_msg_queue);

	spin_lock_irqsave(&msg_queue->lock, flags);

	while (msg_queue->count) {
		msg = &msg_queue->ipi_message[msg_queue->head];
		switch (msg->type) {
		case BFIN_IPI_RESCHEDULE:
			scheduler_ipi();
			break;
		case BFIN_IPI_CALL_FUNC:
			spin_unlock_irqrestore(&msg_queue->lock, flags);
			ipi_call_function(cpu, msg);
			spin_lock_irqsave(&msg_queue->lock, flags);
			break;
		case BFIN_IPI_CPU_STOP:
			spin_unlock_irqrestore(&msg_queue->lock, flags);
			ipi_cpu_stop(cpu);
			spin_lock_irqsave(&msg_queue->lock, flags);
			break;
		default:
			printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
			       cpu, msg->type);
			break;
		}
		msg_queue->head++;
		msg_queue->head %= BFIN_IPI_MSGQ_LEN;
		msg_queue->count--;
	}
	spin_unlock_irqrestore(&msg_queue->lock, flags);
	return IRQ_HANDLED;
}

static void ipi_queue_init(void)
{
	unsigned int cpu;
	struct ipi_message_queue *msg_queue;
	for_each_possible_cpu(cpu) {
		msg_queue = &per_cpu(ipi_msg_queue, cpu);
		spin_lock_init(&msg_queue->lock);
		msg_queue->count = 0;
		msg_queue->head = 0;
	}
}

static inline void smp_send_message(cpumask_t callmap, unsigned long type,
					void (*func) (void *info), void *info, int wait)
{
	unsigned int cpu;
	struct ipi_message_queue *msg_queue;
	struct ipi_message *msg;
	unsigned long flags, next_msg;
	cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */

	for_each_cpu_mask(cpu, callmap) {
		msg_queue = &per_cpu(ipi_msg_queue, cpu);
		spin_lock_irqsave(&msg_queue->lock, flags);
		if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
			next_msg = (msg_queue->head + msg_queue->count)
					% BFIN_IPI_MSGQ_LEN;
			msg = &msg_queue->ipi_message[next_msg];
			msg->type = type;
			if (type == BFIN_IPI_CALL_FUNC) {
				msg->call_struct.func = func;
				msg->call_struct.info = info;
				msg->call_struct.wait = wait;
				msg->call_struct.waitmask = &waitmask;
			}
			msg_queue->count++;
		} else
			panic("IPI message queue overflow\n");
		spin_unlock_irqrestore(&msg_queue->lock, flags);
		platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
	}

	if (wait) {
		while (!cpus_empty(waitmask))
			blackfin_dcache_invalidate_range(
				(unsigned long)(&waitmask),
				(unsigned long)(&waitmask));
#ifdef __ARCH_SYNC_CORE_DCACHE
		/*
		 * Invalidate D cache in case shared data was changed by
		 * other processors to ensure cache coherence.
		 */
		resync_core_dcache();
#endif
	}
}

int smp_call_function(void (*func)(void *info), void *info, int wait)
{
	cpumask_t callmap;

	preempt_disable();
	callmap = cpu_online_map;
	cpu_clear(smp_processor_id(), callmap);
	if (!cpus_empty(callmap))
		smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);

	preempt_enable();

	return 0;
}
EXPORT_SYMBOL_GPL(smp_call_function);

int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
				int wait)
{
	unsigned int cpu = cpuid;
	cpumask_t callmap;

	if (cpu_is_offline(cpu))
		return 0;
	cpus_clear(callmap);
	cpu_set(cpu, callmap);

	smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);

	return 0;
}
EXPORT_SYMBOL_GPL(smp_call_function_single);

void smp_send_reschedule(int cpu)
{
	/* simply trigger an ipi */
	if (cpu_is_offline(cpu))
		return;
	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);

	return;
}

void smp_send_stop(void)
{
	cpumask_t callmap;

	preempt_disable();
	callmap = cpu_online_map;
	cpu_clear(smp_processor_id(), callmap);
	if (!cpus_empty(callmap))
		smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);

	preempt_enable();

	return;
}

int __cpuinit __cpu_up(unsigned int cpu)
{
	int ret;
	static struct task_struct *idle;

	if (idle)
		free_task(idle);

	idle = fork_idle(cpu);
	if (IS_ERR(idle)) {
		printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
		return PTR_ERR(idle);
	}

	secondary_stack = task_stack_page(idle) + THREAD_SIZE;

	ret = platform_boot_secondary(cpu, idle);

	secondary_stack = NULL;

	return ret;
}

static void __cpuinit setup_secondary(unsigned int cpu)
{
	unsigned long ilat;

	bfin_write_IMASK(0);
	CSYNC();
	ilat = bfin_read_ILAT();
	CSYNC();
	bfin_write_ILAT(ilat);
	CSYNC();

	/* Enable interrupt levels IVG7-15. IARs have been already
	 * programmed by the boot CPU.  */
	bfin_irq_flags |= IMASK_IVG15 |
	    IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
	    IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
}

void __cpuinit secondary_start_kernel(void)
{
	unsigned int cpu = smp_processor_id();
	struct mm_struct *mm = &init_mm;

	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
		printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
#ifdef CONFIG_DEBUG_DOUBLEFAULT
		printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
			(int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
		printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
		printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
#endif
		printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
			init_retx_coreb);
	}

	/*
	 * We want the D-cache to be enabled early, in case the atomic
	 * support code emulates cache coherence (see
	 * __ARCH_SYNC_CORE_DCACHE).
	 */
	init_exception_vectors();

	local_irq_disable();

	/* Attach the new idle task to the global mm. */
	atomic_inc(&mm->mm_users);
	atomic_inc(&mm->mm_count);
	current->active_mm = mm;

	preempt_disable();

	setup_secondary(cpu);

	platform_secondary_init(cpu);

	/* setup local core timer */
	bfin_local_timer_setup();

	local_irq_enable();

	bfin_setup_caches(cpu);

	/*
	 * Calibrate loops per jiffy value.
	 * IRQs need to be enabled here - D-cache can be invalidated
	 * in timer irq handler, so core B can read correct jiffies.
	 */
	calibrate_delay();

	cpu_idle();
}

void __init smp_prepare_boot_cpu(void)
{
}

void __init smp_prepare_cpus(unsigned int max_cpus)
{
	platform_prepare_cpus(max_cpus);
	ipi_queue_init();
	platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
	platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
}

void __init smp_cpus_done(unsigned int max_cpus)
{
	unsigned long bogosum = 0;
	unsigned int cpu;

	for_each_online_cpu(cpu)
		bogosum += loops_per_jiffy;

	printk(KERN_INFO "SMP: Total of %d processors activated "
	       "(%lu.%02lu BogoMIPS).\n",
	       num_online_cpus(),
	       bogosum / (500000/HZ),
	       (bogosum / (5000/HZ)) % 100);
}

void smp_icache_flush_range_others(unsigned long start, unsigned long end)
{
	smp_flush_data.start = start;
	smp_flush_data.end = end;

	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
		printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
}
EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);

#ifdef __ARCH_SYNC_CORE_ICACHE
unsigned long icache_invld_count[NR_CPUS];
void resync_core_icache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_icache();
	icache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_icache);
#endif

#ifdef __ARCH_SYNC_CORE_DCACHE
unsigned long dcache_invld_count[NR_CPUS];
unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));

void resync_core_dcache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_dcache();
	dcache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_dcache);
#endif

#ifdef CONFIG_HOTPLUG_CPU
int __cpuexit __cpu_disable(void)
{
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EPERM;

	set_cpu_online(cpu, false);
	return 0;
}

static DECLARE_COMPLETION(cpu_killed);

int __cpuexit __cpu_die(unsigned int cpu)
{
	return wait_for_completion_timeout(&cpu_killed, 5000);
}

void cpu_die(void)
{
	complete(&cpu_killed);

	atomic_dec(&init_mm.mm_users);
	atomic_dec(&init_mm.mm_count);

	local_irq_disable();
	platform_cpu_die();
}
#endif
Commit	Line	Data
6b3087c6	1	/*
96f1050d	2	* IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
6b3087c6	3	*
96f1050d RG	4	* Copyright 2007-2009 Analog Devices Inc.
96f1050d RG	5	* Philippe Gerum <rpm@xenomai.org>
6b3087c6	6	*
96f1050d	7	* Licensed under the GPL-2.
6b3087c6 GY	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/sched.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/cache.h>
	17	#include <linux/profile.h>
	18	#include <linux/errno.h>
	19	#include <linux/mm.h>
	20	#include <linux/cpu.h>
	21	#include <linux/smp.h>
9c199b59	22	#include <linux/cpumask.h>
6b3087c6 GY	23	#include <linux/seq_file.h>
6b3087c6 GY	24	#include <linux/irq.h>
5a0e3ad6	25	#include <linux/slab.h>
6b3087c6 GY	26	#include <asm/atomic.h>
	27	#include <asm/cacheflush.h>
	28	#include <asm/mmu_context.h>
	29	#include <asm/pgtable.h>
	30	#include <asm/pgalloc.h>
	31	#include <asm/processor.h>
	32	#include <asm/ptrace.h>
	33	#include <asm/cpu.h>
1fa9be72	34	#include <asm/time.h>
6b3087c6 GY	35	#include <linux/err.h>
6b3087c6 GY	36
555487bb GY	37	/*
	38	* Anomaly notes:
	39	* 05000120 - we always define corelock as 32-bit integer in L2
	40	*/
6b3087c6 GY	41	struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
6b3087c6 GY	42
c6345ab1 SZ	43	#ifdef CONFIG_ICACHE_FLUSH_L1
	44	unsigned long blackfin_iflush_l1_entry[NR_CPUS];
	45	#endif
	46
6b3087c6 GY	47	void __cpuinitdata init_retx_coreb, init_saved_retx_coreb,
	48	init_saved_seqstat_coreb, init_saved_icplb_fault_addr_coreb,
	49	*init_saved_dcplb_fault_addr_coreb;
	50
6b3087c6 GY	51	#define BFIN_IPI_RESCHEDULE 0
	52	#define BFIN_IPI_CALL_FUNC 1
	53	#define BFIN_IPI_CPU_STOP 2
	54
	55	struct blackfin_flush_data {
	56	unsigned long start;
	57	unsigned long end;
	58	};
	59
	60	void *secondary_stack;
	61
	62
	63	struct smp_call_struct {
	64	void (func)(void info);
	65	void *info;
	66	int wait;
73a40064	67	cpumask_t *waitmask;
6b3087c6 GY	68	};
	69
	70	static struct blackfin_flush_data smp_flush_data;
	71
	72	static DEFINE_SPINLOCK(stop_lock);
	73
	74	struct ipi_message {
6b3087c6 GY	75	unsigned long type;
	76	struct smp_call_struct call_struct;
	77	};
	78
73a40064 YL	79	/* A magic number - stress test shows this is safe for common cases */
	80	#define BFIN_IPI_MSGQ_LEN 5
	81
	82	/* Simple FIFO buffer, overflow leads to panic */
6b3087c6	83	struct ipi_message_queue {
6b3087c6 GY	84	spinlock_t lock;
6b3087c6 GY	85	unsigned long count;
73a40064 YL	86	unsigned long head; /* head of the queue */
73a40064 YL	87	struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
6b3087c6 GY	88	};
	89
	90	static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
	91
	92	static void ipi_cpu_stop(unsigned int cpu)
	93	{
	94	spin_lock(&stop_lock);
	95	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	96	dump_stack();
	97	spin_unlock(&stop_lock);
	98
	99	cpu_clear(cpu, cpu_online_map);
	100
	101	local_irq_disable();
	102
	103	while (1)
	104	SSYNC();
	105	}
	106
	107	static void ipi_flush_icache(void *info)
	108	{
	109	struct blackfin_flush_data *fdata = info;
	110
	111	/* Invalidate the memory holding the bounds of the flushed region. */
8d50de9e SZ	112	blackfin_dcache_invalidate_range((unsigned long)fdata,
	113	(unsigned long)fdata + sizeof(*fdata));
	114
	115	/* Make sure all write buffers in the data side of the core
	116	* are flushed before trying to invalidate the icache. This
	117	* needs to be after the data flush and before the icache
	118	* flush so that the SSYNC does the right thing in preventing
	119	* the instruction prefetcher from hitting things in cached
	120	* memory at the wrong time -- it runs much further ahead than
	121	* the pipeline.
	122	*/
	123	SSYNC();
	124
	125	/* ipi_flaush_icache is invoked by generic flush_icache_range,
	126	* so call blackfin arch icache flush directly here.
	127	*/
	128	blackfin_icache_flush_range(fdata->start, fdata->end);
6b3087c6 GY	129	}
	130
	131	static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
	132	{
	133	int wait;
	134	void (func)(void info);
	135	void *info;
	136	func = msg->call_struct.func;
	137	info = msg->call_struct.info;
	138	wait = msg->call_struct.wait;
6b3087c6	139	func(info);
c9784ebb YL	140	if (wait) {
	141	#ifdef __ARCH_SYNC_CORE_DCACHE
	142	/*
	143	* 'wait' usually means synchronization between CPUs.
	144	* Invalidate D cache in case shared data was changed
	145	* by func() to ensure cache coherence.
	146	*/
	147	resync_core_dcache();
	148	#endif
73a40064 YL	149	cpu_clear(cpu, *msg->call_struct.waitmask);
73a40064 YL	150	}
6b3087c6 GY	151	}
6b3087c6 GY	152
73a40064 YL	153	/* Use IRQ_SUPPLE_0 to request reschedule.
	154	* When returning from interrupt to user space,
	155	* there is chance to reschedule */
	156	static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
	157	{
	158	unsigned int cpu = smp_processor_id();
	159
	160	platform_clear_ipi(cpu, IRQ_SUPPLE_0);
	161	return IRQ_HANDLED;
	162	}
	163
	164	static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
6b3087c6	165	{
86f2008b	166	struct ipi_message *msg;
6b3087c6 GY	167	struct ipi_message_queue *msg_queue;
6b3087c6 GY	168	unsigned int cpu = smp_processor_id();
73a40064	169	unsigned long flags;
6b3087c6	170
73a40064	171	platform_clear_ipi(cpu, IRQ_SUPPLE_1);
6b3087c6 GY	172
6b3087c6 GY	173	msg_queue = &__get_cpu_var(ipi_msg_queue);
6b3087c6	174
73a40064 YL	175	spin_lock_irqsave(&msg_queue->lock, flags);
	176
	177	while (msg_queue->count) {
	178	msg = &msg_queue->ipi_message[msg_queue->head];
6b3087c6	179	switch (msg->type) {
184748cc PZ	180	case BFIN_IPI_RESCHEDULE:
	181	scheduler_ipi();
	182	break;
6b3087c6	183	case BFIN_IPI_CALL_FUNC:
73a40064	184	spin_unlock_irqrestore(&msg_queue->lock, flags);
6b3087c6	185	ipi_call_function(cpu, msg);
73a40064	186	spin_lock_irqsave(&msg_queue->lock, flags);
6b3087c6 GY	187	break;
6b3087c6 GY	188	case BFIN_IPI_CPU_STOP:
73a40064	189	spin_unlock_irqrestore(&msg_queue->lock, flags);
6b3087c6	190	ipi_cpu_stop(cpu);
73a40064	191	spin_lock_irqsave(&msg_queue->lock, flags);
6b3087c6 GY	192	break;
6b3087c6 GY	193	default:
db52ecc2 JP	194	printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
db52ecc2 JP	195	cpu, msg->type);
6b3087c6 GY	196	break;
6b3087c6 GY	197	}
73a40064 YL	198	msg_queue->head++;
	199	msg_queue->head %= BFIN_IPI_MSGQ_LEN;
	200	msg_queue->count--;
6b3087c6	201	}
73a40064	202	spin_unlock_irqrestore(&msg_queue->lock, flags);
6b3087c6 GY	203	return IRQ_HANDLED;
	204	}
	205
	206	static void ipi_queue_init(void)
	207	{
	208	unsigned int cpu;
	209	struct ipi_message_queue *msg_queue;
	210	for_each_possible_cpu(cpu) {
	211	msg_queue = &per_cpu(ipi_msg_queue, cpu);
6b3087c6 GY	212	spin_lock_init(&msg_queue->lock);
6b3087c6 GY	213	msg_queue->count = 0;
73a40064	214	msg_queue->head = 0;
6b3087c6 GY	215	}
	216	}
	217
73a40064 YL	218	static inline void smp_send_message(cpumask_t callmap, unsigned long type,
73a40064 YL	219	void (func) (void info), void *info, int wait)
6b3087c6 GY	220	{
6b3087c6 GY	221	unsigned int cpu;
6b3087c6 GY	222	struct ipi_message_queue *msg_queue;
6b3087c6 GY	223	struct ipi_message *msg;
73a40064 YL	224	unsigned long flags, next_msg;
73a40064 YL	225	cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
6b3087c6 GY	226
	227	for_each_cpu_mask(cpu, callmap) {
	228	msg_queue = &per_cpu(ipi_msg_queue, cpu);
	229	spin_lock_irqsave(&msg_queue->lock, flags);
73a40064 YL	230	if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
	231	next_msg = (msg_queue->head + msg_queue->count)
	232	% BFIN_IPI_MSGQ_LEN;
	233	msg = &msg_queue->ipi_message[next_msg];
	234	msg->type = type;
	235	if (type == BFIN_IPI_CALL_FUNC) {
	236	msg->call_struct.func = func;
	237	msg->call_struct.info = info;
	238	msg->call_struct.wait = wait;
	239	msg->call_struct.waitmask = &waitmask;
	240	}
	241	msg_queue->count++;
	242	} else
	243	panic("IPI message queue overflow\n");
6b3087c6	244	spin_unlock_irqrestore(&msg_queue->lock, flags);
73a40064	245	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
6b3087c6	246	}
73a40064	247
6b3087c6	248	if (wait) {
73a40064	249	while (!cpus_empty(waitmask))
6b3087c6	250	blackfin_dcache_invalidate_range(
73a40064 YL	251	(unsigned long)(&waitmask),
73a40064 YL	252	(unsigned long)(&waitmask));
c9784ebb YL	253	#ifdef __ARCH_SYNC_CORE_DCACHE
	254	/*
	255	* Invalidate D cache in case shared data was changed by
	256	* other processors to ensure cache coherence.
	257	*/
	258	resync_core_dcache();
	259	#endif
6b3087c6	260	}
73a40064 YL	261	}
	262
	263	int smp_call_function(void (func)(void info), void *info, int wait)
	264	{
	265	cpumask_t callmap;
	266
567ebfc9	267	preempt_disable();
73a40064 YL	268	callmap = cpu_online_map;
73a40064 YL	269	cpu_clear(smp_processor_id(), callmap);
567ebfc9 SZ	270	if (!cpus_empty(callmap))
567ebfc9 SZ	271	smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
73a40064	272
567ebfc9	273	preempt_enable();
73a40064	274
6b3087c6 GY	275	return 0;
	276	}
	277	EXPORT_SYMBOL_GPL(smp_call_function);
	278
	279	int smp_call_function_single(int cpuid, void (func) (void info), void *info,
	280	int wait)
	281	{
	282	unsigned int cpu = cpuid;
	283	cpumask_t callmap;
6b3087c6 GY	284
	285	if (cpu_is_offline(cpu))
	286	return 0;
	287	cpus_clear(callmap);
	288	cpu_set(cpu, callmap);
	289
73a40064	290	smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
6b3087c6	291
6b3087c6 GY	292	return 0;
	293	}
	294	EXPORT_SYMBOL_GPL(smp_call_function_single);
	295
	296	void smp_send_reschedule(int cpu)
	297	{
73a40064	298	/* simply trigger an ipi */
6b3087c6 GY	299	if (cpu_is_offline(cpu))
6b3087c6 GY	300	return;
73a40064	301	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
6b3087c6 GY	302
	303	return;
	304	}
	305
	306	void smp_send_stop(void)
	307	{
6b3087c6	308	cpumask_t callmap;
6b3087c6	309
567ebfc9	310	preempt_disable();
6b3087c6 GY	311	callmap = cpu_online_map;
6b3087c6 GY	312	cpu_clear(smp_processor_id(), callmap);
567ebfc9 SZ	313	if (!cpus_empty(callmap))
567ebfc9 SZ	314	smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
6b3087c6	315
567ebfc9	316	preempt_enable();
6b3087c6	317
6b3087c6 GY	318	return;
	319	}
	320
	321	int __cpuinit __cpu_up(unsigned int cpu)
	322	{
6b3087c6	323	int ret;
0b39db28 GY	324	static struct task_struct *idle;
	325
	326	if (idle)
	327	free_task(idle);
6b3087c6 GY	328
	329	idle = fork_idle(cpu);
	330	if (IS_ERR(idle)) {
	331	printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
	332	return PTR_ERR(idle);
	333	}
	334
	335	secondary_stack = task_stack_page(idle) + THREAD_SIZE;
6b3087c6 GY	336
	337	ret = platform_boot_secondary(cpu, idle);
	338
6b3087c6 GY	339	secondary_stack = NULL;
	340
	341	return ret;
	342	}
	343
	344	static void __cpuinit setup_secondary(unsigned int cpu)
	345	{
6b3087c6 GY	346	unsigned long ilat;
	347
	348	bfin_write_IMASK(0);
	349	CSYNC();
	350	ilat = bfin_read_ILAT();
	351	CSYNC();
	352	bfin_write_ILAT(ilat);
	353	CSYNC();
	354
6b3087c6 GY	355	/* Enable interrupt levels IVG7-15. IARs have been already
6b3087c6 GY	356	* programmed by the boot CPU. */
40059784	357	bfin_irq_flags \|= IMASK_IVG15 \|
6b3087c6 GY	358	IMASK_IVG14 \| IMASK_IVG13 \| IMASK_IVG12 \| IMASK_IVG11 \|
6b3087c6 GY	359	IMASK_IVG10 \| IMASK_IVG9 \| IMASK_IVG8 \| IMASK_IVG7 \| IMASK_IVGHW;
6b3087c6 GY	360	}
	361
	362	void __cpuinit secondary_start_kernel(void)
	363	{
	364	unsigned int cpu = smp_processor_id();
	365	struct mm_struct *mm = &init_mm;
	366
	367	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
	368	printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
	369	#ifdef CONFIG_DEBUG_DOUBLEFAULT
	370	printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
	371	(int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
	372	printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
	373	printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
	374	#endif
	375	printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
	376	init_retx_coreb);
	377	}
	378
	379	/*
	380	* We want the D-cache to be enabled early, in case the atomic
	381	* support code emulates cache coherence (see
	382	* __ARCH_SYNC_CORE_DCACHE).
	383	*/
	384	init_exception_vectors();
	385
6b3087c6 GY	386	local_irq_disable();
	387
	388	/* Attach the new idle task to the global mm. */
	389	atomic_inc(&mm->mm_users);
	390	atomic_inc(&mm->mm_count);
	391	current->active_mm = mm;
6b3087c6 GY	392
	393	preempt_disable();
	394
	395	setup_secondary(cpu);
	396
578d36f5 YL	397	platform_secondary_init(cpu);
578d36f5 YL	398
0d152c27 YL	399	/* setup local core timer */
	400	bfin_local_timer_setup();
	401
6b3087c6 GY	402	local_irq_enable();
6b3087c6 GY	403
ab61d2ac	404	bfin_setup_caches(cpu);
ab61d2ac	405
578d36f5 YL	406	/*
	407	* Calibrate loops per jiffy value.
	408	* IRQs need to be enabled here - D-cache can be invalidated
	409	* in timer irq handler, so core B can read correct jiffies.
	410	*/
	411	calibrate_delay();
6b3087c6 GY	412
	413	cpu_idle();
	414	}
	415
	416	void __init smp_prepare_boot_cpu(void)
	417	{
	418	}
	419
	420	void __init smp_prepare_cpus(unsigned int max_cpus)
	421	{
	422	platform_prepare_cpus(max_cpus);
	423	ipi_queue_init();
73a40064 YL	424	platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
73a40064 YL	425	platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
6b3087c6 GY	426	}
	427
	428	void __init smp_cpus_done(unsigned int max_cpus)
	429	{
	430	unsigned long bogosum = 0;
	431	unsigned int cpu;
	432
	433	for_each_online_cpu(cpu)
c70c754f	434	bogosum += loops_per_jiffy;
6b3087c6 GY	435
	436	printk(KERN_INFO "SMP: Total of %d processors activated "
	437	"(%lu.%02lu BogoMIPS).\n",
	438	num_online_cpus(),
	439	bogosum / (500000/HZ),
	440	(bogosum / (5000/HZ)) % 100);
	441	}
	442
	443	void smp_icache_flush_range_others(unsigned long start, unsigned long end)
	444	{
	445	smp_flush_data.start = start;
	446	smp_flush_data.end = end;
	447
0bf3d933	448	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
6b3087c6 GY	449	printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
	450	}
	451	EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
	452
47e9dedb	453	#ifdef __ARCH_SYNC_CORE_ICACHE
718340f6	454	unsigned long icache_invld_count[NR_CPUS];
47e9dedb SZ	455	void resync_core_icache(void)
	456	{
	457	unsigned int cpu = get_cpu();
	458	blackfin_invalidate_entire_icache();
718340f6	459	icache_invld_count[cpu]++;
47e9dedb SZ	460	put_cpu();
	461	}
	462	EXPORT_SYMBOL(resync_core_icache);
	463	#endif
	464
6b3087c6	465	#ifdef __ARCH_SYNC_CORE_DCACHE
718340f6	466	unsigned long dcache_invld_count[NR_CPUS];
6b3087c6 GY	467	unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
	468
	469	void resync_core_dcache(void)
	470	{
	471	unsigned int cpu = get_cpu();
	472	blackfin_invalidate_entire_dcache();
718340f6	473	dcache_invld_count[cpu]++;
6b3087c6 GY	474	put_cpu();
	475	}
	476	EXPORT_SYMBOL(resync_core_dcache);
	477	#endif
0b39db28 GY	478
	479	#ifdef CONFIG_HOTPLUG_CPU
	480	int __cpuexit __cpu_disable(void)
	481	{
	482	unsigned int cpu = smp_processor_id();
	483
	484	if (cpu == 0)
	485	return -EPERM;
	486
	487	set_cpu_online(cpu, false);
	488	return 0;
	489	}
	490
	491	static DECLARE_COMPLETION(cpu_killed);
	492
	493	int __cpuexit __cpu_die(unsigned int cpu)
	494	{
	495	return wait_for_completion_timeout(&cpu_killed, 5000);
	496	}
	497
	498	void cpu_die(void)
	499	{
	500	complete(&cpu_killed);
	501
	502	atomic_dec(&init_mm.mm_users);
	503	atomic_dec(&init_mm.mm_count);
	504
	505	local_irq_disable();
	506	platform_cpu_die();
	507	}
	508	#endif