Commit | Line | Data |
---|---|---|
6b3087c6 | 1 | /* |
96f1050d | 2 | * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited) |
6b3087c6 | 3 | * |
96f1050d RG |
4 | * Copyright 2007-2009 Analog Devices Inc. |
5 | * Philippe Gerum <rpm@xenomai.org> | |
6b3087c6 | 6 | * |
96f1050d | 7 | * Licensed under the GPL-2. |
6b3087c6 GY |
8 | */ |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/cache.h> | |
d0014be4 | 17 | #include <linux/clockchips.h> |
6b3087c6 GY |
18 | #include <linux/profile.h> |
19 | #include <linux/errno.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
9c199b59 | 23 | #include <linux/cpumask.h> |
6b3087c6 GY |
24 | #include <linux/seq_file.h> |
25 | #include <linux/irq.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
60063497 | 27 | #include <linux/atomic.h> |
6b3087c6 | 28 | #include <asm/cacheflush.h> |
6327a574 | 29 | #include <asm/irq_handler.h> |
6b3087c6 GY |
30 | #include <asm/mmu_context.h> |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/pgalloc.h> | |
33 | #include <asm/processor.h> | |
34 | #include <asm/ptrace.h> | |
35 | #include <asm/cpu.h> | |
1fa9be72 | 36 | #include <asm/time.h> |
6b3087c6 GY |
37 | #include <linux/err.h> |
38 | ||
555487bb GY |
39 | /* |
40 | * Anomaly notes: | |
41 | * 05000120 - we always define corelock as 32-bit integer in L2 | |
42 | */ | |
6b3087c6 GY |
43 | struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); |
44 | ||
c6345ab1 SZ |
45 | #ifdef CONFIG_ICACHE_FLUSH_L1 |
46 | unsigned long blackfin_iflush_l1_entry[NR_CPUS]; | |
47 | #endif | |
48 | ||
fb1d9be5 | 49 | struct blackfin_initial_pda __cpuinitdata initial_pda_coreb; |
6b3087c6 | 50 | |
50888469 SM |
51 | enum ipi_message_type { |
52 | BFIN_IPI_TIMER, | |
53 | BFIN_IPI_RESCHEDULE, | |
54 | BFIN_IPI_CALL_FUNC, | |
55 | BFIN_IPI_CALL_FUNC_SINGLE, | |
56 | BFIN_IPI_CPU_STOP, | |
57 | }; | |
6b3087c6 GY |
58 | |
59 | struct blackfin_flush_data { | |
60 | unsigned long start; | |
61 | unsigned long end; | |
62 | }; | |
63 | ||
64 | void *secondary_stack; | |
65 | ||
6b3087c6 GY |
66 | static struct blackfin_flush_data smp_flush_data; |
67 | ||
68 | static DEFINE_SPINLOCK(stop_lock); | |
69 | ||
73a40064 YL |
70 | /* A magic number - stress test shows this is safe for common cases */ |
71 | #define BFIN_IPI_MSGQ_LEN 5 | |
72 | ||
73 | /* Simple FIFO buffer, overflow leads to panic */ | |
50888469 | 74 | struct ipi_data { |
6b3087c6 | 75 | unsigned long count; |
50888469 | 76 | unsigned long bits; |
6b3087c6 GY |
77 | }; |
78 | ||
50888469 | 79 | static DEFINE_PER_CPU(struct ipi_data, bfin_ipi); |
6b3087c6 GY |
80 | |
81 | static void ipi_cpu_stop(unsigned int cpu) | |
82 | { | |
83 | spin_lock(&stop_lock); | |
84 | printk(KERN_CRIT "CPU%u: stopping\n", cpu); | |
85 | dump_stack(); | |
86 | spin_unlock(&stop_lock); | |
87 | ||
fecedc80 | 88 | set_cpu_online(cpu, false); |
6b3087c6 GY |
89 | |
90 | local_irq_disable(); | |
91 | ||
92 | while (1) | |
93 | SSYNC(); | |
94 | } | |
95 | ||
96 | static void ipi_flush_icache(void *info) | |
97 | { | |
98 | struct blackfin_flush_data *fdata = info; | |
99 | ||
100 | /* Invalidate the memory holding the bounds of the flushed region. */ | |
8d50de9e SZ |
101 | blackfin_dcache_invalidate_range((unsigned long)fdata, |
102 | (unsigned long)fdata + sizeof(*fdata)); | |
103 | ||
104 | /* Make sure all write buffers in the data side of the core | |
105 | * are flushed before trying to invalidate the icache. This | |
106 | * needs to be after the data flush and before the icache | |
107 | * flush so that the SSYNC does the right thing in preventing | |
108 | * the instruction prefetcher from hitting things in cached | |
109 | * memory at the wrong time -- it runs much further ahead than | |
110 | * the pipeline. | |
111 | */ | |
112 | SSYNC(); | |
113 | ||
114 | /* ipi_flaush_icache is invoked by generic flush_icache_range, | |
115 | * so call blackfin arch icache flush directly here. | |
116 | */ | |
117 | blackfin_icache_flush_range(fdata->start, fdata->end); | |
6b3087c6 GY |
118 | } |
119 | ||
73a40064 YL |
120 | /* Use IRQ_SUPPLE_0 to request reschedule. |
121 | * When returning from interrupt to user space, | |
122 | * there is chance to reschedule */ | |
123 | static irqreturn_t ipi_handler_int0(int irq, void *dev_instance) | |
124 | { | |
125 | unsigned int cpu = smp_processor_id(); | |
126 | ||
127 | platform_clear_ipi(cpu, IRQ_SUPPLE_0); | |
128 | return IRQ_HANDLED; | |
129 | } | |
130 | ||
d0014be4 BL |
131 | DECLARE_PER_CPU(struct clock_event_device, coretmr_events); |
132 | void ipi_timer(void) | |
133 | { | |
134 | int cpu = smp_processor_id(); | |
135 | struct clock_event_device *evt = &per_cpu(coretmr_events, cpu); | |
136 | evt->event_handler(evt); | |
137 | } | |
138 | ||
73a40064 | 139 | static irqreturn_t ipi_handler_int1(int irq, void *dev_instance) |
6b3087c6 | 140 | { |
50888469 | 141 | struct ipi_data *bfin_ipi_data; |
6b3087c6 | 142 | unsigned int cpu = smp_processor_id(); |
50888469 SM |
143 | unsigned long pending; |
144 | unsigned long msg; | |
6b3087c6 | 145 | |
73a40064 | 146 | platform_clear_ipi(cpu, IRQ_SUPPLE_1); |
6b3087c6 | 147 | |
50888469 SM |
148 | bfin_ipi_data = &__get_cpu_var(bfin_ipi); |
149 | ||
150 | while ((pending = xchg(&bfin_ipi_data->bits, 0)) != 0) { | |
151 | msg = 0; | |
152 | do { | |
153 | msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1); | |
154 | switch (msg) { | |
155 | case BFIN_IPI_TIMER: | |
156 | ipi_timer(); | |
157 | break; | |
158 | case BFIN_IPI_RESCHEDULE: | |
159 | scheduler_ipi(); | |
160 | break; | |
161 | case BFIN_IPI_CALL_FUNC: | |
162 | generic_smp_call_function_interrupt(); | |
163 | break; | |
164 | ||
165 | case BFIN_IPI_CALL_FUNC_SINGLE: | |
166 | generic_smp_call_function_single_interrupt(); | |
167 | break; | |
168 | ||
169 | case BFIN_IPI_CPU_STOP: | |
170 | ipi_cpu_stop(cpu); | |
171 | break; | |
172 | } | |
173 | } while (msg < BITS_PER_LONG); | |
174 | ||
175 | smp_mb(); | |
6b3087c6 | 176 | } |
6b3087c6 GY |
177 | return IRQ_HANDLED; |
178 | } | |
179 | ||
50888469 | 180 | static void bfin_ipi_init(void) |
6b3087c6 GY |
181 | { |
182 | unsigned int cpu; | |
50888469 | 183 | struct ipi_data *bfin_ipi_data; |
6b3087c6 | 184 | for_each_possible_cpu(cpu) { |
50888469 SM |
185 | bfin_ipi_data = &per_cpu(bfin_ipi, cpu); |
186 | bfin_ipi_data->bits = 0; | |
187 | bfin_ipi_data->count = 0; | |
6b3087c6 GY |
188 | } |
189 | } | |
190 | ||
50888469 | 191 | void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg) |
6b3087c6 GY |
192 | { |
193 | unsigned int cpu; | |
50888469 SM |
194 | struct ipi_data *bfin_ipi_data; |
195 | unsigned long flags; | |
196 | ||
197 | local_irq_save(flags); | |
198 | ||
199 | for_each_cpu(cpu, cpumask) { | |
200 | bfin_ipi_data = &per_cpu(bfin_ipi, cpu); | |
201 | smp_mb(); | |
202 | set_bit(msg, &bfin_ipi_data->bits); | |
203 | bfin_ipi_data->count++; | |
73a40064 | 204 | platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1); |
6b3087c6 | 205 | } |
73a40064 | 206 | |
50888469 | 207 | local_irq_restore(flags); |
73a40064 YL |
208 | } |
209 | ||
50888469 | 210 | void arch_send_call_function_single_ipi(int cpu) |
73a40064 | 211 | { |
50888469 | 212 | send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC_SINGLE); |
6b3087c6 | 213 | } |
6b3087c6 | 214 | |
50888469 | 215 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
6b3087c6 | 216 | { |
50888469 | 217 | send_ipi(mask, BFIN_IPI_CALL_FUNC); |
6b3087c6 | 218 | } |
6b3087c6 GY |
219 | |
220 | void smp_send_reschedule(int cpu) | |
221 | { | |
50888469 | 222 | send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE); |
6b3087c6 GY |
223 | |
224 | return; | |
225 | } | |
226 | ||
d0014be4 BL |
227 | void smp_send_msg(const struct cpumask *mask, unsigned long type) |
228 | { | |
50888469 | 229 | send_ipi(mask, type); |
d0014be4 BL |
230 | } |
231 | ||
232 | void smp_timer_broadcast(const struct cpumask *mask) | |
233 | { | |
234 | smp_send_msg(mask, BFIN_IPI_TIMER); | |
235 | } | |
236 | ||
6b3087c6 GY |
237 | void smp_send_stop(void) |
238 | { | |
6b3087c6 | 239 | cpumask_t callmap; |
6b3087c6 | 240 | |
567ebfc9 | 241 | preempt_disable(); |
fecedc80 KM |
242 | cpumask_copy(&callmap, cpu_online_mask); |
243 | cpumask_clear_cpu(smp_processor_id(), &callmap); | |
244 | if (!cpumask_empty(&callmap)) | |
50888469 | 245 | send_ipi(&callmap, BFIN_IPI_CPU_STOP); |
6b3087c6 | 246 | |
567ebfc9 | 247 | preempt_enable(); |
6b3087c6 | 248 | |
6b3087c6 GY |
249 | return; |
250 | } | |
251 | ||
6bba2682 | 252 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) |
6b3087c6 | 253 | { |
6b3087c6 | 254 | int ret; |
0b39db28 | 255 | |
6b3087c6 | 256 | secondary_stack = task_stack_page(idle) + THREAD_SIZE; |
6b3087c6 GY |
257 | |
258 | ret = platform_boot_secondary(cpu, idle); | |
259 | ||
6b3087c6 GY |
260 | secondary_stack = NULL; |
261 | ||
262 | return ret; | |
263 | } | |
264 | ||
265 | static void __cpuinit setup_secondary(unsigned int cpu) | |
266 | { | |
6b3087c6 GY |
267 | unsigned long ilat; |
268 | ||
269 | bfin_write_IMASK(0); | |
270 | CSYNC(); | |
271 | ilat = bfin_read_ILAT(); | |
272 | CSYNC(); | |
273 | bfin_write_ILAT(ilat); | |
274 | CSYNC(); | |
275 | ||
6b3087c6 GY |
276 | /* Enable interrupt levels IVG7-15. IARs have been already |
277 | * programmed by the boot CPU. */ | |
40059784 | 278 | bfin_irq_flags |= IMASK_IVG15 | |
6b3087c6 GY |
279 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
280 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; | |
6b3087c6 GY |
281 | } |
282 | ||
283 | void __cpuinit secondary_start_kernel(void) | |
284 | { | |
285 | unsigned int cpu = smp_processor_id(); | |
286 | struct mm_struct *mm = &init_mm; | |
287 | ||
288 | if (_bfin_swrst & SWRST_DBL_FAULT_B) { | |
289 | printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n"); | |
290 | #ifdef CONFIG_DEBUG_DOUBLEFAULT | |
fb1d9be5 MF |
291 | printk(KERN_EMERG " While handling exception (EXCAUSE = %#x) at %pF\n", |
292 | initial_pda_coreb.seqstat_doublefault & SEQSTAT_EXCAUSE, | |
293 | initial_pda_coreb.retx_doublefault); | |
294 | printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", | |
295 | initial_pda_coreb.dcplb_doublefault_addr); | |
296 | printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", | |
297 | initial_pda_coreb.icplb_doublefault_addr); | |
6b3087c6 GY |
298 | #endif |
299 | printk(KERN_NOTICE " The instruction at %pF caused a double exception\n", | |
fb1d9be5 | 300 | initial_pda_coreb.retx); |
6b3087c6 GY |
301 | } |
302 | ||
303 | /* | |
304 | * We want the D-cache to be enabled early, in case the atomic | |
305 | * support code emulates cache coherence (see | |
306 | * __ARCH_SYNC_CORE_DCACHE). | |
307 | */ | |
308 | init_exception_vectors(); | |
309 | ||
6b3087c6 GY |
310 | local_irq_disable(); |
311 | ||
312 | /* Attach the new idle task to the global mm. */ | |
313 | atomic_inc(&mm->mm_users); | |
314 | atomic_inc(&mm->mm_count); | |
315 | current->active_mm = mm; | |
6b3087c6 GY |
316 | |
317 | preempt_disable(); | |
318 | ||
319 | setup_secondary(cpu); | |
320 | ||
578d36f5 YL |
321 | platform_secondary_init(cpu); |
322 | ||
0d152c27 YL |
323 | /* setup local core timer */ |
324 | bfin_local_timer_setup(); | |
325 | ||
6b3087c6 GY |
326 | local_irq_enable(); |
327 | ||
ab61d2ac | 328 | bfin_setup_caches(cpu); |
329 | ||
d0014be4 | 330 | notify_cpu_starting(cpu); |
578d36f5 YL |
331 | /* |
332 | * Calibrate loops per jiffy value. | |
333 | * IRQs need to be enabled here - D-cache can be invalidated | |
334 | * in timer irq handler, so core B can read correct jiffies. | |
335 | */ | |
336 | calibrate_delay(); | |
6b3087c6 GY |
337 | |
338 | cpu_idle(); | |
339 | } | |
340 | ||
341 | void __init smp_prepare_boot_cpu(void) | |
342 | { | |
343 | } | |
344 | ||
345 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
346 | { | |
347 | platform_prepare_cpus(max_cpus); | |
50888469 | 348 | bfin_ipi_init(); |
73a40064 YL |
349 | platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0); |
350 | platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1); | |
6b3087c6 GY |
351 | } |
352 | ||
353 | void __init smp_cpus_done(unsigned int max_cpus) | |
354 | { | |
355 | unsigned long bogosum = 0; | |
356 | unsigned int cpu; | |
357 | ||
358 | for_each_online_cpu(cpu) | |
c70c754f | 359 | bogosum += loops_per_jiffy; |
6b3087c6 GY |
360 | |
361 | printk(KERN_INFO "SMP: Total of %d processors activated " | |
362 | "(%lu.%02lu BogoMIPS).\n", | |
363 | num_online_cpus(), | |
364 | bogosum / (500000/HZ), | |
365 | (bogosum / (5000/HZ)) % 100); | |
366 | } | |
367 | ||
368 | void smp_icache_flush_range_others(unsigned long start, unsigned long end) | |
369 | { | |
370 | smp_flush_data.start = start; | |
371 | smp_flush_data.end = end; | |
372 | ||
a2eff9dd SM |
373 | preempt_disable(); |
374 | if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1)) | |
6b3087c6 | 375 | printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n"); |
a2eff9dd | 376 | preempt_enable(); |
6b3087c6 GY |
377 | } |
378 | EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); | |
379 | ||
47e9dedb | 380 | #ifdef __ARCH_SYNC_CORE_ICACHE |
718340f6 | 381 | unsigned long icache_invld_count[NR_CPUS]; |
47e9dedb SZ |
382 | void resync_core_icache(void) |
383 | { | |
384 | unsigned int cpu = get_cpu(); | |
385 | blackfin_invalidate_entire_icache(); | |
718340f6 | 386 | icache_invld_count[cpu]++; |
47e9dedb SZ |
387 | put_cpu(); |
388 | } | |
389 | EXPORT_SYMBOL(resync_core_icache); | |
390 | #endif | |
391 | ||
6b3087c6 | 392 | #ifdef __ARCH_SYNC_CORE_DCACHE |
718340f6 | 393 | unsigned long dcache_invld_count[NR_CPUS]; |
6b3087c6 GY |
394 | unsigned long barrier_mask __attribute__ ((__section__(".l2.bss"))); |
395 | ||
396 | void resync_core_dcache(void) | |
397 | { | |
398 | unsigned int cpu = get_cpu(); | |
399 | blackfin_invalidate_entire_dcache(); | |
718340f6 | 400 | dcache_invld_count[cpu]++; |
6b3087c6 GY |
401 | put_cpu(); |
402 | } | |
403 | EXPORT_SYMBOL(resync_core_dcache); | |
404 | #endif | |
0b39db28 GY |
405 | |
406 | #ifdef CONFIG_HOTPLUG_CPU | |
407 | int __cpuexit __cpu_disable(void) | |
408 | { | |
409 | unsigned int cpu = smp_processor_id(); | |
410 | ||
411 | if (cpu == 0) | |
412 | return -EPERM; | |
413 | ||
414 | set_cpu_online(cpu, false); | |
415 | return 0; | |
416 | } | |
417 | ||
418 | static DECLARE_COMPLETION(cpu_killed); | |
419 | ||
420 | int __cpuexit __cpu_die(unsigned int cpu) | |
421 | { | |
422 | return wait_for_completion_timeout(&cpu_killed, 5000); | |
423 | } | |
424 | ||
425 | void cpu_die(void) | |
426 | { | |
427 | complete(&cpu_killed); | |
428 | ||
429 | atomic_dec(&init_mm.mm_users); | |
430 | atomic_dec(&init_mm.mm_count); | |
431 | ||
432 | local_irq_disable(); | |
433 | platform_cpu_die(); | |
434 | } | |
435 | #endif |