[deliverable/linux.git] / arch / blackfin / mach-common / smp.c

/*
 * IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
 *
 * Copyright 2007-2009 Analog Devices Inc.
 *                         Philippe Gerum <rpm@xenomai.org>
 *
 * Licensed under the GPL-2.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/cache.h>
#include <linux/profile.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/cpu.h>
#include <linux/smp.h>
#include <linux/cpumask.h>
#include <linux/seq_file.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#include <asm/irq_handler.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/cpu.h>
#include <asm/time.h>
#include <linux/err.h>

/*
 * Anomaly notes:
 * 05000120 - we always define corelock as 32-bit integer in L2
 */
struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));

#ifdef CONFIG_ICACHE_FLUSH_L1
unsigned long blackfin_iflush_l1_entry[NR_CPUS];
#endif

void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
	*init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
	*init_saved_dcplb_fault_addr_coreb;

#define BFIN_IPI_RESCHEDULE   0
#define BFIN_IPI_CALL_FUNC    1
#define BFIN_IPI_CPU_STOP     2

struct blackfin_flush_data {
	unsigned long start;
	unsigned long end;
};

void *secondary_stack;


struct smp_call_struct {
	void (*func)(void *info);
	void *info;
	int wait;
	cpumask_t *waitmask;
};

static struct blackfin_flush_data smp_flush_data;

static DEFINE_SPINLOCK(stop_lock);

struct ipi_message {
	unsigned long type;
	struct smp_call_struct call_struct;
};

/* A magic number - stress test shows this is safe for common cases */
#define BFIN_IPI_MSGQ_LEN 5

/* Simple FIFO buffer, overflow leads to panic */
struct ipi_message_queue {
	spinlock_t lock;
	unsigned long count;
	unsigned long head; /* head of the queue */
	struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
};

static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);

static void ipi_cpu_stop(unsigned int cpu)
{
	spin_lock(&stop_lock);
	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	dump_stack();
	spin_unlock(&stop_lock);

	set_cpu_online(cpu, false);

	local_irq_disable();

	while (1)
		SSYNC();
}

static void ipi_flush_icache(void *info)
{
	struct blackfin_flush_data *fdata = info;

	/* Invalidate the memory holding the bounds of the flushed region. */
	blackfin_dcache_invalidate_range((unsigned long)fdata,
					 (unsigned long)fdata + sizeof(*fdata));

	/* Make sure all write buffers in the data side of the core
	 * are flushed before trying to invalidate the icache.  This
	 * needs to be after the data flush and before the icache
	 * flush so that the SSYNC does the right thing in preventing
	 * the instruction prefetcher from hitting things in cached
	 * memory at the wrong time -- it runs much further ahead than
	 * the pipeline.
	 */
	SSYNC();

	/* ipi_flaush_icache is invoked by generic flush_icache_range,
	 * so call blackfin arch icache flush directly here.
	 */
	blackfin_icache_flush_range(fdata->start, fdata->end);
}

static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
{
	int wait;
	void (*func)(void *info);
	void *info;
	func = msg->call_struct.func;
	info = msg->call_struct.info;
	wait = msg->call_struct.wait;
	func(info);
	if (wait) {
#ifdef __ARCH_SYNC_CORE_DCACHE
		/*
		 * 'wait' usually means synchronization between CPUs.
		 * Invalidate D cache in case shared data was changed
		 * by func() to ensure cache coherence.
		 */
		resync_core_dcache();
#endif
		cpumask_clear_cpu(cpu, msg->call_struct.waitmask);
	}
}

/* Use IRQ_SUPPLE_0 to request reschedule.
 * When returning from interrupt to user space,
 * there is chance to reschedule */
static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
{
	unsigned int cpu = smp_processor_id();

	platform_clear_ipi(cpu, IRQ_SUPPLE_0);
	return IRQ_HANDLED;
}

static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
{
	struct ipi_message *msg;
	struct ipi_message_queue *msg_queue;
	unsigned int cpu = smp_processor_id();
	unsigned long flags;

	platform_clear_ipi(cpu, IRQ_SUPPLE_1);

	msg_queue = &__get_cpu_var(ipi_msg_queue);

	spin_lock_irqsave(&msg_queue->lock, flags);

	while (msg_queue->count) {
		msg = &msg_queue->ipi_message[msg_queue->head];
		switch (msg->type) {
		case BFIN_IPI_RESCHEDULE:
			scheduler_ipi();
			break;
		case BFIN_IPI_CALL_FUNC:
			spin_unlock_irqrestore(&msg_queue->lock, flags);
			ipi_call_function(cpu, msg);
			spin_lock_irqsave(&msg_queue->lock, flags);
			break;
		case BFIN_IPI_CPU_STOP:
			spin_unlock_irqrestore(&msg_queue->lock, flags);
			ipi_cpu_stop(cpu);
			spin_lock_irqsave(&msg_queue->lock, flags);
			break;
		default:
			printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
			       cpu, msg->type);
			break;
		}
		msg_queue->head++;
		msg_queue->head %= BFIN_IPI_MSGQ_LEN;
		msg_queue->count--;
	}
	spin_unlock_irqrestore(&msg_queue->lock, flags);
	return IRQ_HANDLED;
}

static void ipi_queue_init(void)
{
	unsigned int cpu;
	struct ipi_message_queue *msg_queue;
	for_each_possible_cpu(cpu) {
		msg_queue = &per_cpu(ipi_msg_queue, cpu);
		spin_lock_init(&msg_queue->lock);
		msg_queue->count = 0;
		msg_queue->head = 0;
	}
}

static inline void smp_send_message(cpumask_t callmap, unsigned long type,
					void (*func) (void *info), void *info, int wait)
{
	unsigned int cpu;
	struct ipi_message_queue *msg_queue;
	struct ipi_message *msg;
	unsigned long flags, next_msg;
	cpumask_t waitmask; /* waitmask is shared by all cpus */

	cpumask_copy(&waitmask, &callmap);
	for_each_cpu(cpu, &callmap) {
		msg_queue = &per_cpu(ipi_msg_queue, cpu);
		spin_lock_irqsave(&msg_queue->lock, flags);
		if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
			next_msg = (msg_queue->head + msg_queue->count)
					% BFIN_IPI_MSGQ_LEN;
			msg = &msg_queue->ipi_message[next_msg];
			msg->type = type;
			if (type == BFIN_IPI_CALL_FUNC) {
				msg->call_struct.func = func;
				msg->call_struct.info = info;
				msg->call_struct.wait = wait;
				msg->call_struct.waitmask = &waitmask;
			}
			msg_queue->count++;
		} else
			panic("IPI message queue overflow\n");
		spin_unlock_irqrestore(&msg_queue->lock, flags);
		platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
	}

	if (wait) {
		while (!cpumask_empty(&waitmask))
			blackfin_dcache_invalidate_range(
				(unsigned long)(&waitmask),
				(unsigned long)(&waitmask));
#ifdef __ARCH_SYNC_CORE_DCACHE
		/*
		 * Invalidate D cache in case shared data was changed by
		 * other processors to ensure cache coherence.
		 */
		resync_core_dcache();
#endif
	}
}

int smp_call_function(void (*func)(void *info), void *info, int wait)
{
	cpumask_t callmap;

	preempt_disable();
	cpumask_copy(&callmap, cpu_online_mask);
	cpumask_clear_cpu(smp_processor_id(), &callmap);
	if (!cpumask_empty(&callmap))
		smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);

	preempt_enable();

	return 0;
}
EXPORT_SYMBOL_GPL(smp_call_function);

int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
				int wait)
{
	unsigned int cpu = cpuid;
	cpumask_t callmap;

	if (cpu_is_offline(cpu))
		return 0;
	cpumask_clear(&callmap);
	cpumask_set_cpu(cpu, &callmap);

	smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);

	return 0;
}
EXPORT_SYMBOL_GPL(smp_call_function_single);

void smp_send_reschedule(int cpu)
{
	/* simply trigger an ipi */
	if (cpu_is_offline(cpu))
		return;
	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);

	return;
}

void smp_send_stop(void)
{
	cpumask_t callmap;

	preempt_disable();
	cpumask_copy(&callmap, cpu_online_mask);
	cpumask_clear_cpu(smp_processor_id(), &callmap);
	if (!cpumask_empty(&callmap))
		smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);

	preempt_enable();

	return;
}

int __cpuinit __cpu_up(unsigned int cpu)
{
	int ret;
	static struct task_struct *idle;

	if (idle)
		free_task(idle);

	idle = fork_idle(cpu);
	if (IS_ERR(idle)) {
		printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
		return PTR_ERR(idle);
	}

	secondary_stack = task_stack_page(idle) + THREAD_SIZE;

	ret = platform_boot_secondary(cpu, idle);

	secondary_stack = NULL;

	return ret;
}

static void __cpuinit setup_secondary(unsigned int cpu)
{
	unsigned long ilat;

	bfin_write_IMASK(0);
	CSYNC();
	ilat = bfin_read_ILAT();
	CSYNC();
	bfin_write_ILAT(ilat);
	CSYNC();

	/* Enable interrupt levels IVG7-15. IARs have been already
	 * programmed by the boot CPU.  */
	bfin_irq_flags |= IMASK_IVG15 |
	    IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
	    IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
}

void __cpuinit secondary_start_kernel(void)
{
	unsigned int cpu = smp_processor_id();
	struct mm_struct *mm = &init_mm;

	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
		printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
#ifdef CONFIG_DEBUG_DOUBLEFAULT
		printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
			(int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
		printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
		printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
#endif
		printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
			init_retx_coreb);
	}

	/*
	 * We want the D-cache to be enabled early, in case the atomic
	 * support code emulates cache coherence (see
	 * __ARCH_SYNC_CORE_DCACHE).
	 */
	init_exception_vectors();

	local_irq_disable();

	/* Attach the new idle task to the global mm. */
	atomic_inc(&mm->mm_users);
	atomic_inc(&mm->mm_count);
	current->active_mm = mm;

	preempt_disable();

	setup_secondary(cpu);

	platform_secondary_init(cpu);

	/* setup local core timer */
	bfin_local_timer_setup();

	local_irq_enable();

	bfin_setup_caches(cpu);

	/*
	 * Calibrate loops per jiffy value.
	 * IRQs need to be enabled here - D-cache can be invalidated
	 * in timer irq handler, so core B can read correct jiffies.
	 */
	calibrate_delay();

	cpu_idle();
}

void __init smp_prepare_boot_cpu(void)
{
}

void __init smp_prepare_cpus(unsigned int max_cpus)
{
	platform_prepare_cpus(max_cpus);
	ipi_queue_init();
	platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
	platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
}

void __init smp_cpus_done(unsigned int max_cpus)
{
	unsigned long bogosum = 0;
	unsigned int cpu;

	for_each_online_cpu(cpu)
		bogosum += loops_per_jiffy;

	printk(KERN_INFO "SMP: Total of %d processors activated "
	       "(%lu.%02lu BogoMIPS).\n",
	       num_online_cpus(),
	       bogosum / (500000/HZ),
	       (bogosum / (5000/HZ)) % 100);
}

void smp_icache_flush_range_others(unsigned long start, unsigned long end)
{
	smp_flush_data.start = start;
	smp_flush_data.end = end;

	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
		printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
}
EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);

#ifdef __ARCH_SYNC_CORE_ICACHE
unsigned long icache_invld_count[NR_CPUS];
void resync_core_icache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_icache();
	icache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_icache);
#endif

#ifdef __ARCH_SYNC_CORE_DCACHE
unsigned long dcache_invld_count[NR_CPUS];
unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));

void resync_core_dcache(void)
{
	unsigned int cpu = get_cpu();
	blackfin_invalidate_entire_dcache();
	dcache_invld_count[cpu]++;
	put_cpu();
}
EXPORT_SYMBOL(resync_core_dcache);
#endif

#ifdef CONFIG_HOTPLUG_CPU
int __cpuexit __cpu_disable(void)
{
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EPERM;

	set_cpu_online(cpu, false);
	return 0;
}

static DECLARE_COMPLETION(cpu_killed);

int __cpuexit __cpu_die(unsigned int cpu)
{
	return wait_for_completion_timeout(&cpu_killed, 5000);
}

void cpu_die(void)
{
	complete(&cpu_killed);

	atomic_dec(&init_mm.mm_users);
	atomic_dec(&init_mm.mm_count);

	local_irq_disable();
	platform_cpu_die();
}
#endif
Commit	Line	Data
6b3087c6	1	/*
96f1050d	2	* IPI management based on arch/arm/kernel/smp.c (Copyright 2002 ARM Limited)
6b3087c6	3	*
96f1050d RG	4	* Copyright 2007-2009 Analog Devices Inc.
96f1050d RG	5	* Philippe Gerum <rpm@xenomai.org>
6b3087c6	6	*
96f1050d	7	* Licensed under the GPL-2.
6b3087c6 GY	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/sched.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/cache.h>
	17	#include <linux/profile.h>
	18	#include <linux/errno.h>
	19	#include <linux/mm.h>
	20	#include <linux/cpu.h>
	21	#include <linux/smp.h>
9c199b59	22	#include <linux/cpumask.h>
6b3087c6 GY	23	#include <linux/seq_file.h>
6b3087c6 GY	24	#include <linux/irq.h>
5a0e3ad6	25	#include <linux/slab.h>
6b3087c6 GY	26	#include <asm/atomic.h>
6b3087c6 GY	27	#include <asm/cacheflush.h>
6327a574	28	#include <asm/irq_handler.h>
6b3087c6 GY	29	#include <asm/mmu_context.h>
	30	#include <asm/pgtable.h>
	31	#include <asm/pgalloc.h>
	32	#include <asm/processor.h>
	33	#include <asm/ptrace.h>
	34	#include <asm/cpu.h>
1fa9be72	35	#include <asm/time.h>
6b3087c6 GY	36	#include <linux/err.h>
6b3087c6 GY	37
555487bb GY	38	/*
	39	* Anomaly notes:
	40	* 05000120 - we always define corelock as 32-bit integer in L2
	41	*/
6b3087c6 GY	42	struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
6b3087c6 GY	43
c6345ab1 SZ	44	#ifdef CONFIG_ICACHE_FLUSH_L1
	45	unsigned long blackfin_iflush_l1_entry[NR_CPUS];
	46	#endif
	47
6b3087c6 GY	48	void __cpuinitdata init_retx_coreb, init_saved_retx_coreb,
	49	init_saved_seqstat_coreb, init_saved_icplb_fault_addr_coreb,
	50	*init_saved_dcplb_fault_addr_coreb;
	51
6b3087c6 GY	52	#define BFIN_IPI_RESCHEDULE 0
	53	#define BFIN_IPI_CALL_FUNC 1
	54	#define BFIN_IPI_CPU_STOP 2
	55
	56	struct blackfin_flush_data {
	57	unsigned long start;
	58	unsigned long end;
	59	};
	60
	61	void *secondary_stack;
	62
	63
	64	struct smp_call_struct {
	65	void (func)(void info);
	66	void *info;
	67	int wait;
73a40064	68	cpumask_t *waitmask;
6b3087c6 GY	69	};
	70
	71	static struct blackfin_flush_data smp_flush_data;
	72
	73	static DEFINE_SPINLOCK(stop_lock);
	74
	75	struct ipi_message {
6b3087c6 GY	76	unsigned long type;
	77	struct smp_call_struct call_struct;
	78	};
	79
73a40064 YL	80	/* A magic number - stress test shows this is safe for common cases */
	81	#define BFIN_IPI_MSGQ_LEN 5
	82
	83	/* Simple FIFO buffer, overflow leads to panic */
6b3087c6	84	struct ipi_message_queue {
6b3087c6 GY	85	spinlock_t lock;
6b3087c6 GY	86	unsigned long count;
73a40064 YL	87	unsigned long head; /* head of the queue */
73a40064 YL	88	struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
6b3087c6 GY	89	};
	90
	91	static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
	92
	93	static void ipi_cpu_stop(unsigned int cpu)
	94	{
	95	spin_lock(&stop_lock);
	96	printk(KERN_CRIT "CPU%u: stopping\n", cpu);
	97	dump_stack();
	98	spin_unlock(&stop_lock);
	99
fecedc80	100	set_cpu_online(cpu, false);
6b3087c6 GY	101
	102	local_irq_disable();
	103
	104	while (1)
	105	SSYNC();
	106	}
	107
	108	static void ipi_flush_icache(void *info)
	109	{
	110	struct blackfin_flush_data *fdata = info;
	111
	112	/* Invalidate the memory holding the bounds of the flushed region. */
8d50de9e SZ	113	blackfin_dcache_invalidate_range((unsigned long)fdata,
	114	(unsigned long)fdata + sizeof(*fdata));
	115
	116	/* Make sure all write buffers in the data side of the core
	117	* are flushed before trying to invalidate the icache. This
	118	* needs to be after the data flush and before the icache
	119	* flush so that the SSYNC does the right thing in preventing
	120	* the instruction prefetcher from hitting things in cached
	121	* memory at the wrong time -- it runs much further ahead than
	122	* the pipeline.
	123	*/
	124	SSYNC();
	125
	126	/* ipi_flaush_icache is invoked by generic flush_icache_range,
	127	* so call blackfin arch icache flush directly here.
	128	*/
	129	blackfin_icache_flush_range(fdata->start, fdata->end);
6b3087c6 GY	130	}
	131
	132	static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
	133	{
	134	int wait;
	135	void (func)(void info);
	136	void *info;
	137	func = msg->call_struct.func;
	138	info = msg->call_struct.info;
	139	wait = msg->call_struct.wait;
6b3087c6	140	func(info);
c9784ebb YL	141	if (wait) {
	142	#ifdef __ARCH_SYNC_CORE_DCACHE
	143	/*
	144	* 'wait' usually means synchronization between CPUs.
	145	* Invalidate D cache in case shared data was changed
	146	* by func() to ensure cache coherence.
	147	*/
	148	resync_core_dcache();
	149	#endif
fecedc80	150	cpumask_clear_cpu(cpu, msg->call_struct.waitmask);
73a40064	151	}
6b3087c6 GY	152	}
6b3087c6 GY	153
73a40064 YL	154	/* Use IRQ_SUPPLE_0 to request reschedule.
	155	* When returning from interrupt to user space,
	156	* there is chance to reschedule */
	157	static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
	158	{
	159	unsigned int cpu = smp_processor_id();
	160
	161	platform_clear_ipi(cpu, IRQ_SUPPLE_0);
	162	return IRQ_HANDLED;
	163	}
	164
	165	static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
6b3087c6	166	{
86f2008b	167	struct ipi_message *msg;
6b3087c6 GY	168	struct ipi_message_queue *msg_queue;
6b3087c6 GY	169	unsigned int cpu = smp_processor_id();
73a40064	170	unsigned long flags;
6b3087c6	171
73a40064	172	platform_clear_ipi(cpu, IRQ_SUPPLE_1);
6b3087c6 GY	173
6b3087c6 GY	174	msg_queue = &__get_cpu_var(ipi_msg_queue);
6b3087c6	175
73a40064 YL	176	spin_lock_irqsave(&msg_queue->lock, flags);
	177
	178	while (msg_queue->count) {
	179	msg = &msg_queue->ipi_message[msg_queue->head];
6b3087c6	180	switch (msg->type) {
184748cc PZ	181	case BFIN_IPI_RESCHEDULE:
	182	scheduler_ipi();
	183	break;
6b3087c6	184	case BFIN_IPI_CALL_FUNC:
73a40064	185	spin_unlock_irqrestore(&msg_queue->lock, flags);
6b3087c6	186	ipi_call_function(cpu, msg);
73a40064	187	spin_lock_irqsave(&msg_queue->lock, flags);
6b3087c6 GY	188	break;
6b3087c6 GY	189	case BFIN_IPI_CPU_STOP:
73a40064	190	spin_unlock_irqrestore(&msg_queue->lock, flags);
6b3087c6	191	ipi_cpu_stop(cpu);
73a40064	192	spin_lock_irqsave(&msg_queue->lock, flags);
6b3087c6 GY	193	break;
6b3087c6 GY	194	default:
db52ecc2 JP	195	printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
db52ecc2 JP	196	cpu, msg->type);
6b3087c6 GY	197	break;
6b3087c6 GY	198	}
73a40064 YL	199	msg_queue->head++;
	200	msg_queue->head %= BFIN_IPI_MSGQ_LEN;
	201	msg_queue->count--;
6b3087c6	202	}
73a40064	203	spin_unlock_irqrestore(&msg_queue->lock, flags);
6b3087c6 GY	204	return IRQ_HANDLED;
	205	}
	206
	207	static void ipi_queue_init(void)
	208	{
	209	unsigned int cpu;
	210	struct ipi_message_queue *msg_queue;
	211	for_each_possible_cpu(cpu) {
	212	msg_queue = &per_cpu(ipi_msg_queue, cpu);
6b3087c6 GY	213	spin_lock_init(&msg_queue->lock);
6b3087c6 GY	214	msg_queue->count = 0;
73a40064	215	msg_queue->head = 0;
6b3087c6 GY	216	}
	217	}
	218
73a40064 YL	219	static inline void smp_send_message(cpumask_t callmap, unsigned long type,
73a40064 YL	220	void (func) (void info), void *info, int wait)
6b3087c6 GY	221	{
6b3087c6 GY	222	unsigned int cpu;
6b3087c6 GY	223	struct ipi_message_queue *msg_queue;
6b3087c6 GY	224	struct ipi_message *msg;
73a40064	225	unsigned long flags, next_msg;
fecedc80	226	cpumask_t waitmask; /* waitmask is shared by all cpus */
6b3087c6	227
fecedc80 KM	228	cpumask_copy(&waitmask, &callmap);
fecedc80 KM	229	for_each_cpu(cpu, &callmap) {
6b3087c6 GY	230	msg_queue = &per_cpu(ipi_msg_queue, cpu);
6b3087c6 GY	231	spin_lock_irqsave(&msg_queue->lock, flags);
73a40064 YL	232	if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
	233	next_msg = (msg_queue->head + msg_queue->count)
	234	% BFIN_IPI_MSGQ_LEN;
	235	msg = &msg_queue->ipi_message[next_msg];
	236	msg->type = type;
	237	if (type == BFIN_IPI_CALL_FUNC) {
	238	msg->call_struct.func = func;
	239	msg->call_struct.info = info;
	240	msg->call_struct.wait = wait;
	241	msg->call_struct.waitmask = &waitmask;
	242	}
	243	msg_queue->count++;
	244	} else
	245	panic("IPI message queue overflow\n");
6b3087c6	246	spin_unlock_irqrestore(&msg_queue->lock, flags);
73a40064	247	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
6b3087c6	248	}
73a40064	249
6b3087c6	250	if (wait) {
fecedc80	251	while (!cpumask_empty(&waitmask))
6b3087c6	252	blackfin_dcache_invalidate_range(
73a40064 YL	253	(unsigned long)(&waitmask),
73a40064 YL	254	(unsigned long)(&waitmask));
c9784ebb YL	255	#ifdef __ARCH_SYNC_CORE_DCACHE
	256	/*
	257	* Invalidate D cache in case shared data was changed by
	258	* other processors to ensure cache coherence.
	259	*/
	260	resync_core_dcache();
	261	#endif
6b3087c6	262	}
73a40064 YL	263	}
	264
	265	int smp_call_function(void (func)(void info), void *info, int wait)
	266	{
	267	cpumask_t callmap;
	268
567ebfc9	269	preempt_disable();
fecedc80 KM	270	cpumask_copy(&callmap, cpu_online_mask);
	271	cpumask_clear_cpu(smp_processor_id(), &callmap);
	272	if (!cpumask_empty(&callmap))
567ebfc9	273	smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
73a40064	274
567ebfc9	275	preempt_enable();
73a40064	276
6b3087c6 GY	277	return 0;
	278	}
	279	EXPORT_SYMBOL_GPL(smp_call_function);
	280
	281	int smp_call_function_single(int cpuid, void (func) (void info), void *info,
	282	int wait)
	283	{
	284	unsigned int cpu = cpuid;
	285	cpumask_t callmap;
6b3087c6 GY	286
	287	if (cpu_is_offline(cpu))
	288	return 0;
fecedc80 KM	289	cpumask_clear(&callmap);
fecedc80 KM	290	cpumask_set_cpu(cpu, &callmap);
6b3087c6	291
73a40064	292	smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
6b3087c6	293
6b3087c6 GY	294	return 0;
	295	}
	296	EXPORT_SYMBOL_GPL(smp_call_function_single);
	297
	298	void smp_send_reschedule(int cpu)
	299	{
73a40064	300	/* simply trigger an ipi */
6b3087c6 GY	301	if (cpu_is_offline(cpu))
6b3087c6 GY	302	return;
73a40064	303	platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
6b3087c6 GY	304
	305	return;
	306	}
	307
	308	void smp_send_stop(void)
	309	{
6b3087c6	310	cpumask_t callmap;
6b3087c6	311
567ebfc9	312	preempt_disable();
fecedc80 KM	313	cpumask_copy(&callmap, cpu_online_mask);
	314	cpumask_clear_cpu(smp_processor_id(), &callmap);
	315	if (!cpumask_empty(&callmap))
567ebfc9	316	smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
6b3087c6	317
567ebfc9	318	preempt_enable();
6b3087c6	319
6b3087c6 GY	320	return;
	321	}
	322
	323	int __cpuinit __cpu_up(unsigned int cpu)
	324	{
6b3087c6	325	int ret;
0b39db28 GY	326	static struct task_struct *idle;
	327
	328	if (idle)
	329	free_task(idle);
6b3087c6 GY	330
	331	idle = fork_idle(cpu);
	332	if (IS_ERR(idle)) {
	333	printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
	334	return PTR_ERR(idle);
	335	}
	336
	337	secondary_stack = task_stack_page(idle) + THREAD_SIZE;
6b3087c6 GY	338
	339	ret = platform_boot_secondary(cpu, idle);
	340
6b3087c6 GY	341	secondary_stack = NULL;
	342
	343	return ret;
	344	}
	345
	346	static void __cpuinit setup_secondary(unsigned int cpu)
	347	{
6b3087c6 GY	348	unsigned long ilat;
	349
	350	bfin_write_IMASK(0);
	351	CSYNC();
	352	ilat = bfin_read_ILAT();
	353	CSYNC();
	354	bfin_write_ILAT(ilat);
	355	CSYNC();
	356
6b3087c6 GY	357	/* Enable interrupt levels IVG7-15. IARs have been already
6b3087c6 GY	358	* programmed by the boot CPU. */
40059784	359	bfin_irq_flags \|= IMASK_IVG15 \|
6b3087c6 GY	360	IMASK_IVG14 \| IMASK_IVG13 \| IMASK_IVG12 \| IMASK_IVG11 \|
6b3087c6 GY	361	IMASK_IVG10 \| IMASK_IVG9 \| IMASK_IVG8 \| IMASK_IVG7 \| IMASK_IVGHW;
6b3087c6 GY	362	}
	363
	364	void __cpuinit secondary_start_kernel(void)
	365	{
	366	unsigned int cpu = smp_processor_id();
	367	struct mm_struct *mm = &init_mm;
	368
	369	if (_bfin_swrst & SWRST_DBL_FAULT_B) {
	370	printk(KERN_EMERG "CoreB Recovering from DOUBLE FAULT event\n");
	371	#ifdef CONFIG_DEBUG_DOUBLEFAULT
	372	printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
	373	(int)init_saved_seqstat_coreb & SEQSTAT_EXCAUSE, init_saved_retx_coreb);
	374	printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr_coreb);
	375	printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr_coreb);
	376	#endif
	377	printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
	378	init_retx_coreb);
	379	}
	380
	381	/*
	382	* We want the D-cache to be enabled early, in case the atomic
	383	* support code emulates cache coherence (see
	384	* __ARCH_SYNC_CORE_DCACHE).
	385	*/
	386	init_exception_vectors();
	387
6b3087c6 GY	388	local_irq_disable();
	389
	390	/* Attach the new idle task to the global mm. */
	391	atomic_inc(&mm->mm_users);
	392	atomic_inc(&mm->mm_count);
	393	current->active_mm = mm;
6b3087c6 GY	394
	395	preempt_disable();
	396
	397	setup_secondary(cpu);
	398
578d36f5 YL	399	platform_secondary_init(cpu);
578d36f5 YL	400
0d152c27 YL	401	/* setup local core timer */
	402	bfin_local_timer_setup();
	403
6b3087c6 GY	404	local_irq_enable();
6b3087c6 GY	405
ab61d2ac	406	bfin_setup_caches(cpu);
ab61d2ac	407
578d36f5 YL	408	/*
	409	* Calibrate loops per jiffy value.
	410	* IRQs need to be enabled here - D-cache can be invalidated
	411	* in timer irq handler, so core B can read correct jiffies.
	412	*/
	413	calibrate_delay();
6b3087c6 GY	414
	415	cpu_idle();
	416	}
	417
	418	void __init smp_prepare_boot_cpu(void)
	419	{
	420	}
	421
	422	void __init smp_prepare_cpus(unsigned int max_cpus)
	423	{
	424	platform_prepare_cpus(max_cpus);
	425	ipi_queue_init();
73a40064 YL	426	platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
73a40064 YL	427	platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
6b3087c6 GY	428	}
	429
	430	void __init smp_cpus_done(unsigned int max_cpus)
	431	{
	432	unsigned long bogosum = 0;
	433	unsigned int cpu;
	434
	435	for_each_online_cpu(cpu)
c70c754f	436	bogosum += loops_per_jiffy;
6b3087c6 GY	437
	438	printk(KERN_INFO "SMP: Total of %d processors activated "
	439	"(%lu.%02lu BogoMIPS).\n",
	440	num_online_cpus(),
	441	bogosum / (500000/HZ),
	442	(bogosum / (5000/HZ)) % 100);
	443	}
	444
	445	void smp_icache_flush_range_others(unsigned long start, unsigned long end)
	446	{
	447	smp_flush_data.start = start;
	448	smp_flush_data.end = end;
	449
0bf3d933	450	if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
6b3087c6 GY	451	printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
	452	}
	453	EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
	454
47e9dedb	455	#ifdef __ARCH_SYNC_CORE_ICACHE
718340f6	456	unsigned long icache_invld_count[NR_CPUS];
47e9dedb SZ	457	void resync_core_icache(void)
	458	{
	459	unsigned int cpu = get_cpu();
	460	blackfin_invalidate_entire_icache();
718340f6	461	icache_invld_count[cpu]++;
47e9dedb SZ	462	put_cpu();
	463	}
	464	EXPORT_SYMBOL(resync_core_icache);
	465	#endif
	466
6b3087c6	467	#ifdef __ARCH_SYNC_CORE_DCACHE
718340f6	468	unsigned long dcache_invld_count[NR_CPUS];
6b3087c6 GY	469	unsigned long barrier_mask __attribute__ ((__section__(".l2.bss")));
	470
	471	void resync_core_dcache(void)
	472	{
	473	unsigned int cpu = get_cpu();
	474	blackfin_invalidate_entire_dcache();
718340f6	475	dcache_invld_count[cpu]++;
6b3087c6 GY	476	put_cpu();
	477	}
	478	EXPORT_SYMBOL(resync_core_dcache);
	479	#endif
0b39db28 GY	480
	481	#ifdef CONFIG_HOTPLUG_CPU
	482	int __cpuexit __cpu_disable(void)
	483	{
	484	unsigned int cpu = smp_processor_id();
	485
	486	if (cpu == 0)
	487	return -EPERM;
	488
	489	set_cpu_online(cpu, false);
	490	return 0;
	491	}
	492
	493	static DECLARE_COMPLETION(cpu_killed);
	494
	495	int __cpuexit __cpu_die(unsigned int cpu)
	496	{
	497	return wait_for_completion_timeout(&cpu_killed, 5000);
	498	}
	499
	500	void cpu_die(void)
	501	{
	502	complete(&cpu_killed);
	503
	504	atomic_dec(&init_mm.mm_users);
	505	atomic_dec(&init_mm.mm_count);
	506
	507	local_irq_disable();
	508	platform_cpu_die();
	509	}
	510	#endif