[deliverable/linux.git] / arch / blackfin / mm / isram-driver.c

/*
 * Description: Instruction SRAM accessor functions for the Blackfin
 *
 * Copyright 2008 Analog Devices Inc.
 *
 * Bugs: Enter bugs at http://blackfin.uclinux.org/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see the file COPYING, or write
 * to the Free Software Foundation, Inc.,
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */

#define pr_fmt(fmt) "isram: " fmt

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/sched.h>

#include <asm/blackfin.h>
#include <asm/dma.h>

/*
 * IMPORTANT WARNING ABOUT THESE FUNCTIONS
 *
 * The emulator will not function correctly if a write command is left in
 * ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
 * the emulator. To avoid such problems, ensure that both ITEST_COMMAND
 * and DTEST_COMMAND are zero when exiting these functions.
 */


/*
 * On the Blackfin, L1 instruction sram (which operates at core speeds) can not
 * be accessed by a normal core load, so we need to go through a few hoops to
 * read/write it.
 * To try to make it easier - we export a memcpy interface, where either src or
 * dest can be in this special L1 memory area.
 * The low level read/write functions should not be exposed to the rest of the
 * kernel, since they operate on 64-bit data, and need specific address alignment
 */

static DEFINE_SPINLOCK(dtest_lock);

/* Takes a void pointer */
#define IADDR2DTEST(x) \
	({ unsigned long __addr = (unsigned long)(x); \
		(__addr & 0x47F8)        | /* address bits 14 & 10:3 */ \
		(__addr & 0x8000) << 23  | /* Bank A/B               */ \
		(__addr & 0x0800) << 15  | /* address bit  11        */ \
		(__addr & 0x3000) <<  4  | /* address bits 13:12     */ \
		(__addr & 0x8000) <<  8  | /* address bit  15        */ \
		(0x1000000)              | /* instruction access = 1 */ \
		(0x4);                     /* data array = 1         */ \
	})

/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)

/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)

static void isram_write(const void *addr, uint64_t data)
{
	uint32_t cmd;
	unsigned long flags;

	if (addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH))
		return;

	cmd = IADDR2DTEST(addr) | 2;             /* write */

	/*
	 * Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
	 * While in exception context - atomicity is guaranteed or double fault
	 */
	spin_lock_irqsave(&dtest_lock, flags);

	bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
	bfin_write_DTEST_DATA1(data >> 32);

	/* use the builtin, since interrupts are already turned off */
	__builtin_bfin_csync();
	bfin_write_DTEST_COMMAND(cmd);
	__builtin_bfin_csync();

	bfin_write_DTEST_COMMAND(0);
	__builtin_bfin_csync();

	spin_unlock_irqrestore(&dtest_lock, flags);
}

static uint64_t isram_read(const void *addr)
{
	uint32_t cmd;
	unsigned long flags;
	uint64_t ret;

	if (addr > (void *)(L1_CODE_START + L1_CODE_LENGTH))
		return 0;

	cmd = IADDR2DTEST(addr) | 0;              /* read */

	/*
	 * Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
	 * While in exception context - atomicity is guaranteed or double fault
	 */
	spin_lock_irqsave(&dtest_lock, flags);
	/* use the builtin, since interrupts are already turned off */
	__builtin_bfin_csync();
	bfin_write_DTEST_COMMAND(cmd);
	__builtin_bfin_csync();
	ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);

	bfin_write_DTEST_COMMAND(0);
	__builtin_bfin_csync();
	spin_unlock_irqrestore(&dtest_lock, flags);

	return ret;
}

static bool isram_check_addr(const void *addr, size_t n)
{
	if ((addr >= (void *)L1_CODE_START) &&
	    (addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
		if ((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH)) {
			show_stack(NULL, NULL);
			pr_err("copy involving %p length (%zu) too long\n", addr, n);
		}
		return true;
	}
	return false;
}

/*
 * The isram_memcpy() function copies n bytes from memory area src to memory area dest.
 * The isram_memcpy() function returns a pointer to dest.
 * Either dest or src can be in L1 instruction sram.
 */
void *isram_memcpy(void *dest, const void *src, size_t n)
{
	uint64_t data_in = 0, data_out = 0;
	size_t count;
	bool dest_in_l1, src_in_l1, need_data, put_data;
	unsigned char byte, *src_byte, *dest_byte;

	src_byte = (unsigned char *)src;
	dest_byte = (unsigned char *)dest;

	dest_in_l1 = isram_check_addr(dest, n);
	src_in_l1 = isram_check_addr(src, n);

	need_data = true;
	put_data = true;
	for (count = 0; count < n; count++) {
		if (src_in_l1) {
			if (need_data) {
				data_in = isram_read(src + count);
				need_data = false;
			}

			if (ADDR2LAST(src + count))
				need_data = true;

			byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);

		} else {
			/* src is in L2 or L3 - so just dereference*/
			byte = src_byte[count];
		}

		if (dest_in_l1) {
			if (put_data) {
				data_out = isram_read(dest + count);
				put_data = false;
			}

			data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
			data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count));

			if (ADDR2LAST(dest + count)) {
				put_data = true;
				isram_write(dest + count, data_out);
			}
		} else {
			/* dest in L2 or L3 - so just dereference */
			dest_byte[count] = byte;
		}
	}

	/* make sure we dump the last byte if necessary */
	if (dest_in_l1 && !put_data)
		isram_write(dest + count, data_out);

	return dest;
}
EXPORT_SYMBOL(isram_memcpy);

#ifdef CONFIG_BFIN_ISRAM_SELF_TEST

#define TEST_LEN 0x100

static __init void hex_dump(unsigned char *buf, int len)
{
	while (len--)
		pr_cont("%02x", *buf++);
}

static __init int isram_read_test(char *sdram, void *l1inst)
{
	int i, ret = 0;
	uint64_t data1, data2;

	pr_info("INFO: running isram_read tests\n");

	/* setup some different data to play with */
	for (i = 0; i < TEST_LEN; ++i)
		sdram[i] = i;
	dma_memcpy(l1inst, sdram, TEST_LEN);

	/* make sure we can read the L1 inst */
	for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) {
		data1 = isram_read(l1inst + i);
		memcpy(&data2, sdram + i, sizeof(data2));
		if (memcmp(&data1, &data2, sizeof(uint64_t))) {
			pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
				l1inst + i, data1, data2);
			++ret;
		}
	}

	return ret;
}

static __init int isram_write_test(char *sdram, void *l1inst)
{
	int i, ret = 0;
	uint64_t data1, data2;

	pr_info("INFO: running isram_write tests\n");

	/* setup some different data to play with */
	memset(sdram, 0, TEST_LEN * 2);
	dma_memcpy(l1inst, sdram, TEST_LEN);
	for (i = 0; i < TEST_LEN; ++i)
		sdram[i] = i;

	/* make sure we can write the L1 inst */
	for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) {
		memcpy(&data1, sdram + i, sizeof(data1));
		isram_write(l1inst + i, data1);
		data2 = isram_read(l1inst + i);
		if (memcmp(&data1, &data2, sizeof(uint64_t))) {
			pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
				l1inst + i, data1, data2);
			++ret;
		}
	}

	dma_memcpy(sdram + TEST_LEN, l1inst, TEST_LEN);
	if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) {
		pr_err("FAIL: isram_write() did not work properly\n");
		++ret;
	}

	return ret;
}

static __init int
_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy,
                   void *(*fmemcpy)(void *, const void *, size_t))
{
	memset(sdram, pattern, TEST_LEN);
	fmemcpy(l1inst, sdram, TEST_LEN);
	fmemcpy(sdram + TEST_LEN, l1inst, TEST_LEN);
	if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) {
		pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
			smemcpy, l1inst, sdram, TEST_LEN, pattern);
		return 1;
	}
	return 0;
}
#define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d)

static __init int isram_memcpy_test(char *sdram, void *l1inst)
{
	int i, j, thisret, ret = 0;

	/* check broad isram_memcpy() */
	pr_info("INFO: running broad isram_memcpy tests\n");
	for (i = 0xf; i >= 0; --i)
		ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy);

	/* check read of small, unaligned, and hardware 64bit limits */
	pr_info("INFO: running isram_memcpy (read) tests\n");

	for (i = 0; i < TEST_LEN; ++i)
		sdram[i] = i;
	dma_memcpy(l1inst, sdram, TEST_LEN);

	thisret = 0;
	for (i = 0; i < TEST_LEN - 32; ++i) {
		unsigned char cmp[32];
		for (j = 1; j <= 32; ++j) {
			memset(cmp, 0, sizeof(cmp));
			isram_memcpy(cmp, l1inst + i, j);
			if (memcmp(cmp, sdram + i, j)) {
				pr_err("FAIL: %p:", l1inst + 1);
				hex_dump(cmp, j);
				pr_cont(" SDRAM:");
				hex_dump(sdram + i, j);
				pr_cont("\n");
				if (++thisret > 20) {
					pr_err("FAIL: skipping remaining series\n");
					i = TEST_LEN;
					break;
				}
			}
		}
	}
	ret += thisret;

	/* check write of small, unaligned, and hardware 64bit limits */
	pr_info("INFO: running isram_memcpy (write) tests\n");

	memset(sdram + TEST_LEN, 0, TEST_LEN);
	dma_memcpy(l1inst, sdram + TEST_LEN, TEST_LEN);

	thisret = 0;
	for (i = 0; i < TEST_LEN - 32; ++i) {
		unsigned char cmp[32];
		for (j = 1; j <= 32; ++j) {
			isram_memcpy(l1inst + i, sdram + i, j);
			dma_memcpy(cmp, l1inst + i, j);
			if (memcmp(cmp, sdram + i, j)) {
				pr_err("FAIL: %p:", l1inst + i);
				hex_dump(cmp, j);
				pr_cont(" SDRAM:");
				hex_dump(sdram + i, j);
				pr_cont("\n");
				if (++thisret > 20) {
					pr_err("FAIL: skipping remaining series\n");
					i = TEST_LEN;
					break;
				}
			}
		}
	}
	ret += thisret;

	return ret;
}

static __init int isram_test_init(void)
{
	int ret;
	char *sdram;
	void *l1inst;

	sdram = kmalloc(TEST_LEN * 2, GFP_KERNEL);
	if (!sdram) {
		pr_warning("SKIP: could not allocate sdram\n");
		return 0;
	}

	l1inst = l1_inst_sram_alloc(TEST_LEN);
	if (!l1inst) {
		kfree(sdram);
		pr_warning("SKIP: could not allocate L1 inst\n");
		return 0;
	}

	/* sanity check initial L1 inst state */
	ret = 1;
	pr_info("INFO: running initial dma_memcpy checks\n");
	if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
		goto abort;
	if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
		goto abort;

	ret = 0;
	ret += isram_read_test(sdram, l1inst);
	ret += isram_write_test(sdram, l1inst);
	ret += isram_memcpy_test(sdram, l1inst);

 abort:
	sram_free(l1inst);
	kfree(sdram);

	if (ret)
		return -EIO;

	pr_info("PASS: all tests worked !\n");
	return 0;
}
late_initcall(isram_test_init);

static __exit void isram_test_exit(void)
{
	/* stub to allow unloading */
}
module_exit(isram_test_exit);

#endif
Commit	Line	Data
9df10281 RG	1	/*
	2	* Description: Instruction SRAM accessor functions for the Blackfin
	3	*
	4	* Copyright 2008 Analog Devices Inc.
	5	*
	6	* Bugs: Enter bugs at http://blackfin.uclinux.org/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, see the file COPYING, or write
	15	* to the Free Software Foundation, Inc.,
	16	* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	17	*/
	18
c40cdb2c MF	19	#define pr_fmt(fmt) "isram: " fmt
c40cdb2c MF	20
9df10281 RG	21	#include <linux/module.h>
	22	#include <linux/kernel.h>
	23	#include <linux/types.h>
	24	#include <linux/spinlock.h>
	25	#include <linux/sched.h>
	26
	27	#include <asm/blackfin.h>
c40cdb2c	28	#include <asm/dma.h>
9df10281 RG	29
	30	/*
	31	* IMPORTANT WARNING ABOUT THESE FUNCTIONS
	32	*
	33	* The emulator will not function correctly if a write command is left in
	34	* ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
	35	* the emulator. To avoid such problems, ensure that both ITEST_COMMAND
	36	* and DTEST_COMMAND are zero when exiting these functions.
	37	*/
	38
	39
	40	/*
	41	* On the Blackfin, L1 instruction sram (which operates at core speeds) can not
	42	* be accessed by a normal core load, so we need to go through a few hoops to
	43	* read/write it.
	44	* To try to make it easier - we export a memcpy interface, where either src or
	45	* dest can be in this special L1 memory area.
	46	* The low level read/write functions should not be exposed to the rest of the
	47	* kernel, since they operate on 64-bit data, and need specific address alignment
	48	*/
	49
	50	static DEFINE_SPINLOCK(dtest_lock);
	51
	52	/* Takes a void pointer */
	53	#define IADDR2DTEST(x) \
	54	({ unsigned long __addr = (unsigned long)(x); \
	55	(__addr & 0x47F8) \| /* address bits 14 & 10:3 */ \
774b8022	56	(__addr & 0x8000) << 23 \| /* Bank A/B */ \
9df10281	57	(__addr & 0x0800) << 15 \| /* address bit 11 */ \
774b8022 RG	58	(__addr & 0x3000) << 4 \| /* address bits 13:12 */ \
	59	(__addr & 0x8000) << 8 \| /* address bit 15 */ \
	60	(0x1000000) \| /* instruction access = 1 */ \
	61	(0x4); /* data array = 1 */ \
9df10281 RG	62	})
	63
	64	/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
	65	#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
	66
	67	/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
	68	#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
	69
	70	static void isram_write(const void *addr, uint64_t data)
	71	{
	72	uint32_t cmd;
	73	unsigned long flags;
	74
	75	if (addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH))
	76	return;
	77
774b8022	78	cmd = IADDR2DTEST(addr) \| 2; /* write */
9df10281 RG	79
	80	/*
	81	* Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
	82	* While in exception context - atomicity is guaranteed or double fault
	83	*/
	84	spin_lock_irqsave(&dtest_lock, flags);
	85
	86	bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
	87	bfin_write_DTEST_DATA1(data >> 32);
	88
	89	/* use the builtin, since interrupts are already turned off */
	90	__builtin_bfin_csync();
	91	bfin_write_DTEST_COMMAND(cmd);
	92	__builtin_bfin_csync();
	93
	94	bfin_write_DTEST_COMMAND(0);
	95	__builtin_bfin_csync();
	96
	97	spin_unlock_irqrestore(&dtest_lock, flags);
	98	}
	99
	100	static uint64_t isram_read(const void *addr)
	101	{
	102	uint32_t cmd;
	103	unsigned long flags;
	104	uint64_t ret;
	105
	106	if (addr > (void *)(L1_CODE_START + L1_CODE_LENGTH))
	107	return 0;
	108
	109	cmd = IADDR2DTEST(addr) \| 0; /* read */
	110
	111	/*
	112	* Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
	113	* While in exception context - atomicity is guaranteed or double fault
	114	*/
	115	spin_lock_irqsave(&dtest_lock, flags);
	116	/* use the builtin, since interrupts are already turned off */
	117	__builtin_bfin_csync();
	118	bfin_write_DTEST_COMMAND(cmd);
	119	__builtin_bfin_csync();
	120	ret = bfin_read_DTEST_DATA0() \| ((uint64_t)bfin_read_DTEST_DATA1() << 32);
	121
	122	bfin_write_DTEST_COMMAND(0);
	123	__builtin_bfin_csync();
	124	spin_unlock_irqrestore(&dtest_lock, flags);
	125
	126	return ret;
	127	}
	128
	129	static bool isram_check_addr(const void *addr, size_t n)
	130	{
	131	if ((addr >= (void *)L1_CODE_START) &&
	132	(addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
4b402e3a	133	if ((addr + n) > (void *)(L1_CODE_START + L1_CODE_LENGTH)) {
9df10281	134	show_stack(NULL, NULL);
c40cdb2c	135	pr_err("copy involving %p length (%zu) too long\n", addr, n);
9df10281 RG	136	}
	137	return true;
	138	}
	139	return false;
	140	}
	141
	142	/*
	143	* The isram_memcpy() function copies n bytes from memory area src to memory area dest.
	144	* The isram_memcpy() function returns a pointer to dest.
	145	* Either dest or src can be in L1 instruction sram.
	146	*/
	147	void isram_memcpy(void dest, const void *src, size_t n)
	148	{
	149	uint64_t data_in = 0, data_out = 0;
	150	size_t count;
	151	bool dest_in_l1, src_in_l1, need_data, put_data;
	152	unsigned char byte, src_byte, dest_byte;
	153
	154	src_byte = (unsigned char *)src;
	155	dest_byte = (unsigned char *)dest;
	156
	157	dest_in_l1 = isram_check_addr(dest, n);
	158	src_in_l1 = isram_check_addr(src, n);
	159
	160	need_data = true;
	161	put_data = true;
	162	for (count = 0; count < n; count++) {
	163	if (src_in_l1) {
	164	if (need_data) {
	165	data_in = isram_read(src + count);
	166	need_data = false;
	167	}
	168
	169	if (ADDR2LAST(src + count))
	170	need_data = true;
	171
	172	byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);
	173
	174	} else {
	175	/* src is in L2 or L3 - so just dereference*/
	176	byte = src_byte[count];
	177	}
	178
	179	if (dest_in_l1) {
	180	if (put_data) {
	181	data_out = isram_read(dest + count);
	182	put_data = false;
	183	}
	184
	185	data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
	186	data_out \|= ((uint64_t)byte << ADDR2OFFSET(dest + count));
	187
	188	if (ADDR2LAST(dest + count)) {
	189	put_data = true;
	190	isram_write(dest + count, data_out);
	191	}
	192	} else {
	193	/* dest in L2 or L3 - so just dereference */
	194	dest_byte[count] = byte;
	195	}
	196	}
	197
	198	/* make sure we dump the last byte if necessary */
	199	if (dest_in_l1 && !put_data)
200	isram_write(dest + count, data_out);
201
202	return dest;
203	}
204	EXPORT_SYMBOL(isram_memcpy);
205
c40cdb2c MF	206	#ifdef CONFIG_BFIN_ISRAM_SELF_TEST
	207
	208	#define TEST_LEN 0x100
	209
	210	static __init void hex_dump(unsigned char *buf, int len)
	211	{
	212	while (len--)
	213	pr_cont("%02x", *buf++);
	214	}
	215
	216	static __init int isram_read_test(char sdram, void l1inst)
	217	{
	218	int i, ret = 0;
	219	uint64_t data1, data2;
	220
	221	pr_info("INFO: running isram_read tests\n");
	222
	223	/* setup some different data to play with */
	224	for (i = 0; i < TEST_LEN; ++i)
	225	sdram[i] = i;
	226	dma_memcpy(l1inst, sdram, TEST_LEN);
	227
	228	/* make sure we can read the L1 inst */
	229	for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) {
	230	data1 = isram_read(l1inst + i);
	231	memcpy(&data2, sdram + i, sizeof(data2));
	232	if (memcmp(&data1, &data2, sizeof(uint64_t))) {
	233	pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
	234	l1inst + i, data1, data2);
	235	++ret;
	236	}
	237	}
	238
	239	return ret;
	240	}
	241
	242	static __init int isram_write_test(char sdram, void l1inst)
	243	{
	244	int i, ret = 0;
	245	uint64_t data1, data2;
	246
	247	pr_info("INFO: running isram_write tests\n");
	248
	249	/* setup some different data to play with */
	250	memset(sdram, 0, TEST_LEN * 2);
	251	dma_memcpy(l1inst, sdram, TEST_LEN);
	252	for (i = 0; i < TEST_LEN; ++i)
	253	sdram[i] = i;
	254
	255	/* make sure we can write the L1 inst */
	256	for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) {
	257	memcpy(&data1, sdram + i, sizeof(data1));
	258	isram_write(l1inst + i, data1);
	259	data2 = isram_read(l1inst + i);
	260	if (memcmp(&data1, &data2, sizeof(uint64_t))) {
	261	pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
	262	l1inst + i, data1, data2);
	263	++ret;
	264	}
	265	}
	266
	267	dma_memcpy(sdram + TEST_LEN, l1inst, TEST_LEN);
	268	if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) {
	269	pr_err("FAIL: isram_write() did not work properly\n");
270	++ret;
271	}
272
273	return ret;
274	}
275
276	static __init int
277	_isram_memcpy_test(char pattern, void sdram, void l1inst, const char *smemcpy,
278	void (fmemcpy)(void , const void , size_t))
279	{
280	memset(sdram, pattern, TEST_LEN);
281	fmemcpy(l1inst, sdram, TEST_LEN);
282	fmemcpy(sdram + TEST_LEN, l1inst, TEST_LEN);
283	if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) {
284	pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
285	smemcpy, l1inst, sdram, TEST_LEN, pattern);
286	return 1;
287	}
288	return 0;
289	}
290	#define _isram_memcpy_test(a, b, c, d) _isram_memcpy_test(a, b, c, #d, d)
291
292	static __init int isram_memcpy_test(char sdram, void l1inst)
293	{
294	int i, j, thisret, ret = 0;
295
296	/* check broad isram_memcpy() */
297	pr_info("INFO: running broad isram_memcpy tests\n");
298	for (i = 0xf; i >= 0; --i)
299	ret += _isram_memcpy_test(i, sdram, l1inst, isram_memcpy);
300
301	/* check read of small, unaligned, and hardware 64bit limits */
302	pr_info("INFO: running isram_memcpy (read) tests\n");
303
304	for (i = 0; i < TEST_LEN; ++i)
305	sdram[i] = i;
306	dma_memcpy(l1inst, sdram, TEST_LEN);
307
308	thisret = 0;
309	for (i = 0; i < TEST_LEN - 32; ++i) {
310	unsigned char cmp[32];
311	for (j = 1; j <= 32; ++j) {
312	memset(cmp, 0, sizeof(cmp));
313	isram_memcpy(cmp, l1inst + i, j);
314	if (memcmp(cmp, sdram + i, j)) {
315	pr_err("FAIL: %p:", l1inst + 1);
316	hex_dump(cmp, j);
317	pr_cont(" SDRAM:");
318	hex_dump(sdram + i, j);
319	pr_cont("\n");
320	if (++thisret > 20) {
321	pr_err("FAIL: skipping remaining series\n");
322	i = TEST_LEN;
323	break;
324	}
325	}
326	}
327	}
328	ret += thisret;
329
330	/* check write of small, unaligned, and hardware 64bit limits */
331	pr_info("INFO: running isram_memcpy (write) tests\n");
332
333	memset(sdram + TEST_LEN, 0, TEST_LEN);
334	dma_memcpy(l1inst, sdram + TEST_LEN, TEST_LEN);
335
336	thisret = 0;
337	for (i = 0; i < TEST_LEN - 32; ++i) {
338	unsigned char cmp[32];
339	for (j = 1; j <= 32; ++j) {
340	isram_memcpy(l1inst + i, sdram + i, j);
341	dma_memcpy(cmp, l1inst + i, j);
342	if (memcmp(cmp, sdram + i, j)) {
343	pr_err("FAIL: %p:", l1inst + i);
344	hex_dump(cmp, j);
345	pr_cont(" SDRAM:");
346	hex_dump(sdram + i, j);
347	pr_cont("\n");
348	if (++thisret > 20) {
349	pr_err("FAIL: skipping remaining series\n");
350	i = TEST_LEN;
351	break;
352	}
353	}
354	}
355	}
356	ret += thisret;
357
358	return ret;
359	}
360
361	static __init int isram_test_init(void)
362	{
363	int ret;
364	char *sdram;
365	void *l1inst;
366
367	sdram = kmalloc(TEST_LEN * 2, GFP_KERNEL);
368	if (!sdram) {
369	pr_warning("SKIP: could not allocate sdram\n");
370	return 0;
371	}
372
373	l1inst = l1_inst_sram_alloc(TEST_LEN);
374	if (!l1inst) {
375	kfree(sdram);
376	pr_warning("SKIP: could not allocate L1 inst\n");
377	return 0;
378	}
379
380	/* sanity check initial L1 inst state */
381	ret = 1;
382	pr_info("INFO: running initial dma_memcpy checks\n");
383	if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
384	goto abort;
385	if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
386	goto abort;
387
388	ret = 0;
389	ret += isram_read_test(sdram, l1inst);
390	ret += isram_write_test(sdram, l1inst);
391	ret += isram_memcpy_test(sdram, l1inst);
392
393	abort:
394	sram_free(l1inst);
395	kfree(sdram);
396
397	if (ret)
398	return -EIO;
399
400	pr_info("PASS: all tests worked !\n");
401	return 0;
402	}
403	late_initcall(isram_test_init);
404
405	static __exit void isram_test_exit(void)
406	{
407	/* stub to allow unloading */
408	}
409	module_exit(isram_test_exit);
410
411	#endif