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CRIS v32: remove I2C bitbanging driver
[deliverable/linux.git] / arch / cris / arch-v32 / drivers / mach-fs / gpio.c
CommitLineData
6107c61f
JN		 1/*
2 * ETRAX CRISv32 general port I/O device
3 *
4 * Copyright (c) 1999-2006 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen (initial version)
7 * Ola Knutsson (LED handling)
8 * Johan Adolfsson (read/set directions, write, port G,
9 * port to ETRAX FS.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/sched.h>
15#include <linux/slab.h>
16#include <linux/ioport.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/fs.h>
20#include <linux/string.h>
21#include <linux/poll.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/spinlock.h>
0890b588 25#include <linux/mutex.h>
6107c61f
JN		 26
27#include <asm/etraxgpio.h>
28#include <hwregs/reg_map.h>
29#include <hwregs/reg_rdwr.h>
30#include <hwregs/gio_defs.h>
31#include <hwregs/intr_vect_defs.h>
32#include <asm/io.h>
6107c61f
JN		 33#include <asm/irq.h>
34
35#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
36#include "../i2c.h"
37
38#define VIRT_I2C_ADDR 0x40
39#endif
40
41/* The following gio ports on ETRAX FS is available:
42 * pa 8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge
43 * pb 18 bits
44 * pc 18 bits
45 * pd 18 bits
46 * pe 18 bits
47 * each port has a rw_px_dout, r_px_din and rw_px_oe register.
48 */
49
50#define GPIO_MAJOR 120 /* experimental MAJOR number */
51
52#define D(x)
53
54#if 0
55static int dp_cnt;
56#define DP(x) \
57 do { \
58 dp_cnt++; \
59 if (dp_cnt % 1000 == 0) \
60 x; \
61 } while (0)
62#else
63#define DP(x)
64#endif
65
0890b588 66static DEFINE_MUTEX(gpio_mutex);
6107c61f
JN		 67static char gpio_name[] = "etrax gpio";
68
69#if 0
70static wait_queue_head_t *gpio_wq;
71#endif
72
73#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
74static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
75 unsigned long arg);
76#endif
90276a1a 77static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
6107c61f
JN		 78static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
79 loff_t *off);
80static int gpio_open(struct inode *inode, struct file *filp);
81static int gpio_release(struct inode *inode, struct file *filp);
82static unsigned int gpio_poll(struct file *filp,
83 struct poll_table_struct *wait);
84
85/* private data per open() of this driver */
86
87struct gpio_private {
88 struct gpio_private *next;
89 /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
90 unsigned char clk_mask;
91 unsigned char data_mask;
92 unsigned char write_msb;
93 unsigned char pad1;
94 /* These fields are generic */
95 unsigned long highalarm, lowalarm;
96 wait_queue_head_t alarm_wq;
97 int minor;
98};
99
100/* linked list of alarms to check for */
101
102static struct gpio_private *alarmlist;
103
104static int gpio_some_alarms; /* Set if someone uses alarm */
105static unsigned long gpio_pa_high_alarms;
106static unsigned long gpio_pa_low_alarms;
107
108static DEFINE_SPINLOCK(alarm_lock);
109
110#define NUM_PORTS (GPIO_MINOR_LAST+1)
111#define GIO_REG_RD_ADDR(reg) \
112 (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
113#define GIO_REG_WR_ADDR(reg) \
114 (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
115unsigned long led_dummy;
116#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
117static unsigned long virtual_dummy;
118static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
119static unsigned short cached_virtual_gpio_read;
120#endif
121
122static volatile unsigned long *data_out[NUM_PORTS] = {
123 GIO_REG_WR_ADDR(rw_pa_dout),
124 GIO_REG_WR_ADDR(rw_pb_dout),
125 &led_dummy,
126 GIO_REG_WR_ADDR(rw_pc_dout),
127 GIO_REG_WR_ADDR(rw_pd_dout),
128 GIO_REG_WR_ADDR(rw_pe_dout),
129#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
130 &virtual_dummy,
131#endif
132};
133
134static volatile unsigned long *data_in[NUM_PORTS] = {
135 GIO_REG_RD_ADDR(r_pa_din),
136 GIO_REG_RD_ADDR(r_pb_din),
137 &led_dummy,
138 GIO_REG_RD_ADDR(r_pc_din),
139 GIO_REG_RD_ADDR(r_pd_din),
140 GIO_REG_RD_ADDR(r_pe_din),
141#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
142 &virtual_dummy,
143#endif
144};
145
146static unsigned long changeable_dir[NUM_PORTS] = {
147 CONFIG_ETRAX_PA_CHANGEABLE_DIR,
148 CONFIG_ETRAX_PB_CHANGEABLE_DIR,
149 0,
150 CONFIG_ETRAX_PC_CHANGEABLE_DIR,
151 CONFIG_ETRAX_PD_CHANGEABLE_DIR,
152 CONFIG_ETRAX_PE_CHANGEABLE_DIR,
153#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
154 CONFIG_ETRAX_PV_CHANGEABLE_DIR,
155#endif
156};
157
158static unsigned long changeable_bits[NUM_PORTS] = {
159 CONFIG_ETRAX_PA_CHANGEABLE_BITS,
160 CONFIG_ETRAX_PB_CHANGEABLE_BITS,
161 0,
162 CONFIG_ETRAX_PC_CHANGEABLE_BITS,
163 CONFIG_ETRAX_PD_CHANGEABLE_BITS,
164 CONFIG_ETRAX_PE_CHANGEABLE_BITS,
165#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
166 CONFIG_ETRAX_PV_CHANGEABLE_BITS,
167#endif
168};
169
170static volatile unsigned long *dir_oe[NUM_PORTS] = {
171 GIO_REG_WR_ADDR(rw_pa_oe),
172 GIO_REG_WR_ADDR(rw_pb_oe),
173 &led_dummy,
174 GIO_REG_WR_ADDR(rw_pc_oe),
175 GIO_REG_WR_ADDR(rw_pd_oe),
176 GIO_REG_WR_ADDR(rw_pe_oe),
177#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
178 &virtual_rw_pv_oe,
179#endif
180};
181
182
183
2c30da71 184static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
6107c61f
JN		 185{
186 unsigned int mask = 0;
16bc0fe5 187 struct gpio_private *priv = file->private_data;
6107c61f
JN		 188 unsigned long data;
189 poll_wait(file, &priv->alarm_wq, wait);
190 if (priv->minor == GPIO_MINOR_A) {
191 reg_gio_rw_intr_cfg intr_cfg;
192 unsigned long tmp;
193 unsigned long flags;
194
195 local_irq_save(flags);
196 data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din,
197 REG_RD(gio, regi_gio, r_pa_din));
198 /* PA has support for interrupt
199 * lets activate high for those low and with highalarm set
200 */
201 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
202
203 tmp = ~data & priv->highalarm & 0xFF;
204 if (tmp & (1 << 0))
205 intr_cfg.pa0 = regk_gio_hi;
206 if (tmp & (1 << 1))
207 intr_cfg.pa1 = regk_gio_hi;
208 if (tmp & (1 << 2))
209 intr_cfg.pa2 = regk_gio_hi;
210 if (tmp & (1 << 3))
211 intr_cfg.pa3 = regk_gio_hi;
212 if (tmp & (1 << 4))
213 intr_cfg.pa4 = regk_gio_hi;
214 if (tmp & (1 << 5))
215 intr_cfg.pa5 = regk_gio_hi;
216 if (tmp & (1 << 6))
217 intr_cfg.pa6 = regk_gio_hi;
218 if (tmp & (1 << 7))
219 intr_cfg.pa7 = regk_gio_hi;
220 /*
221 * lets activate low for those high and with lowalarm set
222 */
223 tmp = data & priv->lowalarm & 0xFF;
224 if (tmp & (1 << 0))
225 intr_cfg.pa0 = regk_gio_lo;
226 if (tmp & (1 << 1))
227 intr_cfg.pa1 = regk_gio_lo;
228 if (tmp & (1 << 2))
229 intr_cfg.pa2 = regk_gio_lo;
230 if (tmp & (1 << 3))
231 intr_cfg.pa3 = regk_gio_lo;
232 if (tmp & (1 << 4))
233 intr_cfg.pa4 = regk_gio_lo;
234 if (tmp & (1 << 5))
235 intr_cfg.pa5 = regk_gio_lo;
236 if (tmp & (1 << 6))
237 intr_cfg.pa6 = regk_gio_lo;
238 if (tmp & (1 << 7))
239 intr_cfg.pa7 = regk_gio_lo;
240
241 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
242 local_irq_restore(flags);
243 } else if (priv->minor <= GPIO_MINOR_E)
244 data = *data_in[priv->minor];
245 else
246 return 0;
247
248 if ((data & priv->highalarm) || (~data & priv->lowalarm))
249 mask = POLLIN|POLLRDNORM;
250
251 DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
252 return mask;
253}
254
255int etrax_gpio_wake_up_check(void)
256{
257 struct gpio_private *priv;
258 unsigned long data = 0;
259 unsigned long flags;
260 int ret = 0;
261 spin_lock_irqsave(&alarm_lock, flags);
262 priv = alarmlist;
263 while (priv) {
264#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
265 if (priv->minor == GPIO_MINOR_V)
266 data = (unsigned long)cached_virtual_gpio_read;
267 else {
268 data = *data_in[priv->minor];
269 if (priv->minor == GPIO_MINOR_A)
270 priv->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
271 }
272#else
273 data = *data_in[priv->minor];
274#endif
275 if ((data & priv->highalarm) ||
276 (~data & priv->lowalarm)) {
277 DP(printk(KERN_DEBUG
278 "etrax_gpio_wake_up_check %i\n", priv->minor));
279 wake_up_interruptible(&priv->alarm_wq);
280 ret = 1;
281 }
282 priv = priv->next;
283 }
284 spin_unlock_irqrestore(&alarm_lock, flags);
285 return ret;
286}
287
288static irqreturn_t
289gpio_poll_timer_interrupt(int irq, void *dev_id)
290{
291 if (gpio_some_alarms)
292 return IRQ_RETVAL(etrax_gpio_wake_up_check());
293 return IRQ_NONE;
294}
295
296static irqreturn_t
297gpio_pa_interrupt(int irq, void *dev_id)
298{
299 reg_gio_rw_intr_mask intr_mask;
300 reg_gio_r_masked_intr masked_intr;
301 reg_gio_rw_ack_intr ack_intr;
302 unsigned long tmp;
303 unsigned long tmp2;
304#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
305 unsigned char enable_gpiov_ack = 0;
306#endif
307
308 /* Find what PA interrupts are active */
309 masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
310 tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
311
312 /* Find those that we have enabled */
313 spin_lock(&alarm_lock);
314 tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms);
315 spin_unlock(&alarm_lock);
316
317#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
318 /* Something changed on virtual GPIO. Interrupt is acked by
319 * reading the device.
320 */
321 if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
322 i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
323 sizeof(cached_virtual_gpio_read));
324 enable_gpiov_ack = 1;
325 }
326#endif
327
328 /* Ack them */
329 ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
330 REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
331
332 /* Disable those interrupts.. */
333 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
334 tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
335 tmp2 &= ~tmp;
336#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
337 /* Do not disable interrupt on virtual GPIO. Changes on virtual
338 * pins are only noticed by an interrupt.
339 */
340 if (enable_gpiov_ack)
341 tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
342#endif
343 intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
344 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
345
346 if (gpio_some_alarms)
347 return IRQ_RETVAL(etrax_gpio_wake_up_check());
348 return IRQ_NONE;
349}
350
351
352static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
353 loff_t *off)
354{
16bc0fe5 355 struct gpio_private *priv = file->private_data;
6107c61f
JN		 356 unsigned char data, clk_mask, data_mask, write_msb;
357 unsigned long flags;
358 unsigned long shadow;
359 volatile unsigned long *port;
360 ssize_t retval = count;
361 /* Only bits 0-7 may be used for write operations but allow all
362 devices except leds... */
363#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
364 if (priv->minor == GPIO_MINOR_V)
365 return -EFAULT;
366#endif
367 if (priv->minor == GPIO_MINOR_LEDS)
368 return -EFAULT;
369
370 if (!access_ok(VERIFY_READ, buf, count))
371 return -EFAULT;
372 clk_mask = priv->clk_mask;
373 data_mask = priv->data_mask;
374 /* It must have been configured using the IO_CFG_WRITE_MODE */
375 /* Perhaps a better error code? */
376 if (clk_mask == 0 || data_mask == 0)
377 return -EPERM;
378 write_msb = priv->write_msb;
379 D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
380 "msb: %i\n", count, data_mask, clk_mask, write_msb));
381 port = data_out[priv->minor];
382
383 while (count--) {
384 int i;
385 data = *buf++;
386 if (priv->write_msb) {
387 for (i = 7; i >= 0; i--) {
388 local_irq_save(flags);
389 shadow = *port;
390 *port = shadow &= ~clk_mask;
391 if (data & 1<<i)
392 *port = shadow |= data_mask;
393 else
394 *port = shadow &= ~data_mask;
395 /* For FPGA: min 5.0ns (DCC) before CCLK high */
396 *port = shadow |= clk_mask;
397 local_irq_restore(flags);
398 }
399 } else {
400 for (i = 0; i <= 7; i++) {
401 local_irq_save(flags);
402 shadow = *port;
403 *port = shadow &= ~clk_mask;
404 if (data & 1<<i)
405 *port = shadow |= data_mask;
406 else
407 *port = shadow &= ~data_mask;
408 /* For FPGA: min 5.0ns (DCC) before CCLK high */
409 *port = shadow |= clk_mask;
410 local_irq_restore(flags);
411 }
412 }
413 }
414 return retval;
415}
416
417
418
419static int
420gpio_open(struct inode *inode, struct file *filp)
421{
422 struct gpio_private *priv;
423 int p = iminor(inode);
424
425 if (p > GPIO_MINOR_LAST)
426 return -EINVAL;
427
6a4756f6 428 priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
6107c61f
JN		 429 if (!priv)
430 return -ENOMEM;
0c401df3 431
0890b588 432 mutex_lock(&gpio_mutex);
6107c61f
JN		 433
434 priv->minor = p;
435
436 /* initialize the io/alarm struct */
437
438 priv->clk_mask = 0;
439 priv->data_mask = 0;
440 priv->highalarm = 0;
441 priv->lowalarm = 0;
442 init_waitqueue_head(&priv->alarm_wq);
443
444 filp->private_data = (void *)priv;
445
446 /* link it into our alarmlist */
447 spin_lock_irq(&alarm_lock);
448 priv->next = alarmlist;
449 alarmlist = priv;
450 spin_unlock_irq(&alarm_lock);
451
0890b588 452 mutex_unlock(&gpio_mutex);
6107c61f
JN		 453 return 0;
454}
455
456static int
457gpio_release(struct inode *inode, struct file *filp)
458{
459 struct gpio_private *p;
460 struct gpio_private *todel;
461 /* local copies while updating them: */
462 unsigned long a_high, a_low;
463 unsigned long some_alarms;
464
465 /* unlink from alarmlist and free the private structure */
466
467 spin_lock_irq(&alarm_lock);
468 p = alarmlist;
16bc0fe5 469 todel = filp->private_data;
6107c61f
JN		 470
471 if (p == todel) {
472 alarmlist = todel->next;
473 } else {
474 while (p->next != todel)
475 p = p->next;
476 p->next = todel->next;
477 }
478
479 kfree(todel);
480 /* Check if there are still any alarms set */
481 p = alarmlist;
482 some_alarms = 0;
483 a_high = 0;
484 a_low = 0;
485 while (p) {
486 if (p->minor == GPIO_MINOR_A) {
487#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
488 p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
489#endif
490 a_high |= p->highalarm;
491 a_low |= p->lowalarm;
492 }
493
494 if (p->highalarm | p->lowalarm)
495 some_alarms = 1;
496 p = p->next;
497 }
498
499#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
500 /* Variables 'some_alarms' and 'a_low' needs to be set here again
501 * to ensure that interrupt for virtual GPIO is handled.
502 */
503 some_alarms = 1;
504 a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
505#endif
506
507 gpio_some_alarms = some_alarms;
508 gpio_pa_high_alarms = a_high;
509 gpio_pa_low_alarms = a_low;
510 spin_unlock_irq(&alarm_lock);
511
512 return 0;
513}
514
515/* Main device API. ioctl's to read/set/clear bits, as well as to
516 * set alarms to wait for using a subsequent select().
517 */
518
519inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
520{
521 /* Set direction 0=unchanged 1=input,
522 * return mask with 1=input
523 */
524 unsigned long flags;
525 unsigned long dir_shadow;
526
527 local_irq_save(flags);
528 dir_shadow = *dir_oe[priv->minor];
529 dir_shadow &= ~(arg & changeable_dir[priv->minor]);
530 *dir_oe[priv->minor] = dir_shadow;
531 local_irq_restore(flags);
532
533 if (priv->minor == GPIO_MINOR_A)
534 dir_shadow ^= 0xFF; /* Only 8 bits */
535#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
536 else if (priv->minor == GPIO_MINOR_V)
537 dir_shadow ^= 0xFFFF; /* Only 16 bits */
538#endif
539 else
540 dir_shadow ^= 0x3FFFF; /* Only 18 bits */
541 return dir_shadow;
542
543} /* setget_input */
544
545inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
546{
547 unsigned long flags;
548 unsigned long dir_shadow;
549
550 local_irq_save(flags);
551 dir_shadow = *dir_oe[priv->minor];
552 dir_shadow |= (arg & changeable_dir[priv->minor]);
553 *dir_oe[priv->minor] = dir_shadow;
554 local_irq_restore(flags);
555 return dir_shadow;
556} /* setget_output */
557
90276a1a 558static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
6107c61f
JN		 559
560static int
90276a1a 561gpio_ioctl_unlocked(struct file *file, unsigned int cmd, unsigned long arg)
6107c61f
JN		 562{
563 unsigned long flags;
564 unsigned long val;
565 unsigned long shadow;
16bc0fe5 566 struct gpio_private *priv = file->private_data;
6107c61f
JN		 567 if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
568 return -EINVAL;
569
570#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
571 if (priv->minor == GPIO_MINOR_V)
572 return virtual_gpio_ioctl(file, cmd, arg);
573#endif
574
575 switch (_IOC_NR(cmd)) {
576 case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
577 /* Read the port. */
578 return *data_in[priv->minor];
579 break;
580 case IO_SETBITS:
581 local_irq_save(flags);
582 /* Set changeable bits with a 1 in arg. */
583 shadow = *data_out[priv->minor];
584 shadow |= (arg & changeable_bits[priv->minor]);
585 *data_out[priv->minor] = shadow;
586 local_irq_restore(flags);
587 break;
588 case IO_CLRBITS:
589 local_irq_save(flags);
590 /* Clear changeable bits with a 1 in arg. */
591 shadow = *data_out[priv->minor];
592 shadow &= ~(arg & changeable_bits[priv->minor]);
593 *data_out[priv->minor] = shadow;
594 local_irq_restore(flags);
595 break;
596 case IO_HIGHALARM:
597 /* Set alarm when bits with 1 in arg go high. */
598 priv->highalarm |= arg;
599 spin_lock_irqsave(&alarm_lock, flags);
600 gpio_some_alarms = 1;
601 if (priv->minor == GPIO_MINOR_A)
602 gpio_pa_high_alarms |= arg;
603 spin_unlock_irqrestore(&alarm_lock, flags);
604 break;
605 case IO_LOWALARM:
606 /* Set alarm when bits with 1 in arg go low. */
607 priv->lowalarm |= arg;
608 spin_lock_irqsave(&alarm_lock, flags);
609 gpio_some_alarms = 1;
610 if (priv->minor == GPIO_MINOR_A)
611 gpio_pa_low_alarms |= arg;
612 spin_unlock_irqrestore(&alarm_lock, flags);
613 break;
614 case IO_CLRALARM:
615 /* Clear alarm for bits with 1 in arg. */
616 priv->highalarm &= ~arg;
617 priv->lowalarm &= ~arg;
618 spin_lock_irqsave(&alarm_lock, flags);
619 if (priv->minor == GPIO_MINOR_A) {
620 if (gpio_pa_high_alarms & arg ||
621 gpio_pa_low_alarms & arg)
622 /* Must update the gpio_pa_*alarms masks */
623 ;
624 }
625 spin_unlock_irqrestore(&alarm_lock, flags);
626 break;
627 case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
628 /* Read direction 0=input 1=output */
629 return *dir_oe[priv->minor];
630 case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
631 /* Set direction 0=unchanged 1=input,
632 * return mask with 1=input
633 */
634 return setget_input(priv, arg);
635 break;
636 case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
637 /* Set direction 0=unchanged 1=output,
638 * return mask with 1=output
639 */
640 return setget_output(priv, arg);
641
642 case IO_CFG_WRITE_MODE:
643 {
644 unsigned long dir_shadow;
645 dir_shadow = *dir_oe[priv->minor];
646
647 priv->clk_mask = arg & 0xFF;
648 priv->data_mask = (arg >> 8) & 0xFF;
649 priv->write_msb = (arg >> 16) & 0x01;
650 /* Check if we're allowed to change the bits and
651 * the direction is correct
652 */
653 if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
654 (priv->data_mask & changeable_bits[priv->minor]) &&
655 (priv->clk_mask & dir_shadow) &&
656 (priv->data_mask & dir_shadow))) {
657 priv->clk_mask = 0;
658 priv->data_mask = 0;
659 return -EPERM;
660 }
661 break;
662 }
663 case IO_READ_INBITS:
664 /* *arg is result of reading the input pins */
665 val = *data_in[priv->minor];
666 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
667 return -EFAULT;
668 return 0;
669 break;
670 case IO_READ_OUTBITS:
671 /* *arg is result of reading the output shadow */
672 val = *data_out[priv->minor];
673 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
674 return -EFAULT;
675 break;
676 case IO_SETGET_INPUT:
677 /* bits set in *arg is set to input,
678 * *arg updated with current input pins.
679 */
680 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
681 return -EFAULT;
682 val = setget_input(priv, val);
683 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
684 return -EFAULT;
685 break;
686 case IO_SETGET_OUTPUT:
687 /* bits set in *arg is set to output,
688 * *arg updated with current output pins.
689 */
690 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
691 return -EFAULT;
692 val = setget_output(priv, val);
693 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
694 return -EFAULT;
695 break;
696 default:
697 if (priv->minor == GPIO_MINOR_LEDS)
698 return gpio_leds_ioctl(cmd, arg);
699 else
700 return -EINVAL;
701 } /* switch */
702
703 return 0;
704}
705
90276a1a
JN		 706static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
707{
708 long ret;
709
0890b588 710 mutex_lock(&gpio_mutex);
90276a1a 711 ret = gpio_ioctl_unlocked(file, cmd, arg);
0890b588 712 mutex_unlock(&gpio_mutex);
90276a1a
JN		 713
714 return ret;
715}
716
6107c61f
JN		 717#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
718static int
719virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
720{
721 unsigned long flags;
722 unsigned short val;
723 unsigned short shadow;
16bc0fe5 724 struct gpio_private *priv = file->private_data;
6107c61f
JN		 725
726 switch (_IOC_NR(cmd)) {
727 case IO_SETBITS:
728 local_irq_save(flags);
729 /* Set changeable bits with a 1 in arg. */
730 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
731 shadow |= ~*dir_oe[priv->minor];
732 shadow |= (arg & changeable_bits[priv->minor]);
733 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
734 local_irq_restore(flags);
735 break;
736 case IO_CLRBITS:
737 local_irq_save(flags);
738 /* Clear changeable bits with a 1 in arg. */
739 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
740 shadow |= ~*dir_oe[priv->minor];
741 shadow &= ~(arg & changeable_bits[priv->minor]);
742 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
743 local_irq_restore(flags);
744 break;
745 case IO_HIGHALARM:
746 /* Set alarm when bits with 1 in arg go high. */
747 priv->highalarm |= arg;
748 spin_lock(&alarm_lock);
749 gpio_some_alarms = 1;
750 spin_unlock(&alarm_lock);
751 break;
752 case IO_LOWALARM:
753 /* Set alarm when bits with 1 in arg go low. */
754 priv->lowalarm |= arg;
755 spin_lock(&alarm_lock);
756 gpio_some_alarms = 1;
757 spin_unlock(&alarm_lock);
758 break;
759 case IO_CLRALARM:
760 /* Clear alarm for bits with 1 in arg. */
761 priv->highalarm &= ~arg;
762 priv->lowalarm &= ~arg;
763 spin_lock(&alarm_lock);
764 spin_unlock(&alarm_lock);
765 break;
766 case IO_CFG_WRITE_MODE:
767 {
768 unsigned long dir_shadow;
769 dir_shadow = *dir_oe[priv->minor];
770
771 priv->clk_mask = arg & 0xFF;
772 priv->data_mask = (arg >> 8) & 0xFF;
773 priv->write_msb = (arg >> 16) & 0x01;
774 /* Check if we're allowed to change the bits and
775 * the direction is correct
776 */
777 if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
778 (priv->data_mask & changeable_bits[priv->minor]) &&
779 (priv->clk_mask & dir_shadow) &&
780 (priv->data_mask & dir_shadow))) {
781 priv->clk_mask = 0;
782 priv->data_mask = 0;
783 return -EPERM;
784 }
785 break;
786 }
787 case IO_READ_INBITS:
788 /* *arg is result of reading the input pins */
789 val = cached_virtual_gpio_read;
790 val &= ~*dir_oe[priv->minor];
791 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
792 return -EFAULT;
793 return 0;
794 break;
795 case IO_READ_OUTBITS:
796 /* *arg is result of reading the output shadow */
797 i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
798 val &= *dir_oe[priv->minor];
799 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
800 return -EFAULT;
801 break;
802 case IO_SETGET_INPUT:
803 {
804 /* bits set in *arg is set to input,
805 * *arg updated with current input pins.
806 */
807 unsigned short input_mask = ~*dir_oe[priv->minor];
808 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
809 return -EFAULT;
810 val = setget_input(priv, val);
811 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
812 return -EFAULT;
813 if ((input_mask & val) != input_mask) {
814 /* Input pins changed. All ports desired as input
815 * should be set to logic 1.
816 */
817 unsigned short change = input_mask ^ val;
818 i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
819 sizeof(shadow));
820 shadow &= ~change;
821 shadow |= val;
822 i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
823 sizeof(shadow));
824 }
825 break;
826 }
827 case IO_SETGET_OUTPUT:
828 /* bits set in *arg is set to output,
829 * *arg updated with current output pins.
830 */
831 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
832 return -EFAULT;
833 val = setget_output(priv, val);
834 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
835 return -EFAULT;
836 break;
837 default:
838 return -EINVAL;
839 } /* switch */
840 return 0;
841}
842#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
843
844static int
845gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
846{
847 unsigned char green;
848 unsigned char red;
849
850 switch (_IOC_NR(cmd)) {
851 case IO_LEDACTIVE_SET:
852 green = ((unsigned char) arg) & 1;
853 red = (((unsigned char) arg) >> 1) & 1;
2c30da71
JN		 854 CRIS_LED_ACTIVE_SET_G(green);
855 CRIS_LED_ACTIVE_SET_R(red);
6107c61f
JN		 856 break;
857
858 default:
859 return -EINVAL;
860 } /* switch */
861
862 return 0;
863}
864
828c0950 865static const struct file_operations gpio_fops = {
90276a1a
JN		 866 .owner = THIS_MODULE,
867 .poll = gpio_poll,
868 .unlocked_ioctl = gpio_ioctl,
869 .write = gpio_write,
870 .open = gpio_open,
871 .release = gpio_release,
6038f373 872 .llseek = noop_llseek,
6107c61f
JN		 873};
874
875#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
876static void
877virtual_gpio_init(void)
878{
879 reg_gio_rw_intr_cfg intr_cfg;
880 reg_gio_rw_intr_mask intr_mask;
881 unsigned short shadow;
882
883 shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
884 shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
885 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
886
887 /* Set interrupt mask and on what state the interrupt shall trigger.
888 * For virtual gpio the interrupt shall trigger on logic '0'.
889 */
890 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
891 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
892
893 switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
894 case 0:
895 intr_cfg.pa0 = regk_gio_lo;
896 intr_mask.pa0 = regk_gio_yes;
897 break;
898 case 1:
899 intr_cfg.pa1 = regk_gio_lo;
900 intr_mask.pa1 = regk_gio_yes;
901 break;
902 case 2:
903 intr_cfg.pa2 = regk_gio_lo;
904 intr_mask.pa2 = regk_gio_yes;
905 break;
906 case 3:
907 intr_cfg.pa3 = regk_gio_lo;
908 intr_mask.pa3 = regk_gio_yes;
909 break;
910 case 4:
911 intr_cfg.pa4 = regk_gio_lo;
912 intr_mask.pa4 = regk_gio_yes;
913 break;
914 case 5:
915 intr_cfg.pa5 = regk_gio_lo;
916 intr_mask.pa5 = regk_gio_yes;
917 break;
918 case 6:
919 intr_cfg.pa6 = regk_gio_lo;
920 intr_mask.pa6 = regk_gio_yes;
921 break;
922 case 7:
923 intr_cfg.pa7 = regk_gio_lo;
924 intr_mask.pa7 = regk_gio_yes;
925 break;
926 }
927
928 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
929 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
930
931 gpio_pa_low_alarms |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
932 gpio_some_alarms = 1;
933}
934#endif
935
936/* main driver initialization routine, called from mem.c */
937
938static __init int
939gpio_init(void)
940{
941 int res;
942
943 /* do the formalities */
944
945 res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
946 if (res < 0) {
947 printk(KERN_ERR "gpio: couldn't get a major number.\n");
948 return res;
949 }
950
951 /* Clear all leds */
2c30da71
JN		 952 CRIS_LED_NETWORK_GRP0_SET(0);
953 CRIS_LED_NETWORK_GRP1_SET(0);
954 CRIS_LED_ACTIVE_SET(0);
955 CRIS_LED_DISK_READ(0);
956 CRIS_LED_DISK_WRITE(0);
6107c61f
JN		 957
958 printk(KERN_INFO "ETRAX FS GPIO driver v2.5, (c) 2003-2007 "
959 "Axis Communications AB\n");
835eeeed 960 /* We call etrax_gpio_wake_up_check() from timer interrupt */
6107c61f 961 if (request_irq(TIMER0_INTR_VECT, gpio_poll_timer_interrupt,
64d8ad93 962 IRQF_SHARED, "gpio poll", &alarmlist))
6107c61f
JN		 963 printk(KERN_ERR "timer0 irq for gpio\n");
964
965 if (request_irq(GIO_INTR_VECT, gpio_pa_interrupt,
64d8ad93 966 IRQF_SHARED, "gpio PA", &alarmlist))
6107c61f
JN		 967 printk(KERN_ERR "PA irq for gpio\n");
968
969#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
970 virtual_gpio_init();
971#endif
972
973 return res;
974}
975
976/* this makes sure that gpio_init is called during kernel boot */
977
978module_init(gpio_init);
Linux kernel - Deliverables
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