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1da177e4 LT |
1 | /* head-uc-fr555.S: FR555 uc-linux specific bits of initialisation |
2 | * | |
3 | * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. | |
4 | * Written by David Howells (dhowells@redhat.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
df1f6d20 | 12 | #include <linux/init.h> |
1da177e4 LT |
13 | #include <linux/threads.h> |
14 | #include <linux/linkage.h> | |
15 | #include <asm/ptrace.h> | |
16 | #include <asm/page.h> | |
17 | #include <asm/spr-regs.h> | |
18 | #include <asm/mb86943a.h> | |
19 | #include "head.inc" | |
20 | ||
21 | ||
22 | #define __551_DARS0 0xfeff0100 | |
23 | #define __551_DARS1 0xfeff0104 | |
24 | #define __551_DARS2 0xfeff0108 | |
25 | #define __551_DARS3 0xfeff010c | |
26 | #define __551_DAMK0 0xfeff0110 | |
27 | #define __551_DAMK1 0xfeff0114 | |
28 | #define __551_DAMK2 0xfeff0118 | |
29 | #define __551_DAMK3 0xfeff011c | |
30 | #define __551_LCR 0xfeff1100 | |
31 | #define __551_LSBR 0xfeff1c00 | |
32 | ||
df1f6d20 | 33 | __INIT |
1da177e4 LT |
34 | .balign 4 |
35 | ||
36 | ############################################################################### | |
37 | # | |
38 | # describe the position and layout of the SDRAM controller registers | |
39 | # | |
40 | # ENTRY: EXIT: | |
41 | # GR5 - cacheline size | |
42 | # GR11 - displacement of 2nd SDRAM addr reg from GR14 | |
43 | # GR12 - displacement of 3rd SDRAM addr reg from GR14 | |
44 | # GR13 - displacement of 4th SDRAM addr reg from GR14 | |
45 | # GR14 - address of 1st SDRAM addr reg | |
46 | # GR15 - amount to shift address by to match SDRAM addr reg | |
47 | # GR26 &__head_reference [saved] | |
48 | # GR30 LED address [saved] | |
49 | # CC0 - T if DARS0 is present | |
50 | # CC1 - T if DARS1 is present | |
51 | # CC2 - T if DARS2 is present | |
52 | # CC3 - T if DARS3 is present | |
53 | # | |
54 | ############################################################################### | |
55 | .globl __head_fr555_describe_sdram | |
56 | __head_fr555_describe_sdram: | |
57 | sethi.p %hi(__551_DARS0),gr14 | |
58 | setlo %lo(__551_DARS0),gr14 | |
59 | setlos.p #__551_DARS1-__551_DARS0,gr11 | |
60 | setlos #__551_DARS2-__551_DARS0,gr12 | |
61 | setlos.p #__551_DARS3-__551_DARS0,gr13 | |
62 | setlos #64,gr5 ; cacheline size | |
63 | setlos #20,gr15 ; amount to shift addr by | |
64 | setlos #0x00ff,gr4 | |
65 | movgs gr4,cccr ; extant DARS/DAMK regs | |
66 | bralr | |
67 | ||
68 | ############################################################################### | |
69 | # | |
70 | # rearrange the bus controller registers | |
71 | # | |
72 | # ENTRY: EXIT: | |
73 | # GR26 &__head_reference [saved] | |
74 | # GR30 LED address revised LED address | |
75 | # | |
76 | ############################################################################### | |
77 | .globl __head_fr555_set_busctl | |
78 | __head_fr555_set_busctl: | |
79 | LEDS 0x100f | |
80 | sethi.p %hi(__551_LSBR),gr10 | |
81 | setlo %lo(__551_LSBR),gr10 | |
82 | sethi.p %hi(__551_LCR),gr11 | |
83 | setlo %lo(__551_LCR),gr11 | |
84 | ||
85 | # set the bus controller | |
86 | sethi.p %hi(__region_CS1),gr4 | |
87 | setlo %lo(__region_CS1),gr4 | |
88 | sethi.p %hi(__region_CS1_M),gr5 | |
89 | setlo %lo(__region_CS1_M),gr5 | |
90 | sethi.p %hi(__region_CS1_C),gr6 | |
91 | setlo %lo(__region_CS1_C),gr6 | |
92 | sti gr4,@(gr10,#1*0x08) | |
93 | sti gr5,@(gr10,#1*0x08+0x100) | |
94 | sti gr6,@(gr11,#1*0x08) | |
95 | sethi.p %hi(__region_CS2),gr4 | |
96 | setlo %lo(__region_CS2),gr4 | |
97 | sethi.p %hi(__region_CS2_M),gr5 | |
98 | setlo %lo(__region_CS2_M),gr5 | |
99 | sethi.p %hi(__region_CS2_C),gr6 | |
100 | setlo %lo(__region_CS2_C),gr6 | |
101 | sti gr4,@(gr10,#2*0x08) | |
102 | sti gr5,@(gr10,#2*0x08+0x100) | |
103 | sti gr6,@(gr11,#2*0x08) | |
104 | sethi.p %hi(__region_CS3),gr4 | |
105 | setlo %lo(__region_CS3),gr4 | |
106 | sethi.p %hi(__region_CS3_M),gr5 | |
107 | setlo %lo(__region_CS3_M),gr5 | |
108 | sethi.p %hi(__region_CS3_C),gr6 | |
109 | setlo %lo(__region_CS3_C),gr6 | |
110 | sti gr4,@(gr10,#3*0x08) | |
111 | sti gr5,@(gr10,#3*0x08+0x100) | |
112 | sti gr6,@(gr11,#3*0x08) | |
113 | sethi.p %hi(__region_CS4),gr4 | |
114 | setlo %lo(__region_CS4),gr4 | |
115 | sethi.p %hi(__region_CS4_M),gr5 | |
116 | setlo %lo(__region_CS4_M),gr5 | |
117 | sethi.p %hi(__region_CS4_C),gr6 | |
118 | setlo %lo(__region_CS4_C),gr6 | |
119 | sti gr4,@(gr10,#4*0x08) | |
120 | sti gr5,@(gr10,#4*0x08+0x100) | |
121 | sti gr6,@(gr11,#4*0x08) | |
122 | sethi.p %hi(__region_CS5),gr4 | |
123 | setlo %lo(__region_CS5),gr4 | |
124 | sethi.p %hi(__region_CS5_M),gr5 | |
125 | setlo %lo(__region_CS5_M),gr5 | |
126 | sethi.p %hi(__region_CS5_C),gr6 | |
127 | setlo %lo(__region_CS5_C),gr6 | |
128 | sti gr4,@(gr10,#5*0x08) | |
129 | sti gr5,@(gr10,#5*0x08+0x100) | |
130 | sti gr6,@(gr11,#5*0x08) | |
131 | sethi.p %hi(__region_CS6),gr4 | |
132 | setlo %lo(__region_CS6),gr4 | |
133 | sethi.p %hi(__region_CS6_M),gr5 | |
134 | setlo %lo(__region_CS6_M),gr5 | |
135 | sethi.p %hi(__region_CS6_C),gr6 | |
136 | setlo %lo(__region_CS6_C),gr6 | |
137 | sti gr4,@(gr10,#6*0x08) | |
138 | sti gr5,@(gr10,#6*0x08+0x100) | |
139 | sti gr6,@(gr11,#6*0x08) | |
140 | sethi.p %hi(__region_CS7),gr4 | |
141 | setlo %lo(__region_CS7),gr4 | |
142 | sethi.p %hi(__region_CS7_M),gr5 | |
143 | setlo %lo(__region_CS7_M),gr5 | |
144 | sethi.p %hi(__region_CS7_C),gr6 | |
145 | setlo %lo(__region_CS7_C),gr6 | |
146 | sti gr4,@(gr10,#7*0x08) | |
147 | sti gr5,@(gr10,#7*0x08+0x100) | |
148 | sti gr6,@(gr11,#7*0x08) | |
149 | membar | |
150 | bar | |
151 | ||
152 | # adjust LED bank address | |
153 | #ifdef CONFIG_MB93091_VDK | |
154 | sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30 | |
155 | setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30 | |
156 | #endif | |
157 | bralr | |
158 | ||
159 | ############################################################################### | |
160 | # | |
161 | # determine the total SDRAM size | |
162 | # | |
163 | # ENTRY: EXIT: | |
164 | # GR25 - SDRAM size | |
165 | # GR26 &__head_reference [saved] | |
166 | # GR30 LED address [saved] | |
167 | # | |
168 | ############################################################################### | |
169 | .globl __head_fr555_survey_sdram | |
170 | __head_fr555_survey_sdram: | |
171 | sethi.p %hi(__551_DAMK0),gr11 | |
172 | setlo %lo(__551_DAMK0),gr11 | |
173 | sethi.p %hi(__551_DARS0),gr12 | |
174 | setlo %lo(__551_DARS0),gr12 | |
175 | ||
176 | sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value | |
177 | setlo %lo(0xfff),gr17 | |
178 | setlos #0,gr25 | |
179 | ||
180 | ldi @(gr11,#0x00),gr6 ; DAMK0: bits 11:0 match addr 11:0 | |
181 | subcc gr6,gr17,gr0,icc0 | |
182 | beq icc0,#0,__head_no_DCS0 | |
183 | ldi @(gr12,#0x00),gr4 ; DARS0 | |
184 | add gr25,gr6,gr25 | |
185 | addi gr25,#1,gr25 | |
186 | __head_no_DCS0: | |
187 | ||
188 | ldi @(gr11,#0x04),gr6 ; DAMK1: bits 11:0 match addr 11:0 | |
189 | subcc gr6,gr17,gr0,icc0 | |
190 | beq icc0,#0,__head_no_DCS1 | |
191 | ldi @(gr12,#0x04),gr4 ; DARS1 | |
192 | add gr25,gr6,gr25 | |
193 | addi gr25,#1,gr25 | |
194 | __head_no_DCS1: | |
195 | ||
196 | ldi @(gr11,#0x8),gr6 ; DAMK2: bits 11:0 match addr 11:0 | |
197 | subcc gr6,gr17,gr0,icc0 | |
198 | beq icc0,#0,__head_no_DCS2 | |
199 | ldi @(gr12,#0x8),gr4 ; DARS2 | |
200 | add gr25,gr6,gr25 | |
201 | addi gr25,#1,gr25 | |
202 | __head_no_DCS2: | |
203 | ||
204 | ldi @(gr11,#0xc),gr6 ; DAMK3: bits 11:0 match addr 11:0 | |
205 | subcc gr6,gr17,gr0,icc0 | |
206 | beq icc0,#0,__head_no_DCS3 | |
207 | ldi @(gr12,#0xc),gr4 ; DARS3 | |
208 | add gr25,gr6,gr25 | |
209 | addi gr25,#1,gr25 | |
210 | __head_no_DCS3: | |
211 | ||
212 | slli gr25,#20,gr25 ; shift [11:0] -> [31:20] | |
213 | bralr | |
214 | ||
215 | ############################################################################### | |
216 | # | |
217 | # set the protection map with the I/DAMPR registers | |
218 | # | |
219 | # ENTRY: EXIT: | |
220 | # GR25 SDRAM size saved | |
221 | # GR30 LED address saved | |
222 | # | |
223 | ############################################################################### | |
224 | .globl __head_fr555_set_protection | |
225 | __head_fr555_set_protection: | |
226 | movsg lr,gr27 | |
227 | ||
228 | sethi.p %hi(0xfff00000),gr11 | |
229 | setlo %lo(0xfff00000),gr11 | |
230 | ||
231 | # set the I/O region protection registers for FR555 | |
232 | sethi.p %hi(__region_IO),gr7 | |
233 | setlo %lo(__region_IO),gr7 | |
234 | ori gr7,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5 | |
235 | movgs gr0,iampr15 | |
236 | movgs gr0,iamlr15 | |
237 | movgs gr5,dampr15 | |
238 | movgs gr7,damlr15 | |
239 | ||
240 | # need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible | |
241 | # - start with the highest numbered registers | |
242 | sethi.p %hi(__kernel_image_end),gr8 | |
243 | setlo %lo(__kernel_image_end),gr8 | |
244 | sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap | |
245 | setlo %lo(32768),gr4 | |
246 | add gr8,gr4,gr8 | |
247 | sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB | |
248 | setlo %lo(1024*2048-1),gr4 | |
249 | add.p gr8,gr4,gr8 | |
250 | not gr4,gr4 | |
251 | and gr8,gr4,gr8 | |
252 | ||
253 | sethi.p %hi(__page_offset),gr9 | |
254 | setlo %lo(__page_offset),gr9 | |
255 | add gr9,gr25,gr9 | |
256 | ||
257 | # GR8 = base of uncovered RAM | |
258 | # GR9 = top of uncovered RAM | |
259 | # GR11 - mask for DAMLR/IAMLR regs | |
260 | # | |
261 | call __head_split_region | |
262 | movgs gr4,iampr14 | |
263 | movgs gr6,iamlr14 | |
264 | movgs gr5,dampr14 | |
265 | movgs gr7,damlr14 | |
266 | call __head_split_region | |
267 | movgs gr4,iampr13 | |
268 | movgs gr6,iamlr13 | |
269 | movgs gr5,dampr13 | |
270 | movgs gr7,damlr13 | |
271 | call __head_split_region | |
272 | movgs gr4,iampr12 | |
273 | movgs gr6,iamlr12 | |
274 | movgs gr5,dampr12 | |
275 | movgs gr7,damlr12 | |
276 | call __head_split_region | |
277 | movgs gr4,iampr11 | |
278 | movgs gr6,iamlr11 | |
279 | movgs gr5,dampr11 | |
280 | movgs gr7,damlr11 | |
281 | call __head_split_region | |
282 | movgs gr4,iampr10 | |
283 | movgs gr6,iamlr10 | |
284 | movgs gr5,dampr10 | |
285 | movgs gr7,damlr10 | |
286 | call __head_split_region | |
287 | movgs gr4,iampr9 | |
288 | movgs gr6,iamlr9 | |
289 | movgs gr5,dampr9 | |
290 | movgs gr7,damlr9 | |
291 | call __head_split_region | |
292 | movgs gr4,iampr8 | |
293 | movgs gr6,iamlr8 | |
294 | movgs gr5,dampr8 | |
295 | movgs gr7,damlr8 | |
296 | ||
297 | call __head_split_region | |
298 | movgs gr4,iampr7 | |
299 | movgs gr6,iamlr7 | |
300 | movgs gr5,dampr7 | |
301 | movgs gr7,damlr7 | |
302 | call __head_split_region | |
303 | movgs gr4,iampr6 | |
304 | movgs gr6,iamlr6 | |
305 | movgs gr5,dampr6 | |
306 | movgs gr7,damlr6 | |
307 | call __head_split_region | |
308 | movgs gr4,iampr5 | |
309 | movgs gr6,iamlr5 | |
310 | movgs gr5,dampr5 | |
311 | movgs gr7,damlr5 | |
312 | call __head_split_region | |
313 | movgs gr4,iampr4 | |
314 | movgs gr6,iamlr4 | |
315 | movgs gr5,dampr4 | |
316 | movgs gr7,damlr4 | |
317 | call __head_split_region | |
318 | movgs gr4,iampr3 | |
319 | movgs gr6,iamlr3 | |
320 | movgs gr5,dampr3 | |
321 | movgs gr7,damlr3 | |
322 | call __head_split_region | |
323 | movgs gr4,iampr2 | |
324 | movgs gr6,iamlr2 | |
325 | movgs gr5,dampr2 | |
326 | movgs gr7,damlr2 | |
327 | call __head_split_region | |
328 | movgs gr4,iampr1 | |
329 | movgs gr6,iamlr1 | |
330 | movgs gr5,dampr1 | |
331 | movgs gr7,damlr1 | |
332 | ||
333 | # cover kernel core image with kernel-only segment | |
334 | sethi.p %hi(__page_offset),gr8 | |
335 | setlo %lo(__page_offset),gr8 | |
336 | call __head_split_region | |
337 | ||
338 | #ifdef CONFIG_PROTECT_KERNEL | |
339 | ori.p gr4,#xAMPRx_S_KERNEL,gr4 | |
340 | ori gr5,#xAMPRx_S_KERNEL,gr5 | |
341 | #endif | |
342 | ||
343 | movgs gr4,iampr0 | |
344 | movgs gr6,iamlr0 | |
345 | movgs gr5,dampr0 | |
346 | movgs gr7,damlr0 | |
347 | jmpl @(gr27,gr0) |