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calibrate_delay() must be __cpuinit
[deliverable/linux.git] / arch / frv / kernel / setup.c
CommitLineData
1da177e4
LT		 1/* setup.c: FRV specific setup
2 *
3 * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 * - Derived from arch/m68k/kernel/setup.c
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
63104eec 13#include <linux/utsrelease.h>
1da177e4
LT		 14#include <linux/kernel.h>
15#include <linux/sched.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/fs.h>
19#include <linux/mm.h>
20#include <linux/fb.h>
21#include <linux/console.h>
22#include <linux/genhd.h>
23#include <linux/errno.h>
24#include <linux/string.h>
25#include <linux/major.h>
26#include <linux/bootmem.h>
27#include <linux/highmem.h>
28#include <linux/seq_file.h>
29#include <linux/serial.h>
30#include <linux/serial_core.h>
31#include <linux/serial_reg.h>
b187f180 32#include <linux/serial_8250.h>
1da177e4
LT		 33
34#include <asm/setup.h>
1da177e4
LT		 35#include <asm/irq.h>
36#include <asm/sections.h>
37#include <asm/pgalloc.h>
38#include <asm/busctl-regs.h>
39#include <asm/serial-regs.h>
40#include <asm/timer-regs.h>
41#include <asm/irc-regs.h>
42#include <asm/spr-regs.h>
43#include <asm/mb-regs.h>
44#include <asm/mb93493-regs.h>
45#include <asm/gdb-stub.h>
1da177e4
LT		 46#include <asm/io.h>
47
48#ifdef CONFIG_BLK_DEV_INITRD
49#include <linux/blk.h>
50#include <asm/pgtable.h>
51#endif
52
53#include "local.h"
54
55#ifdef CONFIG_MB93090_MB00
56static void __init mb93090_display(void);
57#endif
58#ifdef CONFIG_MMU
59static void __init setup_linux_memory(void);
60#else
61static void __init setup_uclinux_memory(void);
62#endif
63
1da177e4
LT		 64#ifdef CONFIG_MB93090_MB00
65static char __initdata mb93090_banner[] = "FJ/RH FR-V Linux";
66static char __initdata mb93090_version[] = UTS_RELEASE;
67
68int __nongprelbss mb93090_mb00_detected;
69#endif
70
71const char __frv_unknown_system[] = "unknown";
72const char __frv_mb93091_cb10[] = "mb93091-cb10";
73const char __frv_mb93091_cb11[] = "mb93091-cb11";
74const char __frv_mb93091_cb30[] = "mb93091-cb30";
75const char __frv_mb93091_cb41[] = "mb93091-cb41";
76const char __frv_mb93091_cb60[] = "mb93091-cb60";
77const char __frv_mb93091_cb70[] = "mb93091-cb70";
78const char __frv_mb93091_cb451[] = "mb93091-cb451";
79const char __frv_mb93090_mb00[] = "mb93090-mb00";
80
81const char __frv_mb93493[] = "mb93493";
82
83const char __frv_mb93093[] = "mb93093";
84
85static const char *__nongprelbss cpu_series;
86static const char *__nongprelbss cpu_core;
87static const char *__nongprelbss cpu_silicon;
88static const char *__nongprelbss cpu_mmu;
89static const char *__nongprelbss cpu_system;
90static const char *__nongprelbss cpu_board1;
91static const char *__nongprelbss cpu_board2;
92
93static unsigned long __nongprelbss cpu_psr_all;
94static unsigned long __nongprelbss cpu_hsr0_all;
95
96unsigned long __nongprelbss pdm_suspend_mode;
97
98unsigned long __nongprelbss rom_length;
99unsigned long __nongprelbss memory_start;
100unsigned long __nongprelbss memory_end;
101
102unsigned long __nongprelbss dma_coherent_mem_start;
103unsigned long __nongprelbss dma_coherent_mem_end;
104
105unsigned long __initdata __sdram_old_base;
106unsigned long __initdata num_mappedpages;
107
108struct cpuinfo_frv __nongprelbss boot_cpu_data;
109
9c00f761 110char __initdata command_line[COMMAND_LINE_SIZE];
1da177e4
LT		 111char __initdata redboot_command_line[COMMAND_LINE_SIZE];
112
113#ifdef CONFIG_PM
114#define __pminit
115#define __pminitdata
116#else
117#define __pminit __init
118#define __pminitdata __initdata
119#endif
120
121struct clock_cmode {
122 uint8_t xbus, sdram, corebus, core, dsu;
123};
124
125#define _frac(N,D) ((N)<<4 | (D))
126#define _x0_16 _frac(1,6)
127#define _x0_25 _frac(1,4)
128#define _x0_33 _frac(1,3)
129#define _x0_375 _frac(3,8)
130#define _x0_5 _frac(1,2)
131#define _x0_66 _frac(2,3)
132#define _x0_75 _frac(3,4)
133#define _x1 _frac(1,1)
134#define _x1_5 _frac(3,2)
135#define _x2 _frac(2,1)
136#define _x3 _frac(3,1)
137#define _x4 _frac(4,1)
138#define _x4_5 _frac(9,2)
139#define _x6 _frac(6,1)
140#define _x8 _frac(8,1)
141#define _x9 _frac(9,1)
142
143int __nongprelbss clock_p0_current;
144int __nongprelbss clock_cm_current;
145int __nongprelbss clock_cmode_current;
146#ifdef CONFIG_PM
147int __nongprelbss clock_cmodes_permitted;
148unsigned long __nongprelbss clock_bits_settable;
149#endif
150
151static struct clock_cmode __pminitdata undef_clock_cmode = { _x1, _x1, _x1, _x1, _x1 };
152
153static struct clock_cmode __pminitdata clock_cmodes_fr401_fr403[16] = {
154 [4] = { _x1, _x1, _x2, _x2, _x0_25 },
155 [5] = { _x1, _x2, _x4, _x4, _x0_5 },
156 [8] = { _x1, _x1, _x1, _x2, _x0_25 },
157 [9] = { _x1, _x2, _x2, _x4, _x0_5 },
158 [11] = { _x1, _x4, _x4, _x8, _x1 },
159 [12] = { _x1, _x1, _x2, _x4, _x0_5 },
160 [13] = { _x1, _x2, _x4, _x8, _x1 },
161};
162
163static struct clock_cmode __pminitdata clock_cmodes_fr405[16] = {
164 [0] = { _x1, _x1, _x1, _x1, _x0_5 },
165 [1] = { _x1, _x1, _x1, _x3, _x0_25 },
166 [2] = { _x1, _x1, _x2, _x6, _x0_5 },
167 [3] = { _x1, _x2, _x2, _x6, _x0_5 },
168 [4] = { _x1, _x1, _x2, _x2, _x0_16 },
169 [8] = { _x1, _x1, _x1, _x2, _x0_16 },
170 [9] = { _x1, _x2, _x2, _x4, _x0_33 },
171 [12] = { _x1, _x1, _x2, _x4, _x0_33 },
172 [14] = { _x1, _x3, _x3, _x9, _x0_75 },
173 [15] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
174
175#define CLOCK_CMODES_PERMITTED_FR405 0xd31f
176};
177
178static struct clock_cmode __pminitdata clock_cmodes_fr555[16] = {
179 [0] = { _x1, _x2, _x2, _x4, _x0_33 },
180 [1] = { _x1, _x3, _x3, _x6, _x0_5 },
181 [2] = { _x1, _x2, _x4, _x8, _x0_66 },
182 [3] = { _x1, _x1_5, _x3, _x6, _x0_5 },
183 [4] = { _x1, _x3, _x3, _x9, _x0_75 },
184 [5] = { _x1, _x2, _x2, _x6, _x0_5 },
185 [6] = { _x1, _x1_5, _x1_5, _x4_5, _x0_375 },
186};
187
188static const struct clock_cmode __pminitdata *clock_cmodes;
189static int __pminitdata clock_doubled;
190
5616df20 191static struct uart_port __pminitdata __frv_uart0 = {
1da177e4
LT		 192 .uartclk = 0,
193 .membase = (char *) UART0_BASE,
194 .irq = IRQ_CPU_UART0,
195 .regshift = 3,
196 .iotype = UPIO_MEM,
197 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
198};
199
5616df20 200static struct uart_port __pminitdata __frv_uart1 = {
1da177e4
LT		 201 .uartclk = 0,
202 .membase = (char *) UART1_BASE,
203 .irq = IRQ_CPU_UART1,
204 .regshift = 3,
205 .iotype = UPIO_MEM,
206 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
207};
208
209#if 0
210static void __init printk_xampr(unsigned long ampr, unsigned long amlr, char i_d, int n)
211{
212 unsigned long phys, virt, cxn, size;
213
214#ifdef CONFIG_MMU
215 virt = amlr & 0xffffc000;
216 cxn = amlr & 0x3fff;
217#else
218 virt = ampr & 0xffffc000;
219 cxn = 0;
220#endif
221 phys = ampr & xAMPRx_PPFN;
222 size = 1 << (((ampr & xAMPRx_SS) >> 4) + 17);
223
224 printk("%cAMPR%d: va %08lx-%08lx [pa %08lx] %c%c%c%c [cxn:%04lx]\n",
225 i_d, n,
226 virt, virt + size - 1,
227 phys,
228 ampr & xAMPRx_S ? 'S' : '-',
229 ampr & xAMPRx_C ? 'C' : '-',
230 ampr & DAMPRx_WP ? 'W' : '-',
231 ampr & xAMPRx_V ? 'V' : '-',
232 cxn
233 );
234}
235#endif
236
237/*****************************************************************************/
238/*
239 * dump the memory map
240 */
241static void __init dump_memory_map(void)
242{
243
244#if 0
245 /* dump the protection map */
246 printk_xampr(__get_IAMPR(0), __get_IAMLR(0), 'I', 0);
247 printk_xampr(__get_IAMPR(1), __get_IAMLR(1), 'I', 1);
248 printk_xampr(__get_IAMPR(2), __get_IAMLR(2), 'I', 2);
249 printk_xampr(__get_IAMPR(3), __get_IAMLR(3), 'I', 3);
250 printk_xampr(__get_IAMPR(4), __get_IAMLR(4), 'I', 4);
251 printk_xampr(__get_IAMPR(5), __get_IAMLR(5), 'I', 5);
252 printk_xampr(__get_IAMPR(6), __get_IAMLR(6), 'I', 6);
253 printk_xampr(__get_IAMPR(7), __get_IAMLR(7), 'I', 7);
254 printk_xampr(__get_IAMPR(8), __get_IAMLR(8), 'I', 8);
255 printk_xampr(__get_IAMPR(9), __get_IAMLR(9), 'i', 9);
256 printk_xampr(__get_IAMPR(10), __get_IAMLR(10), 'I', 10);
257 printk_xampr(__get_IAMPR(11), __get_IAMLR(11), 'I', 11);
258 printk_xampr(__get_IAMPR(12), __get_IAMLR(12), 'I', 12);
259 printk_xampr(__get_IAMPR(13), __get_IAMLR(13), 'I', 13);
260 printk_xampr(__get_IAMPR(14), __get_IAMLR(14), 'I', 14);
261 printk_xampr(__get_IAMPR(15), __get_IAMLR(15), 'I', 15);
262
263 printk_xampr(__get_DAMPR(0), __get_DAMLR(0), 'D', 0);
264 printk_xampr(__get_DAMPR(1), __get_DAMLR(1), 'D', 1);
265 printk_xampr(__get_DAMPR(2), __get_DAMLR(2), 'D', 2);
266 printk_xampr(__get_DAMPR(3), __get_DAMLR(3), 'D', 3);
267 printk_xampr(__get_DAMPR(4), __get_DAMLR(4), 'D', 4);
268 printk_xampr(__get_DAMPR(5), __get_DAMLR(5), 'D', 5);
269 printk_xampr(__get_DAMPR(6), __get_DAMLR(6), 'D', 6);
270 printk_xampr(__get_DAMPR(7), __get_DAMLR(7), 'D', 7);
271 printk_xampr(__get_DAMPR(8), __get_DAMLR(8), 'D', 8);
272 printk_xampr(__get_DAMPR(9), __get_DAMLR(9), 'D', 9);
273 printk_xampr(__get_DAMPR(10), __get_DAMLR(10), 'D', 10);
274 printk_xampr(__get_DAMPR(11), __get_DAMLR(11), 'D', 11);
275 printk_xampr(__get_DAMPR(12), __get_DAMLR(12), 'D', 12);
276 printk_xampr(__get_DAMPR(13), __get_DAMLR(13), 'D', 13);
277 printk_xampr(__get_DAMPR(14), __get_DAMLR(14), 'D', 14);
278 printk_xampr(__get_DAMPR(15), __get_DAMLR(15), 'D', 15);
279#endif
280
281#if 0
282 /* dump the bus controller registers */
283 printk("LGCR: %08lx\n", __get_LGCR());
284 printk("Master: %08lx-%08lx CR=%08lx\n",
285 __get_LEMBR(), __get_LEMBR() + __get_LEMAM(),
286 __get_LMAICR());
287
288 int loop;
289 for (loop = 1; loop <= 7; loop++) {
290 unsigned long lcr = __get_LCR(loop), lsbr = __get_LSBR(loop);
291 printk("CS#%d: %08lx-%08lx %c%c%c%c%c%c%c%c%c\n",
292 loop,
293 lsbr, lsbr + __get_LSAM(loop),
294 lcr & 0x80000000 ? 'r' : '-',
295 lcr & 0x40000000 ? 'w' : '-',
296 lcr & 0x08000000 ? 'b' : '-',
297 lcr & 0x04000000 ? 'B' : '-',
298 lcr & 0x02000000 ? 'C' : '-',
299 lcr & 0x01000000 ? 'D' : '-',
300 lcr & 0x00800000 ? 'W' : '-',
301 lcr & 0x00400000 ? 'R' : '-',
302 (lcr & 0x00030000) == 0x00000000 ? '4' :
303 (lcr & 0x00030000) == 0x00010000 ? '2' :
304 (lcr & 0x00030000) == 0x00020000 ? '1' :
305 '-'
306 );
307 }
308#endif
309
310#if 0
311 printk("\n");
312#endif
313} /* end dump_memory_map() */
314
315/*****************************************************************************/
316/*
317 * attempt to detect a VDK motherboard and DAV daughter board on an MB93091 system
318 */
319#ifdef CONFIG_MB93091_VDK
320static void __init detect_mb93091(void)
321{
322#ifdef CONFIG_MB93090_MB00
323 /* Detect CB70 without motherboard */
324 if (!(cpu_system == __frv_mb93091_cb70 && ((*(unsigned short *)0xffc00030) & 0x100))) {
325 cpu_board1 = __frv_mb93090_mb00;
326 mb93090_mb00_detected = 1;
327 }
328#endif
329
330#ifdef CONFIG_FUJITSU_MB93493
331 cpu_board2 = __frv_mb93493;
332#endif
333
334} /* end detect_mb93091() */
335#endif
336
337/*****************************************************************************/
338/*
339 * determine the CPU type and set appropriate parameters
340 *
341 * Family Series CPU Core Silicon Imple Vers
342 * ----------------------------------------------------------
343 * FR-V --+-> FR400 --+-> FR401 --+-> MB93401 02 00 [1]
344 * | | |
345 * | | +-> MB93401/A 02 01
346 * | | |
347 * | | +-> MB93403 02 02
348 * | |
349 * | +-> FR405 ----> MB93405 04 00
350 * |
351 * +-> FR450 ----> FR451 ----> MB93451 05 00
352 * |
353 * +-> FR500 ----> FR501 --+-> MB93501 01 01 [2]
354 * | |
355 * | +-> MB93501/A 01 02
356 * |
357 * +-> FR550 --+-> FR551 ----> MB93555 03 01
358 *
359 * [1] The MB93401 is an obsolete CPU replaced by the MB93401A
360 * [2] The MB93501 is an obsolete CPU replaced by the MB93501A
361 *
362 * Imple is PSR(Processor Status Register)[31:28].
363 * Vers is PSR(Processor Status Register)[27:24].
364 *
365 * A "Silicon" consists of CPU core and some on-chip peripherals.
366 */
367static void __init determine_cpu(void)
368{
369 unsigned long hsr0 = __get_HSR(0);
370 unsigned long psr = __get_PSR();
371
372 /* work out what selectable services the CPU supports */
373 __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM);
374 cpu_psr_all = __get_PSR();
375 __set_PSR(psr);
376
377 __set_HSR(0, hsr0 | HSR0_GRLE | HSR0_GRHE | HSR0_FRLE | HSR0_FRHE);
378 cpu_hsr0_all = __get_HSR(0);
379 __set_HSR(0, hsr0);
380
381 /* derive other service specs from the CPU type */
382 cpu_series = "unknown";
383 cpu_core = "unknown";
384 cpu_silicon = "unknown";
385 cpu_mmu = "Prot";
386 cpu_system = __frv_unknown_system;
387 clock_cmodes = NULL;
388 clock_doubled = 0;
389#ifdef CONFIG_PM
390 clock_bits_settable = CLOCK_BIT_CM_H | CLOCK_BIT_CM_M | CLOCK_BIT_P0;
391#endif
392
393 switch (PSR_IMPLE(psr)) {
394 case PSR_IMPLE_FR401:
395 cpu_series = "fr400";
396 cpu_core = "fr401";
397 pdm_suspend_mode = HSR0_PDM_PLL_RUN;
398
399 switch (PSR_VERSION(psr)) {
400 case PSR_VERSION_FR401_MB93401:
401 cpu_silicon = "mb93401";
402 cpu_system = __frv_mb93091_cb10;
403 clock_cmodes = clock_cmodes_fr401_fr403;
404 clock_doubled = 1;
405 break;
406 case PSR_VERSION_FR401_MB93401A:
407 cpu_silicon = "mb93401/A";
408 cpu_system = __frv_mb93091_cb11;
409 clock_cmodes = clock_cmodes_fr401_fr403;
410 break;
411 case PSR_VERSION_FR401_MB93403:
412 cpu_silicon = "mb93403";
413#ifndef CONFIG_MB93093_PDK
414 cpu_system = __frv_mb93091_cb30;
415#else
416 cpu_system = __frv_mb93093;
417#endif
418 clock_cmodes = clock_cmodes_fr401_fr403;
419 break;
420 default:
421 break;
422 }
423 break;
424
425 case PSR_IMPLE_FR405:
426 cpu_series = "fr400";
427 cpu_core = "fr405";
428 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
429
430 switch (PSR_VERSION(psr)) {
431 case PSR_VERSION_FR405_MB93405:
432 cpu_silicon = "mb93405";
433 cpu_system = __frv_mb93091_cb60;
434 clock_cmodes = clock_cmodes_fr405;
435#ifdef CONFIG_PM
436 clock_bits_settable |= CLOCK_BIT_CMODE;
437 clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
438#endif
439
440 /* the FPGA on the CB70 has extra registers
441 * - it has 0x0046 in the VDK_ID FPGA register at 0x1a0, which is
442 * how we tell the difference between it and a CB60
443 */
444 if (*(volatile unsigned short *) 0xffc001a0 == 0x0046)
445 cpu_system = __frv_mb93091_cb70;
446 break;
447 default:
448 break;
449 }
450 break;
451
452 case PSR_IMPLE_FR451:
453 cpu_series = "fr450";
454 cpu_core = "fr451";
455 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
456#ifdef CONFIG_PM
457 clock_bits_settable |= CLOCK_BIT_CMODE;
458 clock_cmodes_permitted = CLOCK_CMODES_PERMITTED_FR405;
459#endif
460 switch (PSR_VERSION(psr)) {
461 case PSR_VERSION_FR451_MB93451:
462 cpu_silicon = "mb93451";
463 cpu_mmu = "Prot, SAT, xSAT, DAT";
464 cpu_system = __frv_mb93091_cb451;
465 clock_cmodes = clock_cmodes_fr405;
466 break;
467 default:
468 break;
469 }
470 break;
471
472 case PSR_IMPLE_FR501:
473 cpu_series = "fr500";
474 cpu_core = "fr501";
475 pdm_suspend_mode = HSR0_PDM_PLL_STOP;
476
477 switch (PSR_VERSION(psr)) {
478 case PSR_VERSION_FR501_MB93501: cpu_silicon = "mb93501"; break;
479 case PSR_VERSION_FR501_MB93501A: cpu_silicon = "mb93501/A"; break;
480 default:
481 break;
482 }
483 break;
484
485 case PSR_IMPLE_FR551:
486 cpu_series = "fr550";
487 cpu_core = "fr551";
488 pdm_suspend_mode = HSR0_PDM_PLL_RUN;
489
490 switch (PSR_VERSION(psr)) {
491 case PSR_VERSION_FR551_MB93555:
492 cpu_silicon = "mb93555";
493 cpu_mmu = "Prot, SAT";
494 cpu_system = __frv_mb93091_cb41;
495 clock_cmodes = clock_cmodes_fr555;
496 clock_doubled = 1;
497 break;
498 default:
499 break;
500 }
501 break;
502
503 default:
504 break;
505 }
506
507 printk("- Series:%s CPU:%s Silicon:%s\n",
508 cpu_series, cpu_core, cpu_silicon);
509
510#ifdef CONFIG_MB93091_VDK
511 detect_mb93091();
512#endif
513
514#if defined(CONFIG_MB93093_PDK) && defined(CONFIG_FUJITSU_MB93493)
515 cpu_board2 = __frv_mb93493;
516#endif
517
518} /* end determine_cpu() */
519
520/*****************************************************************************/
521/*
522 * calculate the bus clock speed
523 */
524void __pminit determine_clocks(int verbose)
525{
526 const struct clock_cmode *mode, *tmode;
527 unsigned long clkc, psr, quot;
528
529 clkc = __get_CLKC();
530 psr = __get_PSR();
531
532 clock_p0_current = !!(clkc & CLKC_P0);
533 clock_cm_current = clkc & CLKC_CM;
534 clock_cmode_current = (clkc & CLKC_CMODE) >> CLKC_CMODE_s;
535
536 if (verbose)
537 printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc);
538
539 /* the CB70 has some alternative ways of setting the clock speed through switches accessed
540 * through the FPGA. */
541 if (cpu_system == __frv_mb93091_cb70) {
542 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
543
544 if (clkswr & 0x1000)
545 __clkin_clock_speed_HZ = 60000000UL;
546 else
547 __clkin_clock_speed_HZ =
548 ((clkswr >> 8) & 0xf) * 10000000 +
549 ((clkswr >> 4) & 0xf) * 1000000 +
550 ((clkswr ) & 0xf) * 100000;
551 }
552 /* the FR451 is currently fixed at 24MHz */
553 else if (cpu_system == __frv_mb93091_cb451) {
554 //__clkin_clock_speed_HZ = 24000000UL; // CB451-FPGA
555 unsigned short clkswr = *(volatile unsigned short *) 0xffc00104UL & 0x1fffUL;
556
557 if (clkswr & 0x1000)
558 __clkin_clock_speed_HZ = 60000000UL;
559 else
560 __clkin_clock_speed_HZ =
561 ((clkswr >> 8) & 0xf) * 10000000 +
562 ((clkswr >> 4) & 0xf) * 1000000 +
563 ((clkswr ) & 0xf) * 100000;
564 }
565 /* otherwise determine the clockspeed from VDK or other registers */
566 else {
567 __clkin_clock_speed_HZ = __get_CLKIN();
568 }
569
570 /* look up the appropriate clock relationships table entry */
571 mode = &undef_clock_cmode;
572 if (clock_cmodes) {
573 tmode = &clock_cmodes[(clkc & CLKC_CMODE) >> CLKC_CMODE_s];
574 if (tmode->xbus)
575 mode = tmode;
576 }
577
578#define CLOCK(SRC,RATIO) ((SRC) * (((RATIO) >> 4) & 0x0f) / ((RATIO) & 0x0f))
579
580 if (clock_doubled)
581 __clkin_clock_speed_HZ <<= 1;
582
583 __ext_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->xbus);
584 __sdram_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
585 __dsu_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->dsu);
586
587 switch (clkc & CLKC_CM) {
588 case 0: /* High */
589 __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->corebus);
590 __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->core);
591 break;
592 case 1: /* Medium */
593 __core_bus_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
594 __core_clock_speed_HZ = CLOCK(__clkin_clock_speed_HZ, mode->sdram);
595 break;
596 case 2: /* Low; not supported */
597 case 3: /* UNDEF */
598 printk("Unsupported CLKC CM %ld\n", clkc & CLKC_CM);
599 panic("Bye");
600 }
601
602 __res_bus_clock_speed_HZ = __ext_bus_clock_speed_HZ;
603 if (clkc & CLKC_P0)
604 __res_bus_clock_speed_HZ >>= 1;
605
606 if (verbose) {
607 printk("CLKIN: %lu.%3.3luMHz\n",
608 __clkin_clock_speed_HZ / 1000000,
609 (__clkin_clock_speed_HZ / 1000) % 1000);
610
611 printk("CLKS:"
612 " ext=%luMHz res=%luMHz sdram=%luMHz cbus=%luMHz core=%luMHz dsu=%luMHz\n",
613 __ext_bus_clock_speed_HZ / 1000000,
614 __res_bus_clock_speed_HZ / 1000000,
615 __sdram_clock_speed_HZ / 1000000,
616 __core_bus_clock_speed_HZ / 1000000,
617 __core_clock_speed_HZ / 1000000,
618 __dsu_clock_speed_HZ / 1000000
619 );
620 }
621
622 /* calculate the number of __delay() loop iterations per sec (2 insn loop) */
623 __delay_loops_MHz = __core_clock_speed_HZ / (1000000 * 2);
624
625 /* set the serial prescaler */
626 __serial_clock_speed_HZ = __res_bus_clock_speed_HZ;
627 quot = 1;
628 while (__serial_clock_speed_HZ / quot / 16 / 65536 > 3000)
629 quot += 1;
630
631 /* double the divisor if P0 is clear, so that if/when P0 is set, it's still achievable
632 * - we have to be careful - dividing too much can mean we can't get 115200 baud
633 */
634 if (__serial_clock_speed_HZ > 32000000 && !(clkc & CLKC_P0))
635 quot <<= 1;
636
637 __serial_clock_speed_HZ /= quot;
638 __frv_uart0.uartclk = __serial_clock_speed_HZ;
639 __frv_uart1.uartclk = __serial_clock_speed_HZ;
640
641 if (verbose)
642 printk(" uart=%luMHz\n", __serial_clock_speed_HZ / 1000000 * quot);
643
644 while (!(__get_UART0_LSR() & UART_LSR_TEMT))
645 continue;
646
647 while (!(__get_UART1_LSR() & UART_LSR_TEMT))
648 continue;
649
650 __set_UCPVR(quot);
651 __set_UCPSR(0);
652} /* end determine_clocks() */
653
654/*****************************************************************************/
655/*
656 * reserve some DMA consistent memory
657 */
658#ifdef CONFIG_RESERVE_DMA_COHERENT
659static void __init reserve_dma_coherent(void)
660{
661 unsigned long ampr;
662
663 /* find the first non-kernel memory tile and steal it */
664#define __steal_AMPR(r) \
665 if (__get_DAMPR(r) & xAMPRx_V) { \
666 ampr = __get_DAMPR(r); \
667 __set_DAMPR(r, ampr | xAMPRx_S | xAMPRx_C); \
668 __set_IAMPR(r, 0); \
669 goto found; \
670 }
671
672 __steal_AMPR(1);
673 __steal_AMPR(2);
674 __steal_AMPR(3);
675 __steal_AMPR(4);
676 __steal_AMPR(5);
677 __steal_AMPR(6);
678
679 if (PSR_IMPLE(__get_PSR()) == PSR_IMPLE_FR551) {
680 __steal_AMPR(7);
681 __steal_AMPR(8);
682 __steal_AMPR(9);
683 __steal_AMPR(10);
684 __steal_AMPR(11);
685 __steal_AMPR(12);
686 __steal_AMPR(13);
687 __steal_AMPR(14);
688 }
689
690 /* unable to grant any DMA consistent memory */
691 printk("No DMA consistent memory reserved\n");
692 return;
693
694 found:
695 dma_coherent_mem_start = ampr & xAMPRx_PPFN;
696 ampr &= xAMPRx_SS;
697 ampr >>= 4;
698 ampr = 1 << (ampr - 3 + 20);
699 dma_coherent_mem_end = dma_coherent_mem_start + ampr;
700
701 printk("DMA consistent memory reserved %lx-%lx\n",
702 dma_coherent_mem_start, dma_coherent_mem_end);
703
704} /* end reserve_dma_coherent() */
705#endif
706
707/*****************************************************************************/
708/*
709 * calibrate the delay loop
710 */
6c81c32f 711void __cpuinit calibrate_delay(void)
1da177e4
LT		 712{
713 loops_per_jiffy = __delay_loops_MHz * (1000000 / HZ);
714
715 printk("Calibrating delay loop... %lu.%02lu BogoMIPS\n",
716 loops_per_jiffy / (500000 / HZ),
717 (loops_per_jiffy / (5000 / HZ)) % 100);
718
719} /* end calibrate_delay() */
720
721/*****************************************************************************/
722/*
723 * look through the command line for some things we need to know immediately
724 */
725static void __init parse_cmdline_early(char *cmdline)
726{
727 if (!cmdline)
728 return;
729
730 while (*cmdline) {
731 if (*cmdline == ' ')
732 cmdline++;
733
734 /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
735 * out from the SDRAM controller mask register
736 */
737 if (!memcmp(cmdline, "mem=", 4)) {
738 unsigned long long mem_size;
739
740 mem_size = memparse(cmdline + 4, &cmdline);
741 memory_end = memory_start + mem_size;
742 }
743
744 while (*cmdline && *cmdline != ' ')
745 cmdline++;
746 }
747
748} /* end parse_cmdline_early() */
749
750/*****************************************************************************/
751/*
752 *
753 */
754void __init setup_arch(char **cmdline_p)
755{
756#ifdef CONFIG_MMU
757 printk("Linux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
758#else
759 printk("uClinux FR-V port done by Red Hat Inc <dhowells@redhat.com>\n");
760#endif
761
9c00f761 762 memcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);
1da177e4
LT		 763
764 determine_cpu();
765 determine_clocks(1);
766
767 /* For printk-directly-beats-on-serial-hardware hack */
768 console_set_baud(115200);
769#ifdef CONFIG_GDBSTUB
770 gdbstub_set_baud(115200);
771#endif
772
773#ifdef CONFIG_RESERVE_DMA_COHERENT
774 reserve_dma_coherent();
775#endif
776 dump_memory_map();
777
778#ifdef CONFIG_MB93090_MB00
779 if (mb93090_mb00_detected)
780 mb93090_display();
781#endif
782
783 /* register those serial ports that are available */
f8aec757 784#ifdef CONFIG_FRV_ONCPU_SERIAL
1da177e4
LT		 785#ifndef CONFIG_GDBSTUB_UART0
786 __reg(UART0_BASE + UART_IER * 8) = 0;
787 early_serial_setup(&__frv_uart0);
1da177e4
LT		 788#endif
789#ifndef CONFIG_GDBSTUB_UART1
790 __reg(UART1_BASE + UART_IER * 8) = 0;
791 early_serial_setup(&__frv_uart1);
1da177e4 792#endif
f8aec757 793#endif
1da177e4 794
1da177e4 795 /* deal with the command line - RedBoot may have passed one to the kernel */
9c00f761 796 memcpy(command_line, boot_command_line, sizeof(command_line));
1da177e4
LT		 797 *cmdline_p = &command_line[0];
798 parse_cmdline_early(command_line);
799
800 /* set up the memory description
801 * - by now the stack is part of the init task */
802 printk("Memory %08lx-%08lx\n", memory_start, memory_end);
803
125e1874 804 BUG_ON(memory_start == memory_end);
1da177e4
LT		 805
806 init_mm.start_code = (unsigned long) &_stext;
807 init_mm.end_code = (unsigned long) &_etext;
808 init_mm.end_data = (unsigned long) &_edata;
809#if 0 /* DAVIDM - don't set brk just incase someone decides to use it */
810 init_mm.brk = (unsigned long) &_end;
811#else
812 init_mm.brk = (unsigned long) 0;
813#endif
814
815#ifdef DEBUG
816 printk("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x BSS=0x%06x-0x%06x\n",
817 (int) &_stext, (int) &_etext,
818 (int) &_sdata, (int) &_edata,
819 (int) &_sbss, (int) &_ebss);
820#endif
821
822#ifdef CONFIG_VT
823#if defined(CONFIG_VGA_CONSOLE)
824 conswitchp = &vga_con;
825#elif defined(CONFIG_DUMMY_CONSOLE)
826 conswitchp = &dummy_con;
827#endif
828#endif
829
1da177e4
LT		 830#ifdef CONFIG_MMU
831 setup_linux_memory();
832#else
833 setup_uclinux_memory();
834#endif
835
836 /* get kmalloc into gear */
837 paging_init();
838
839 /* init DMA */
840 frv_dma_init();
841#ifdef DEBUG
842 printk("Done setup_arch\n");
843#endif
844
845 /* start the decrement timer running */
846// asm volatile("movgs %0,timerd" :: "r"(10000000));
847// __set_HSR(0, __get_HSR(0) | HSR0_ETMD);
848
849} /* end setup_arch() */
850
851#if 0
852/*****************************************************************************/
853/*
854 *
855 */
856static int __devinit setup_arch_serial(void)
857{
858 /* register those serial ports that are available */
859#ifndef CONFIG_GDBSTUB_UART0
860 early_serial_setup(&__frv_uart0);
861#endif
862#ifndef CONFIG_GDBSTUB_UART1
863 early_serial_setup(&__frv_uart1);
864#endif
865
866 return 0;
867} /* end setup_arch_serial() */
868
869late_initcall(setup_arch_serial);
870#endif
871
872/*****************************************************************************/
873/*
874 * set up the memory map for normal MMU linux
875 */
876#ifdef CONFIG_MMU
877static void __init setup_linux_memory(void)
878{
879 unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
880
881 kstart = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
882 kend = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
883
884 kstart = kstart & PAGE_MASK;
885 kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
886
887 /* give all the memory to the bootmap allocator, tell it to put the
888 * boot mem_map immediately following the kernel image
889 */
890 bootmap_size = init_bootmem_node(NODE_DATA(0),
891 kend >> PAGE_SHIFT, /* map addr */
892 memory_start >> PAGE_SHIFT, /* start of RAM */
893 memory_end >> PAGE_SHIFT /* end of RAM */
894 );
895
896 /* pass the memory that the kernel can immediately use over to the bootmem allocator */
897 max_mapnr = num_physpages = (memory_end - memory_start) >> PAGE_SHIFT;
898 low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
899 high_mem = 0;
900
901 if (num_physpages > low_top_pfn) {
902#ifdef CONFIG_HIGHMEM
903 high_mem = num_physpages - low_top_pfn;
904#else
905 max_mapnr = num_physpages = low_top_pfn;
906#endif
907 }
908 else {
909 low_top_pfn = num_physpages;
910 }
911
912 min_low_pfn = memory_start >> PAGE_SHIFT;
913 max_low_pfn = low_top_pfn;
914 max_pfn = memory_end >> PAGE_SHIFT;
915
916 num_mappedpages = low_top_pfn;
917
918 printk(KERN_NOTICE "%ldMB LOWMEM available.\n", low_top_pfn >> (20 - PAGE_SHIFT));
919
920 free_bootmem(memory_start, low_top_pfn << PAGE_SHIFT);
921
922#ifdef CONFIG_HIGHMEM
923 if (high_mem)
924 printk(KERN_NOTICE "%ldMB HIGHMEM available.\n", high_mem >> (20 - PAGE_SHIFT));
925#endif
926
927 /* take back the memory occupied by the kernel image and the bootmem alloc map */
928 reserve_bootmem(kstart, kend - kstart + bootmap_size);
929
930 /* reserve the memory occupied by the initial ramdisk */
931#ifdef CONFIG_BLK_DEV_INITRD
932 if (LOADER_TYPE && INITRD_START) {
933 if (INITRD_START + INITRD_SIZE <= (low_top_pfn << PAGE_SHIFT)) {
934 reserve_bootmem(INITRD_START, INITRD_SIZE);
19e5d9c0 935 initrd_start = INITRD_START + PAGE_OFFSET;
1da177e4
LT		 936 initrd_end = initrd_start + INITRD_SIZE;
937 }
938 else {
939 printk(KERN_ERR
940 "initrd extends beyond end of memory (0x%08lx > 0x%08lx)\n"
941 "disabling initrd\n",
942 INITRD_START + INITRD_SIZE,
943 low_top_pfn << PAGE_SHIFT);
944 initrd_start = 0;
945 }
946 }
947#endif
948
949} /* end setup_linux_memory() */
950#endif
951
952/*****************************************************************************/
953/*
954 * set up the memory map for uClinux
955 */
956#ifndef CONFIG_MMU
957static void __init setup_uclinux_memory(void)
958{
959#ifdef CONFIG_PROTECT_KERNEL
960 unsigned long dampr;
961#endif
962 unsigned long kend;
963 int bootmap_size;
964
965 kend = (unsigned long) &__kernel_image_end;
966 kend = (kend + PAGE_SIZE - 1) & PAGE_MASK;
967
968 /* give all the memory to the bootmap allocator, tell it to put the
969 * boot mem_map immediately following the kernel image
970 */
971 bootmap_size = init_bootmem_node(NODE_DATA(0),
972 kend >> PAGE_SHIFT, /* map addr */
973 memory_start >> PAGE_SHIFT, /* start of RAM */
974 memory_end >> PAGE_SHIFT /* end of RAM */
975 );
976
977 /* free all the usable memory */
978 free_bootmem(memory_start, memory_end - memory_start);
979
980 high_memory = (void *) (memory_end & PAGE_MASK);
981 max_mapnr = num_physpages = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
982
983 min_low_pfn = memory_start >> PAGE_SHIFT;
984 max_low_pfn = memory_end >> PAGE_SHIFT;
985 max_pfn = max_low_pfn;
986
987 /* now take back the bits the core kernel is occupying */
988#ifndef CONFIG_PROTECT_KERNEL
989 reserve_bootmem(kend, bootmap_size);
990 reserve_bootmem((unsigned long) &__kernel_image_start,
991 kend - (unsigned long) &__kernel_image_start);
992
993#else
994 dampr = __get_DAMPR(0);
995 dampr &= xAMPRx_SS;
996 dampr = (dampr >> 4) + 17;
997 dampr = 1 << dampr;
998
999 reserve_bootmem(__get_DAMPR(0) & xAMPRx_PPFN, dampr);
1000#endif
1001
1002 /* reserve some memory to do uncached DMA through if requested */
1003#ifdef CONFIG_RESERVE_DMA_COHERENT
1004 if (dma_coherent_mem_start)
1005 reserve_bootmem(dma_coherent_mem_start,
1006 dma_coherent_mem_end - dma_coherent_mem_start);
1007#endif
1008
1009} /* end setup_uclinux_memory() */
1010#endif
1011
1012/*****************************************************************************/
1013/*
1014 * get CPU information for use by procfs
1015 */
1016static int show_cpuinfo(struct seq_file *m, void *v)
1017{
1018 const char *gr, *fr, *fm, *fp, *cm, *nem, *ble;
1019#ifdef CONFIG_PM
1020 const char *sep;
1021#endif
1022
1023 gr = cpu_hsr0_all & HSR0_GRHE ? "gr0-63" : "gr0-31";
1024 fr = cpu_hsr0_all & HSR0_FRHE ? "fr0-63" : "fr0-31";
1025 fm = cpu_psr_all & PSR_EM ? ", Media" : "";
1026 fp = cpu_psr_all & PSR_EF ? ", FPU" : "";
1027 cm = cpu_psr_all & PSR_CM ? ", CCCR" : "";
1028 nem = cpu_psr_all & PSR_NEM ? ", NE" : "";
1029 ble = cpu_psr_all & PSR_BE ? "BE" : "LE";
1030
1031 seq_printf(m,
1032 "CPU-Series:\t%s\n"
1033 "CPU-Core:\t%s, %s, %s%s%s\n"
1034 "CPU:\t\t%s\n"
1035 "MMU:\t\t%s\n"
1036 "FP-Media:\t%s%s%s\n"
1037 "System:\t\t%s",
1038 cpu_series,
1039 cpu_core, gr, ble, cm, nem,
1040 cpu_silicon,
1041 cpu_mmu,
1042 fr, fm, fp,
1043 cpu_system);
1044
1045 if (cpu_board1)
1046 seq_printf(m, ", %s", cpu_board1);
1047
1048 if (cpu_board2)
1049 seq_printf(m, ", %s", cpu_board2);
1050
1051 seq_printf(m, "\n");
1052
1053#ifdef CONFIG_PM
1054 seq_printf(m, "PM-Controls:");
1055 sep = "\t";
1056
1057 if (clock_bits_settable & CLOCK_BIT_CMODE) {
1058 seq_printf(m, "%scmode=0x%04hx", sep, clock_cmodes_permitted);
1059 sep = ", ";
1060 }
1061
1062 if (clock_bits_settable & CLOCK_BIT_CM) {
1063 seq_printf(m, "%scm=0x%lx", sep, clock_bits_settable & CLOCK_BIT_CM);
1064 sep = ", ";
1065 }
1066
1067 if (clock_bits_settable & CLOCK_BIT_P0) {
1068 seq_printf(m, "%sp0=0x3", sep);
1069 sep = ", ";
1070 }
1071
1072 seq_printf(m, "%ssuspend=0x22\n", sep);
1073#endif
1074
1075 seq_printf(m,
1076 "PM-Status:\tcmode=%d, cm=%d, p0=%d\n",
1077 clock_cmode_current, clock_cm_current, clock_p0_current);
1078
1079#define print_clk(TAG, VAR) \
1080 seq_printf(m, "Clock-" TAG ":\t%lu.%2.2lu MHz\n", VAR / 1000000, (VAR / 10000) % 100)
1081
1082 print_clk("In", __clkin_clock_speed_HZ);
1083 print_clk("Core", __core_clock_speed_HZ);
1084 print_clk("SDRAM", __sdram_clock_speed_HZ);
1085 print_clk("CBus", __core_bus_clock_speed_HZ);
1086 print_clk("Res", __res_bus_clock_speed_HZ);
1087 print_clk("Ext", __ext_bus_clock_speed_HZ);
1088 print_clk("DSU", __dsu_clock_speed_HZ);
1089
1090 seq_printf(m,
1091 "BogoMips:\t%lu.%02lu\n",
1092 (loops_per_jiffy * HZ) / 500000, ((loops_per_jiffy * HZ) / 5000) % 100);
1093
1094 return 0;
1095} /* end show_cpuinfo() */
1096
1097static void *c_start(struct seq_file *m, loff_t *pos)
1098{
1099 return *pos < NR_CPUS ? (void *) 0x12345678 : NULL;
1100}
1101
1102static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1103{
1104 ++*pos;
1105 return c_start(m, pos);
1106}
1107
1108static void c_stop(struct seq_file *m, void *v)
1109{
1110}
1111
1112struct seq_operations cpuinfo_op = {
1113 .start = c_start,
1114 .next = c_next,
1115 .stop = c_stop,
1116 .show = show_cpuinfo,
1117};
1118
1119void arch_gettod(int *year, int *mon, int *day, int *hour,
1120 int *min, int *sec)
1121{
1122 *year = *mon = *day = *hour = *min = *sec = 0;
1123}
1124
1125/*****************************************************************************/
1126/*
1127 *
1128 */
1129#ifdef CONFIG_MB93090_MB00
1130static void __init mb93090_sendlcdcmd(uint32_t cmd)
1131{
1132 unsigned long base = __addr_LCD();
1133 int loop;
1134
1135 /* request reading of the busy flag */
1136 __set_LCD(base, LCD_CMD_READ_BUSY);
1137 __set_LCD(base, LCD_CMD_READ_BUSY & ~LCD_E);
1138
1139 /* wait for the busy flag to become clear */
1140 for (loop = 10000; loop > 0; loop--)
1141 if (!(__get_LCD(base) & 0x80))
1142 break;
1143
1144 /* send the command */
1145 __set_LCD(base, cmd);
1146 __set_LCD(base, cmd & ~LCD_E);
1147
1148} /* end mb93090_sendlcdcmd() */
1149
1150/*****************************************************************************/
1151/*
1152 * write to the MB93090 LEDs and LCD
1153 */
1154static void __init mb93090_display(void)
1155{
1156 const char *p;
1157
1158 __set_LEDS(0);
1159
1160 /* set up the LCD */
1161 mb93090_sendlcdcmd(LCD_CMD_CLEAR);
1162 mb93090_sendlcdcmd(LCD_CMD_FUNCSET(1,1,0));
1163 mb93090_sendlcdcmd(LCD_CMD_ON(0,0));
1164 mb93090_sendlcdcmd(LCD_CMD_HOME);
1165
1166 mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(0));
1167 for (p = mb93090_banner; *p; p++)
1168 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1169
1170 mb93090_sendlcdcmd(LCD_CMD_SET_DD_ADDR(64));
1171 for (p = mb93090_version; *p; p++)
1172 mb93090_sendlcdcmd(LCD_DATA_WRITE(*p));
1173
1174} /* end mb93090_display() */
1175
1176#endif // CONFIG_MB93090_MB00
Linux kernel - Deliverables
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