Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <linux/mm.h> | |
1da177e4 LT |
21 | #include <linux/delay.h> |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/smp_lock.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/mc146818rtc.h> | |
26 | #include <linux/kernel_stat.h> | |
27 | #include <linux/sysdev.h> | |
f3705136 | 28 | #include <linux/cpu.h> |
6eb0a0fd | 29 | #include <linux/module.h> |
1da177e4 LT |
30 | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/mtrr.h> | |
34 | #include <asm/mpspec.h> | |
35 | #include <asm/desc.h> | |
36 | #include <asm/arch_hooks.h> | |
37 | #include <asm/hpet.h> | |
306e440d | 38 | #include <asm/i8253.h> |
1da177e4 LT |
39 | |
40 | #include <mach_apic.h> | |
6eb0a0fd | 41 | #include <mach_ipi.h> |
1da177e4 LT |
42 | |
43 | #include "io_ports.h" | |
44 | ||
6eb0a0fd VP |
45 | /* |
46 | * cpu_mask that denotes the CPUs that needs timer interrupt coming in as | |
47 | * IPIs in place of local APIC timers | |
48 | */ | |
49 | static cpumask_t timer_bcast_ipi; | |
50 | ||
9635b47d EB |
51 | /* |
52 | * Knob to control our willingness to enable the local APIC. | |
53 | */ | |
54 | int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */ | |
55 | ||
1da177e4 LT |
56 | /* |
57 | * Debug level | |
58 | */ | |
59 | int apic_verbosity; | |
60 | ||
61 | ||
62 | static void apic_pm_activate(void); | |
63 | ||
64 | /* | |
65 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
66 | * each architecture has to answer this themselves. | |
67 | */ | |
68 | void ack_bad_irq(unsigned int irq) | |
69 | { | |
70 | printk("unexpected IRQ trap at vector %02x\n", irq); | |
71 | /* | |
72 | * Currently unexpected vectors happen only on SMP and APIC. | |
73 | * We _must_ ack these because every local APIC has only N | |
74 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
75 | * holds up an irq slot - in excessive cases (when multiple | |
76 | * unexpected vectors occur) that might lock up the APIC | |
77 | * completely. | |
3777a959 | 78 | * But only ack when the APIC is enabled -AK |
1da177e4 | 79 | */ |
e1a8e6c9 | 80 | if (cpu_has_apic) |
3777a959 | 81 | ack_APIC_irq(); |
1da177e4 LT |
82 | } |
83 | ||
84 | void __init apic_intr_init(void) | |
85 | { | |
86 | #ifdef CONFIG_SMP | |
87 | smp_intr_init(); | |
88 | #endif | |
89 | /* self generated IPI for local APIC timer */ | |
90 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
91 | ||
92 | /* IPI vectors for APIC spurious and error interrupts */ | |
93 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
94 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
95 | ||
96 | /* thermal monitor LVT interrupt */ | |
97 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
98 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
99 | #endif | |
100 | } | |
101 | ||
102 | /* Using APIC to generate smp_local_timer_interrupt? */ | |
103 | int using_apic_timer = 0; | |
104 | ||
1da177e4 LT |
105 | static int enabled_via_apicbase; |
106 | ||
107 | void enable_NMI_through_LVT0 (void * dummy) | |
108 | { | |
109 | unsigned int v, ver; | |
110 | ||
111 | ver = apic_read(APIC_LVR); | |
112 | ver = GET_APIC_VERSION(ver); | |
113 | v = APIC_DM_NMI; /* unmask and set to NMI */ | |
114 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
115 | v |= APIC_LVT_LEVEL_TRIGGER; | |
116 | apic_write_around(APIC_LVT0, v); | |
117 | } | |
118 | ||
119 | int get_physical_broadcast(void) | |
120 | { | |
121 | unsigned int lvr, version; | |
122 | lvr = apic_read(APIC_LVR); | |
123 | version = GET_APIC_VERSION(lvr); | |
124 | if (!APIC_INTEGRATED(version) || version >= 0x14) | |
125 | return 0xff; | |
126 | else | |
127 | return 0xf; | |
128 | } | |
129 | ||
130 | int get_maxlvt(void) | |
131 | { | |
132 | unsigned int v, ver, maxlvt; | |
133 | ||
134 | v = apic_read(APIC_LVR); | |
135 | ver = GET_APIC_VERSION(v); | |
136 | /* 82489DXs do not report # of LVT entries. */ | |
137 | maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2; | |
138 | return maxlvt; | |
139 | } | |
140 | ||
141 | void clear_local_APIC(void) | |
142 | { | |
143 | int maxlvt; | |
144 | unsigned long v; | |
145 | ||
146 | maxlvt = get_maxlvt(); | |
147 | ||
148 | /* | |
149 | * Masking an LVT entry on a P6 can trigger a local APIC error | |
150 | * if the vector is zero. Mask LVTERR first to prevent this. | |
151 | */ | |
152 | if (maxlvt >= 3) { | |
153 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
154 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
155 | } | |
156 | /* | |
157 | * Careful: we have to set masks only first to deassert | |
158 | * any level-triggered sources. | |
159 | */ | |
160 | v = apic_read(APIC_LVTT); | |
161 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
162 | v = apic_read(APIC_LVT0); | |
163 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
164 | v = apic_read(APIC_LVT1); | |
165 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
166 | if (maxlvt >= 4) { | |
167 | v = apic_read(APIC_LVTPC); | |
168 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
169 | } | |
170 | ||
171 | /* lets not touch this if we didn't frob it */ | |
172 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
173 | if (maxlvt >= 5) { | |
174 | v = apic_read(APIC_LVTTHMR); | |
175 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
176 | } | |
177 | #endif | |
178 | /* | |
179 | * Clean APIC state for other OSs: | |
180 | */ | |
181 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); | |
182 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
183 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
184 | if (maxlvt >= 3) | |
185 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
186 | if (maxlvt >= 4) | |
187 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
188 | ||
189 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
190 | if (maxlvt >= 5) | |
191 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
192 | #endif | |
193 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
194 | if (APIC_INTEGRATED(v)) { /* !82489DX */ | |
195 | if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */ | |
196 | apic_write(APIC_ESR, 0); | |
197 | apic_read(APIC_ESR); | |
198 | } | |
199 | } | |
200 | ||
201 | void __init connect_bsp_APIC(void) | |
202 | { | |
203 | if (pic_mode) { | |
204 | /* | |
205 | * Do not trust the local APIC being empty at bootup. | |
206 | */ | |
207 | clear_local_APIC(); | |
208 | /* | |
209 | * PIC mode, enable APIC mode in the IMCR, i.e. | |
210 | * connect BSP's local APIC to INT and NMI lines. | |
211 | */ | |
212 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
213 | "enabling APIC mode.\n"); | |
214 | outb(0x70, 0x22); | |
215 | outb(0x01, 0x23); | |
216 | } | |
217 | enable_apic_mode(); | |
218 | } | |
219 | ||
650927ef | 220 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 LT |
221 | { |
222 | if (pic_mode) { | |
223 | /* | |
224 | * Put the board back into PIC mode (has an effect | |
225 | * only on certain older boards). Note that APIC | |
226 | * interrupts, including IPIs, won't work beyond | |
227 | * this point! The only exception are INIT IPIs. | |
228 | */ | |
229 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
230 | "entering PIC mode.\n"); | |
231 | outb(0x70, 0x22); | |
232 | outb(0x00, 0x23); | |
233 | } | |
650927ef EB |
234 | else { |
235 | /* Go back to Virtual Wire compatibility mode */ | |
236 | unsigned long value; | |
237 | ||
238 | /* For the spurious interrupt use vector F, and enable it */ | |
239 | value = apic_read(APIC_SPIV); | |
240 | value &= ~APIC_VECTOR_MASK; | |
241 | value |= APIC_SPIV_APIC_ENABLED; | |
242 | value |= 0xf; | |
243 | apic_write_around(APIC_SPIV, value); | |
244 | ||
245 | if (!virt_wire_setup) { | |
246 | /* For LVT0 make it edge triggered, active high, external and enabled */ | |
247 | value = apic_read(APIC_LVT0); | |
248 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
249 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
250 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
251 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
252 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
253 | apic_write_around(APIC_LVT0, value); | |
254 | } | |
255 | else { | |
256 | /* Disable LVT0 */ | |
257 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
258 | } | |
259 | ||
260 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
261 | value = apic_read(APIC_LVT1); | |
262 | value &= ~( | |
263 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
264 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
265 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
266 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
267 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
268 | apic_write_around(APIC_LVT1, value); | |
269 | } | |
1da177e4 LT |
270 | } |
271 | ||
272 | void disable_local_APIC(void) | |
273 | { | |
274 | unsigned long value; | |
275 | ||
276 | clear_local_APIC(); | |
277 | ||
278 | /* | |
279 | * Disable APIC (implies clearing of registers | |
280 | * for 82489DX!). | |
281 | */ | |
282 | value = apic_read(APIC_SPIV); | |
283 | value &= ~APIC_SPIV_APIC_ENABLED; | |
284 | apic_write_around(APIC_SPIV, value); | |
285 | ||
286 | if (enabled_via_apicbase) { | |
287 | unsigned int l, h; | |
288 | rdmsr(MSR_IA32_APICBASE, l, h); | |
289 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
290 | wrmsr(MSR_IA32_APICBASE, l, h); | |
291 | } | |
292 | } | |
293 | ||
294 | /* | |
295 | * This is to verify that we're looking at a real local APIC. | |
296 | * Check these against your board if the CPUs aren't getting | |
297 | * started for no apparent reason. | |
298 | */ | |
299 | int __init verify_local_APIC(void) | |
300 | { | |
301 | unsigned int reg0, reg1; | |
302 | ||
303 | /* | |
304 | * The version register is read-only in a real APIC. | |
305 | */ | |
306 | reg0 = apic_read(APIC_LVR); | |
307 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
308 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
309 | reg1 = apic_read(APIC_LVR); | |
310 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
311 | ||
312 | /* | |
313 | * The two version reads above should print the same | |
314 | * numbers. If the second one is different, then we | |
315 | * poke at a non-APIC. | |
316 | */ | |
317 | if (reg1 != reg0) | |
318 | return 0; | |
319 | ||
320 | /* | |
321 | * Check if the version looks reasonably. | |
322 | */ | |
323 | reg1 = GET_APIC_VERSION(reg0); | |
324 | if (reg1 == 0x00 || reg1 == 0xff) | |
325 | return 0; | |
326 | reg1 = get_maxlvt(); | |
327 | if (reg1 < 0x02 || reg1 == 0xff) | |
328 | return 0; | |
329 | ||
330 | /* | |
331 | * The ID register is read/write in a real APIC. | |
332 | */ | |
333 | reg0 = apic_read(APIC_ID); | |
334 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
335 | ||
336 | /* | |
337 | * The next two are just to see if we have sane values. | |
338 | * They're only really relevant if we're in Virtual Wire | |
339 | * compatibility mode, but most boxes are anymore. | |
340 | */ | |
341 | reg0 = apic_read(APIC_LVT0); | |
342 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
343 | reg1 = apic_read(APIC_LVT1); | |
344 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
345 | ||
346 | return 1; | |
347 | } | |
348 | ||
349 | void __init sync_Arb_IDs(void) | |
350 | { | |
351 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
352 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
353 | if (ver >= 0x14) /* P4 or higher */ | |
354 | return; | |
355 | /* | |
356 | * Wait for idle. | |
357 | */ | |
358 | apic_wait_icr_idle(); | |
359 | ||
360 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
361 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
362 | | APIC_DM_INIT); | |
363 | } | |
364 | ||
365 | extern void __error_in_apic_c (void); | |
366 | ||
367 | /* | |
368 | * An initial setup of the virtual wire mode. | |
369 | */ | |
370 | void __init init_bsp_APIC(void) | |
371 | { | |
372 | unsigned long value, ver; | |
373 | ||
374 | /* | |
375 | * Don't do the setup now if we have a SMP BIOS as the | |
376 | * through-I/O-APIC virtual wire mode might be active. | |
377 | */ | |
378 | if (smp_found_config || !cpu_has_apic) | |
379 | return; | |
380 | ||
381 | value = apic_read(APIC_LVR); | |
382 | ver = GET_APIC_VERSION(value); | |
383 | ||
384 | /* | |
385 | * Do not trust the local APIC being empty at bootup. | |
386 | */ | |
387 | clear_local_APIC(); | |
388 | ||
389 | /* | |
390 | * Enable APIC. | |
391 | */ | |
392 | value = apic_read(APIC_SPIV); | |
393 | value &= ~APIC_VECTOR_MASK; | |
394 | value |= APIC_SPIV_APIC_ENABLED; | |
395 | ||
396 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
397 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15)) | |
398 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
399 | else | |
400 | value |= APIC_SPIV_FOCUS_DISABLED; | |
401 | value |= SPURIOUS_APIC_VECTOR; | |
402 | apic_write_around(APIC_SPIV, value); | |
403 | ||
404 | /* | |
405 | * Set up the virtual wire mode. | |
406 | */ | |
407 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
408 | value = APIC_DM_NMI; | |
409 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
410 | value |= APIC_LVT_LEVEL_TRIGGER; | |
411 | apic_write_around(APIC_LVT1, value); | |
412 | } | |
413 | ||
0bb3184d | 414 | void __devinit setup_local_APIC(void) |
1da177e4 LT |
415 | { |
416 | unsigned long oldvalue, value, ver, maxlvt; | |
417 | ||
418 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
419 | if (esr_disable) { | |
420 | apic_write(APIC_ESR, 0); | |
421 | apic_write(APIC_ESR, 0); | |
422 | apic_write(APIC_ESR, 0); | |
423 | apic_write(APIC_ESR, 0); | |
424 | } | |
425 | ||
426 | value = apic_read(APIC_LVR); | |
427 | ver = GET_APIC_VERSION(value); | |
428 | ||
429 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) | |
430 | __error_in_apic_c(); | |
431 | ||
432 | /* | |
433 | * Double-check whether this APIC is really registered. | |
434 | */ | |
435 | if (!apic_id_registered()) | |
436 | BUG(); | |
437 | ||
438 | /* | |
439 | * Intel recommends to set DFR, LDR and TPR before enabling | |
440 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
441 | * document number 292116). So here it goes... | |
442 | */ | |
443 | init_apic_ldr(); | |
444 | ||
445 | /* | |
446 | * Set Task Priority to 'accept all'. We never change this | |
447 | * later on. | |
448 | */ | |
449 | value = apic_read(APIC_TASKPRI); | |
450 | value &= ~APIC_TPRI_MASK; | |
451 | apic_write_around(APIC_TASKPRI, value); | |
452 | ||
453 | /* | |
454 | * Now that we are all set up, enable the APIC | |
455 | */ | |
456 | value = apic_read(APIC_SPIV); | |
457 | value &= ~APIC_VECTOR_MASK; | |
458 | /* | |
459 | * Enable APIC | |
460 | */ | |
461 | value |= APIC_SPIV_APIC_ENABLED; | |
462 | ||
463 | /* | |
464 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
465 | * certain networking cards. If high frequency interrupts are | |
466 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
467 | * entry is masked/unmasked at a high rate as well then sooner or | |
468 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
469 | * from the device. If focus CPU is disabled then the hang goes | |
470 | * away, oh well :-( | |
471 | * | |
472 | * [ This bug can be reproduced easily with a level-triggered | |
473 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
474 | * BX chipset. ] | |
475 | */ | |
476 | /* | |
477 | * Actually disabling the focus CPU check just makes the hang less | |
478 | * frequent as it makes the interrupt distributon model be more | |
479 | * like LRU than MRU (the short-term load is more even across CPUs). | |
480 | * See also the comment in end_level_ioapic_irq(). --macro | |
481 | */ | |
482 | #if 1 | |
483 | /* Enable focus processor (bit==0) */ | |
484 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
485 | #else | |
486 | /* Disable focus processor (bit==1) */ | |
487 | value |= APIC_SPIV_FOCUS_DISABLED; | |
488 | #endif | |
489 | /* | |
490 | * Set spurious IRQ vector | |
491 | */ | |
492 | value |= SPURIOUS_APIC_VECTOR; | |
493 | apic_write_around(APIC_SPIV, value); | |
494 | ||
495 | /* | |
496 | * Set up LVT0, LVT1: | |
497 | * | |
498 | * set up through-local-APIC on the BP's LINT0. This is not | |
499 | * strictly necessery in pure symmetric-IO mode, but sometimes | |
500 | * we delegate interrupts to the 8259A. | |
501 | */ | |
502 | /* | |
503 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
504 | */ | |
505 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
506 | if (!smp_processor_id() && (pic_mode || !value)) { | |
507 | value = APIC_DM_EXTINT; | |
508 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
509 | smp_processor_id()); | |
510 | } else { | |
511 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
512 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
513 | smp_processor_id()); | |
514 | } | |
515 | apic_write_around(APIC_LVT0, value); | |
516 | ||
517 | /* | |
518 | * only the BP should see the LINT1 NMI signal, obviously. | |
519 | */ | |
520 | if (!smp_processor_id()) | |
521 | value = APIC_DM_NMI; | |
522 | else | |
523 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
524 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
525 | value |= APIC_LVT_LEVEL_TRIGGER; | |
526 | apic_write_around(APIC_LVT1, value); | |
527 | ||
528 | if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */ | |
529 | maxlvt = get_maxlvt(); | |
530 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
531 | apic_write(APIC_ESR, 0); | |
532 | oldvalue = apic_read(APIC_ESR); | |
533 | ||
534 | value = ERROR_APIC_VECTOR; // enables sending errors | |
535 | apic_write_around(APIC_LVTERR, value); | |
536 | /* | |
537 | * spec says clear errors after enabling vector. | |
538 | */ | |
539 | if (maxlvt > 3) | |
540 | apic_write(APIC_ESR, 0); | |
541 | value = apic_read(APIC_ESR); | |
542 | if (value != oldvalue) | |
543 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
544 | "vector: 0x%08lx after: 0x%08lx\n", | |
545 | oldvalue, value); | |
546 | } else { | |
547 | if (esr_disable) | |
548 | /* | |
549 | * Something untraceble is creating bad interrupts on | |
550 | * secondary quads ... for the moment, just leave the | |
551 | * ESR disabled - we can't do anything useful with the | |
552 | * errors anyway - mbligh | |
553 | */ | |
554 | printk("Leaving ESR disabled.\n"); | |
555 | else | |
556 | printk("No ESR for 82489DX.\n"); | |
557 | } | |
558 | ||
559 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
560 | setup_apic_nmi_watchdog(); | |
561 | apic_pm_activate(); | |
562 | } | |
563 | ||
564 | /* | |
565 | * If Linux enabled the LAPIC against the BIOS default | |
566 | * disable it down before re-entering the BIOS on shutdown. | |
567 | * Otherwise the BIOS may get confused and not power-off. | |
77f72b19 ZM |
568 | * Additionally clear all LVT entries before disable_local_APIC |
569 | * for the case where Linux didn't enable the LAPIC. | |
1da177e4 LT |
570 | */ |
571 | void lapic_shutdown(void) | |
572 | { | |
67963132 MS |
573 | unsigned long flags; |
574 | ||
77f72b19 | 575 | if (!cpu_has_apic) |
1da177e4 LT |
576 | return; |
577 | ||
67963132 | 578 | local_irq_save(flags); |
77f72b19 ZM |
579 | clear_local_APIC(); |
580 | ||
581 | if (enabled_via_apicbase) | |
582 | disable_local_APIC(); | |
583 | ||
67963132 | 584 | local_irq_restore(flags); |
1da177e4 LT |
585 | } |
586 | ||
587 | #ifdef CONFIG_PM | |
588 | ||
589 | static struct { | |
590 | int active; | |
591 | /* r/w apic fields */ | |
592 | unsigned int apic_id; | |
593 | unsigned int apic_taskpri; | |
594 | unsigned int apic_ldr; | |
595 | unsigned int apic_dfr; | |
596 | unsigned int apic_spiv; | |
597 | unsigned int apic_lvtt; | |
598 | unsigned int apic_lvtpc; | |
599 | unsigned int apic_lvt0; | |
600 | unsigned int apic_lvt1; | |
601 | unsigned int apic_lvterr; | |
602 | unsigned int apic_tmict; | |
603 | unsigned int apic_tdcr; | |
604 | unsigned int apic_thmr; | |
605 | } apic_pm_state; | |
606 | ||
438510f6 | 607 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
608 | { |
609 | unsigned long flags; | |
610 | ||
611 | if (!apic_pm_state.active) | |
612 | return 0; | |
613 | ||
614 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
615 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
616 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
617 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
618 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
619 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
620 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
621 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
622 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
623 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
624 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
625 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
626 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
627 | ||
628 | local_irq_save(flags); | |
629 | disable_local_APIC(); | |
630 | local_irq_restore(flags); | |
631 | return 0; | |
632 | } | |
633 | ||
634 | static int lapic_resume(struct sys_device *dev) | |
635 | { | |
636 | unsigned int l, h; | |
637 | unsigned long flags; | |
638 | ||
639 | if (!apic_pm_state.active) | |
640 | return 0; | |
641 | ||
642 | local_irq_save(flags); | |
643 | ||
644 | /* | |
645 | * Make sure the APICBASE points to the right address | |
646 | * | |
647 | * FIXME! This will be wrong if we ever support suspend on | |
648 | * SMP! We'll need to do this as part of the CPU restore! | |
649 | */ | |
650 | rdmsr(MSR_IA32_APICBASE, l, h); | |
651 | l &= ~MSR_IA32_APICBASE_BASE; | |
652 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
653 | wrmsr(MSR_IA32_APICBASE, l, h); | |
654 | ||
655 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
656 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
657 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
658 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
659 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
660 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
661 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
662 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
663 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
664 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
665 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
666 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
667 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
668 | apic_write(APIC_ESR, 0); | |
669 | apic_read(APIC_ESR); | |
670 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
671 | apic_write(APIC_ESR, 0); | |
672 | apic_read(APIC_ESR); | |
673 | local_irq_restore(flags); | |
674 | return 0; | |
675 | } | |
676 | ||
677 | /* | |
678 | * This device has no shutdown method - fully functioning local APICs | |
679 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
680 | */ | |
681 | ||
682 | static struct sysdev_class lapic_sysclass = { | |
683 | set_kset_name("lapic"), | |
684 | .resume = lapic_resume, | |
685 | .suspend = lapic_suspend, | |
686 | }; | |
687 | ||
688 | static struct sys_device device_lapic = { | |
689 | .id = 0, | |
690 | .cls = &lapic_sysclass, | |
691 | }; | |
692 | ||
0bb3184d | 693 | static void __devinit apic_pm_activate(void) |
1da177e4 LT |
694 | { |
695 | apic_pm_state.active = 1; | |
696 | } | |
697 | ||
698 | static int __init init_lapic_sysfs(void) | |
699 | { | |
700 | int error; | |
701 | ||
702 | if (!cpu_has_apic) | |
703 | return 0; | |
704 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
705 | ||
706 | error = sysdev_class_register(&lapic_sysclass); | |
707 | if (!error) | |
708 | error = sysdev_register(&device_lapic); | |
709 | return error; | |
710 | } | |
711 | device_initcall(init_lapic_sysfs); | |
712 | ||
713 | #else /* CONFIG_PM */ | |
714 | ||
715 | static void apic_pm_activate(void) { } | |
716 | ||
717 | #endif /* CONFIG_PM */ | |
718 | ||
719 | /* | |
720 | * Detect and enable local APICs on non-SMP boards. | |
721 | * Original code written by Keir Fraser. | |
722 | */ | |
723 | ||
1da177e4 LT |
724 | static int __init apic_set_verbosity(char *str) |
725 | { | |
726 | if (strcmp("debug", str) == 0) | |
727 | apic_verbosity = APIC_DEBUG; | |
728 | else if (strcmp("verbose", str) == 0) | |
729 | apic_verbosity = APIC_VERBOSE; | |
730 | else | |
731 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
e31b88ba | 732 | " use apic=verbose or apic=debug\n", str); |
1da177e4 LT |
733 | |
734 | return 0; | |
735 | } | |
736 | ||
737 | __setup("apic=", apic_set_verbosity); | |
738 | ||
739 | static int __init detect_init_APIC (void) | |
740 | { | |
741 | u32 h, l, features; | |
1da177e4 LT |
742 | |
743 | /* Disabled by kernel option? */ | |
744 | if (enable_local_apic < 0) | |
745 | return -1; | |
746 | ||
1da177e4 LT |
747 | switch (boot_cpu_data.x86_vendor) { |
748 | case X86_VENDOR_AMD: | |
749 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
750 | (boot_cpu_data.x86 == 15)) | |
751 | break; | |
752 | goto no_apic; | |
753 | case X86_VENDOR_INTEL: | |
754 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
755 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
756 | break; | |
757 | goto no_apic; | |
758 | default: | |
759 | goto no_apic; | |
760 | } | |
761 | ||
762 | if (!cpu_has_apic) { | |
763 | /* | |
764 | * Over-ride BIOS and try to enable the local | |
765 | * APIC only if "lapic" specified. | |
766 | */ | |
767 | if (enable_local_apic <= 0) { | |
768 | printk("Local APIC disabled by BIOS -- " | |
769 | "you can enable it with \"lapic\"\n"); | |
770 | return -1; | |
771 | } | |
772 | /* | |
773 | * Some BIOSes disable the local APIC in the | |
774 | * APIC_BASE MSR. This can only be done in | |
775 | * software for Intel P6 or later and AMD K7 | |
776 | * (Model > 1) or later. | |
777 | */ | |
778 | rdmsr(MSR_IA32_APICBASE, l, h); | |
779 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
780 | printk("Local APIC disabled by BIOS -- reenabling.\n"); | |
781 | l &= ~MSR_IA32_APICBASE_BASE; | |
782 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
783 | wrmsr(MSR_IA32_APICBASE, l, h); | |
784 | enabled_via_apicbase = 1; | |
785 | } | |
786 | } | |
787 | /* | |
788 | * The APIC feature bit should now be enabled | |
789 | * in `cpuid' | |
790 | */ | |
791 | features = cpuid_edx(1); | |
792 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
793 | printk("Could not enable APIC!\n"); | |
794 | return -1; | |
795 | } | |
796 | set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
797 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
798 | ||
799 | /* The BIOS may have set up the APIC at some other address */ | |
800 | rdmsr(MSR_IA32_APICBASE, l, h); | |
801 | if (l & MSR_IA32_APICBASE_ENABLE) | |
802 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
803 | ||
804 | if (nmi_watchdog != NMI_NONE) | |
805 | nmi_watchdog = NMI_LOCAL_APIC; | |
806 | ||
807 | printk("Found and enabled local APIC!\n"); | |
808 | ||
809 | apic_pm_activate(); | |
810 | ||
811 | return 0; | |
812 | ||
813 | no_apic: | |
814 | printk("No local APIC present or hardware disabled\n"); | |
815 | return -1; | |
816 | } | |
817 | ||
818 | void __init init_apic_mappings(void) | |
819 | { | |
820 | unsigned long apic_phys; | |
821 | ||
822 | /* | |
823 | * If no local APIC can be found then set up a fake all | |
824 | * zeroes page to simulate the local APIC and another | |
825 | * one for the IO-APIC. | |
826 | */ | |
827 | if (!smp_found_config && detect_init_APIC()) { | |
828 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
829 | apic_phys = __pa(apic_phys); | |
830 | } else | |
831 | apic_phys = mp_lapic_addr; | |
832 | ||
833 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
834 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
835 | apic_phys); | |
836 | ||
837 | /* | |
838 | * Fetch the APIC ID of the BSP in case we have a | |
839 | * default configuration (or the MP table is broken). | |
840 | */ | |
1e4c85f9 LT |
841 | if (boot_cpu_physical_apicid == -1U) |
842 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 LT |
843 | |
844 | #ifdef CONFIG_X86_IO_APIC | |
845 | { | |
846 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
847 | int i; | |
848 | ||
849 | for (i = 0; i < nr_ioapics; i++) { | |
850 | if (smp_found_config) { | |
851 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
852 | if (!ioapic_phys) { | |
853 | printk(KERN_ERR | |
854 | "WARNING: bogus zero IO-APIC " | |
855 | "address found in MPTABLE, " | |
856 | "disabling IO/APIC support!\n"); | |
857 | smp_found_config = 0; | |
858 | skip_ioapic_setup = 1; | |
859 | goto fake_ioapic_page; | |
860 | } | |
861 | } else { | |
862 | fake_ioapic_page: | |
863 | ioapic_phys = (unsigned long) | |
864 | alloc_bootmem_pages(PAGE_SIZE); | |
865 | ioapic_phys = __pa(ioapic_phys); | |
866 | } | |
867 | set_fixmap_nocache(idx, ioapic_phys); | |
868 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
869 | __fix_to_virt(idx), ioapic_phys); | |
870 | idx++; | |
871 | } | |
872 | } | |
873 | #endif | |
874 | } | |
875 | ||
876 | /* | |
877 | * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts | |
878 | * per second. We assume that the caller has already set up the local | |
879 | * APIC. | |
880 | * | |
881 | * The APIC timer is not exactly sync with the external timer chip, it | |
882 | * closely follows bus clocks. | |
883 | */ | |
884 | ||
885 | /* | |
886 | * The timer chip is already set up at HZ interrupts per second here, | |
887 | * but we do not accept timer interrupts yet. We only allow the BP | |
888 | * to calibrate. | |
889 | */ | |
0bb3184d | 890 | static unsigned int __devinit get_8254_timer_count(void) |
1da177e4 | 891 | { |
1da177e4 LT |
892 | unsigned long flags; |
893 | ||
894 | unsigned int count; | |
895 | ||
896 | spin_lock_irqsave(&i8253_lock, flags); | |
897 | ||
898 | outb_p(0x00, PIT_MODE); | |
899 | count = inb_p(PIT_CH0); | |
900 | count |= inb_p(PIT_CH0) << 8; | |
901 | ||
902 | spin_unlock_irqrestore(&i8253_lock, flags); | |
903 | ||
904 | return count; | |
905 | } | |
906 | ||
907 | /* next tick in 8254 can be caught by catching timer wraparound */ | |
0bb3184d | 908 | static void __devinit wait_8254_wraparound(void) |
1da177e4 LT |
909 | { |
910 | unsigned int curr_count, prev_count; | |
911 | ||
912 | curr_count = get_8254_timer_count(); | |
913 | do { | |
914 | prev_count = curr_count; | |
915 | curr_count = get_8254_timer_count(); | |
916 | ||
917 | /* workaround for broken Mercury/Neptune */ | |
918 | if (prev_count >= curr_count + 0x100) | |
919 | curr_count = get_8254_timer_count(); | |
920 | ||
921 | } while (prev_count >= curr_count); | |
922 | } | |
923 | ||
924 | /* | |
925 | * Default initialization for 8254 timers. If we use other timers like HPET, | |
926 | * we override this later | |
927 | */ | |
0bb3184d | 928 | void (*wait_timer_tick)(void) __devinitdata = wait_8254_wraparound; |
1da177e4 LT |
929 | |
930 | /* | |
931 | * This function sets up the local APIC timer, with a timeout of | |
932 | * 'clocks' APIC bus clock. During calibration we actually call | |
933 | * this function twice on the boot CPU, once with a bogus timeout | |
934 | * value, second time for real. The other (noncalibrating) CPUs | |
935 | * call this function only once, with the real, calibrated value. | |
936 | * | |
937 | * We do reads before writes even if unnecessary, to get around the | |
938 | * P5 APIC double write bug. | |
939 | */ | |
940 | ||
941 | #define APIC_DIVISOR 16 | |
942 | ||
943 | static void __setup_APIC_LVTT(unsigned int clocks) | |
944 | { | |
945 | unsigned int lvtt_value, tmp_value, ver; | |
6eb0a0fd | 946 | int cpu = smp_processor_id(); |
1da177e4 LT |
947 | |
948 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
949 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; | |
950 | if (!APIC_INTEGRATED(ver)) | |
951 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
6eb0a0fd VP |
952 | |
953 | if (cpu_isset(cpu, timer_bcast_ipi)) | |
954 | lvtt_value |= APIC_LVT_MASKED; | |
955 | ||
1da177e4 LT |
956 | apic_write_around(APIC_LVTT, lvtt_value); |
957 | ||
958 | /* | |
959 | * Divide PICLK by 16 | |
960 | */ | |
961 | tmp_value = apic_read(APIC_TDCR); | |
962 | apic_write_around(APIC_TDCR, (tmp_value | |
963 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
964 | | APIC_TDR_DIV_16); | |
965 | ||
966 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
967 | } | |
968 | ||
0bb3184d | 969 | static void __devinit setup_APIC_timer(unsigned int clocks) |
1da177e4 LT |
970 | { |
971 | unsigned long flags; | |
972 | ||
973 | local_irq_save(flags); | |
974 | ||
975 | /* | |
976 | * Wait for IRQ0's slice: | |
977 | */ | |
978 | wait_timer_tick(); | |
979 | ||
980 | __setup_APIC_LVTT(clocks); | |
981 | ||
982 | local_irq_restore(flags); | |
983 | } | |
984 | ||
985 | /* | |
986 | * In this function we calibrate APIC bus clocks to the external | |
987 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
988 | * to calibrate, since some later bootup code depends on getting | |
989 | * the first irq? Ugh. | |
990 | * | |
991 | * We want to do the calibration only once since we | |
992 | * want to have local timer irqs syncron. CPUs connected | |
993 | * by the same APIC bus have the very same bus frequency. | |
994 | * And we want to have irqs off anyways, no accidental | |
995 | * APIC irq that way. | |
996 | */ | |
997 | ||
998 | static int __init calibrate_APIC_clock(void) | |
999 | { | |
1000 | unsigned long long t1 = 0, t2 = 0; | |
1001 | long tt1, tt2; | |
1002 | long result; | |
1003 | int i; | |
1004 | const int LOOPS = HZ/10; | |
1005 | ||
1006 | apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n"); | |
1007 | ||
1008 | /* | |
1009 | * Put whatever arbitrary (but long enough) timeout | |
1010 | * value into the APIC clock, we just want to get the | |
1011 | * counter running for calibration. | |
1012 | */ | |
1013 | __setup_APIC_LVTT(1000000000); | |
1014 | ||
1015 | /* | |
1016 | * The timer chip counts down to zero. Let's wait | |
1017 | * for a wraparound to start exact measurement: | |
1018 | * (the current tick might have been already half done) | |
1019 | */ | |
1020 | ||
1021 | wait_timer_tick(); | |
1022 | ||
1023 | /* | |
1024 | * We wrapped around just now. Let's start: | |
1025 | */ | |
1026 | if (cpu_has_tsc) | |
1027 | rdtscll(t1); | |
1028 | tt1 = apic_read(APIC_TMCCT); | |
1029 | ||
1030 | /* | |
1031 | * Let's wait LOOPS wraprounds: | |
1032 | */ | |
1033 | for (i = 0; i < LOOPS; i++) | |
1034 | wait_timer_tick(); | |
1035 | ||
1036 | tt2 = apic_read(APIC_TMCCT); | |
1037 | if (cpu_has_tsc) | |
1038 | rdtscll(t2); | |
1039 | ||
1040 | /* | |
1041 | * The APIC bus clock counter is 32 bits only, it | |
1042 | * might have overflown, but note that we use signed | |
1043 | * longs, thus no extra care needed. | |
1044 | * | |
1045 | * underflown to be exact, as the timer counts down ;) | |
1046 | */ | |
1047 | ||
1048 | result = (tt1-tt2)*APIC_DIVISOR/LOOPS; | |
1049 | ||
1050 | if (cpu_has_tsc) | |
1051 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " | |
1052 | "%ld.%04ld MHz.\n", | |
1053 | ((long)(t2-t1)/LOOPS)/(1000000/HZ), | |
1054 | ((long)(t2-t1)/LOOPS)%(1000000/HZ)); | |
1055 | ||
1056 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
1057 | "%ld.%04ld MHz.\n", | |
1058 | result/(1000000/HZ), | |
1059 | result%(1000000/HZ)); | |
1060 | ||
1061 | return result; | |
1062 | } | |
1063 | ||
1064 | static unsigned int calibration_result; | |
1065 | ||
1066 | void __init setup_boot_APIC_clock(void) | |
1067 | { | |
f2b36db6 | 1068 | unsigned long flags; |
1da177e4 LT |
1069 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"); |
1070 | using_apic_timer = 1; | |
1071 | ||
f2b36db6 | 1072 | local_irq_save(flags); |
1da177e4 LT |
1073 | |
1074 | calibration_result = calibrate_APIC_clock(); | |
1075 | /* | |
1076 | * Now set up the timer for real. | |
1077 | */ | |
1078 | setup_APIC_timer(calibration_result); | |
1079 | ||
f2b36db6 | 1080 | local_irq_restore(flags); |
1da177e4 LT |
1081 | } |
1082 | ||
0bb3184d | 1083 | void __devinit setup_secondary_APIC_clock(void) |
1da177e4 LT |
1084 | { |
1085 | setup_APIC_timer(calibration_result); | |
1086 | } | |
1087 | ||
6eb0a0fd | 1088 | void disable_APIC_timer(void) |
1da177e4 LT |
1089 | { |
1090 | if (using_apic_timer) { | |
1091 | unsigned long v; | |
1092 | ||
1093 | v = apic_read(APIC_LVTT); | |
1094 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | void enable_APIC_timer(void) | |
1099 | { | |
6eb0a0fd VP |
1100 | int cpu = smp_processor_id(); |
1101 | ||
1102 | if (using_apic_timer && | |
1103 | !cpu_isset(cpu, timer_bcast_ipi)) { | |
1da177e4 LT |
1104 | unsigned long v; |
1105 | ||
1106 | v = apic_read(APIC_LVTT); | |
1107 | apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED); | |
1108 | } | |
1109 | } | |
1110 | ||
6eb0a0fd VP |
1111 | void switch_APIC_timer_to_ipi(void *cpumask) |
1112 | { | |
1113 | cpumask_t mask = *(cpumask_t *)cpumask; | |
1114 | int cpu = smp_processor_id(); | |
1115 | ||
1116 | if (cpu_isset(cpu, mask) && | |
1117 | !cpu_isset(cpu, timer_bcast_ipi)) { | |
1118 | disable_APIC_timer(); | |
1119 | cpu_set(cpu, timer_bcast_ipi); | |
1120 | } | |
1121 | } | |
1122 | EXPORT_SYMBOL(switch_APIC_timer_to_ipi); | |
1123 | ||
1124 | void switch_ipi_to_APIC_timer(void *cpumask) | |
1125 | { | |
1126 | cpumask_t mask = *(cpumask_t *)cpumask; | |
1127 | int cpu = smp_processor_id(); | |
1128 | ||
1129 | if (cpu_isset(cpu, mask) && | |
1130 | cpu_isset(cpu, timer_bcast_ipi)) { | |
1131 | cpu_clear(cpu, timer_bcast_ipi); | |
1132 | enable_APIC_timer(); | |
1133 | } | |
1134 | } | |
1135 | EXPORT_SYMBOL(switch_ipi_to_APIC_timer); | |
1136 | ||
1da177e4 LT |
1137 | #undef APIC_DIVISOR |
1138 | ||
1139 | /* | |
1140 | * Local timer interrupt handler. It does both profiling and | |
1141 | * process statistics/rescheduling. | |
1142 | * | |
1143 | * We do profiling in every local tick, statistics/rescheduling | |
1144 | * happen only every 'profiling multiplier' ticks. The default | |
1145 | * multiplier is 1 and it can be changed by writing the new multiplier | |
1146 | * value into /proc/profile. | |
1147 | */ | |
1148 | ||
1149 | inline void smp_local_timer_interrupt(struct pt_regs * regs) | |
1150 | { | |
1da177e4 | 1151 | profile_tick(CPU_PROFILING, regs); |
1da177e4 | 1152 | #ifdef CONFIG_SMP |
5a07a30c | 1153 | update_process_times(user_mode_vm(regs)); |
1da177e4 | 1154 | #endif |
1da177e4 LT |
1155 | |
1156 | /* | |
1157 | * We take the 'long' return path, and there every subsystem | |
1158 | * grabs the apropriate locks (kernel lock/ irq lock). | |
1159 | * | |
1160 | * we might want to decouple profiling from the 'long path', | |
1161 | * and do the profiling totally in assembly. | |
1162 | * | |
1163 | * Currently this isn't too much of an issue (performance wise), | |
1164 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
1165 | */ | |
1166 | } | |
1167 | ||
1168 | /* | |
1169 | * Local APIC timer interrupt. This is the most natural way for doing | |
1170 | * local interrupts, but local timer interrupts can be emulated by | |
1171 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
1172 | * | |
1173 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
1174 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
1175 | */ | |
1176 | ||
1177 | fastcall void smp_apic_timer_interrupt(struct pt_regs *regs) | |
1178 | { | |
1179 | int cpu = smp_processor_id(); | |
1180 | ||
1181 | /* | |
1182 | * the NMI deadlock-detector uses this. | |
1183 | */ | |
1184 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
1185 | ||
1186 | /* | |
1187 | * NOTE! We'd better ACK the irq immediately, | |
1188 | * because timer handling can be slow. | |
1189 | */ | |
1190 | ack_APIC_irq(); | |
1191 | /* | |
1192 | * update_process_times() expects us to have done irq_enter(). | |
1193 | * Besides, if we don't timer interrupts ignore the global | |
1194 | * interrupt lock, which is the WrongThing (tm) to do. | |
1195 | */ | |
1196 | irq_enter(); | |
1197 | smp_local_timer_interrupt(regs); | |
1198 | irq_exit(); | |
1199 | } | |
1200 | ||
6eb0a0fd VP |
1201 | #ifndef CONFIG_SMP |
1202 | static void up_apic_timer_interrupt_call(struct pt_regs *regs) | |
1203 | { | |
1204 | int cpu = smp_processor_id(); | |
1205 | ||
1206 | /* | |
1207 | * the NMI deadlock-detector uses this. | |
1208 | */ | |
1209 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
1210 | ||
1211 | smp_local_timer_interrupt(regs); | |
1212 | } | |
1213 | #endif | |
1214 | ||
1215 | void smp_send_timer_broadcast_ipi(struct pt_regs *regs) | |
1216 | { | |
1217 | cpumask_t mask; | |
1218 | ||
1219 | cpus_and(mask, cpu_online_map, timer_bcast_ipi); | |
1220 | if (!cpus_empty(mask)) { | |
1221 | #ifdef CONFIG_SMP | |
1222 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
1223 | #else | |
1224 | /* | |
1225 | * We can directly call the apic timer interrupt handler | |
1226 | * in UP case. Minus all irq related functions | |
1227 | */ | |
1228 | up_apic_timer_interrupt_call(regs); | |
1229 | #endif | |
1230 | } | |
1231 | } | |
1232 | ||
5a07a30c VP |
1233 | int setup_profiling_timer(unsigned int multiplier) |
1234 | { | |
1235 | return -EINVAL; | |
1236 | } | |
1237 | ||
1da177e4 LT |
1238 | /* |
1239 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1240 | */ | |
1241 | fastcall void smp_spurious_interrupt(struct pt_regs *regs) | |
1242 | { | |
1243 | unsigned long v; | |
1244 | ||
1245 | irq_enter(); | |
1246 | /* | |
1247 | * Check if this really is a spurious interrupt and ACK it | |
1248 | * if it is a vectored one. Just in case... | |
1249 | * Spurious interrupts should not be ACKed. | |
1250 | */ | |
1251 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1252 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1253 | ack_APIC_irq(); | |
1254 | ||
1255 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
1256 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n", | |
1257 | smp_processor_id()); | |
1258 | irq_exit(); | |
1259 | } | |
1260 | ||
1261 | /* | |
1262 | * This interrupt should never happen with our APIC/SMP architecture | |
1263 | */ | |
1264 | ||
1265 | fastcall void smp_error_interrupt(struct pt_regs *regs) | |
1266 | { | |
1267 | unsigned long v, v1; | |
1268 | ||
1269 | irq_enter(); | |
1270 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1271 | v = apic_read(APIC_ESR); | |
1272 | apic_write(APIC_ESR, 0); | |
1273 | v1 = apic_read(APIC_ESR); | |
1274 | ack_APIC_irq(); | |
1275 | atomic_inc(&irq_err_count); | |
1276 | ||
1277 | /* Here is what the APIC error bits mean: | |
1278 | 0: Send CS error | |
1279 | 1: Receive CS error | |
1280 | 2: Send accept error | |
1281 | 3: Receive accept error | |
1282 | 4: Reserved | |
1283 | 5: Send illegal vector | |
1284 | 6: Received illegal vector | |
1285 | 7: Illegal register address | |
1286 | */ | |
1287 | printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", | |
1288 | smp_processor_id(), v , v1); | |
1289 | irq_exit(); | |
1290 | } | |
1291 | ||
1292 | /* | |
1e4c85f9 LT |
1293 | * This initializes the IO-APIC and APIC hardware if this is |
1294 | * a UP kernel. | |
1da177e4 | 1295 | */ |
1e4c85f9 | 1296 | int __init APIC_init_uniprocessor (void) |
1da177e4 | 1297 | { |
1e4c85f9 LT |
1298 | if (enable_local_apic < 0) |
1299 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1da177e4 | 1300 | |
1e4c85f9 | 1301 | if (!smp_found_config && !cpu_has_apic) |
1da177e4 LT |
1302 | return -1; |
1303 | ||
1304 | /* | |
1e4c85f9 | 1305 | * Complain if the BIOS pretends there is one. |
1da177e4 LT |
1306 | */ |
1307 | if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1308 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1309 | boot_cpu_physical_apicid); | |
3777a959 | 1310 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); |
1da177e4 LT |
1311 | return -1; |
1312 | } | |
1313 | ||
1314 | verify_local_APIC(); | |
1315 | ||
1316 | connect_bsp_APIC(); | |
1317 | ||
1e4c85f9 | 1318 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); |
1da177e4 | 1319 | |
1e4c85f9 | 1320 | setup_local_APIC(); |
1da177e4 | 1321 | |
1da177e4 | 1322 | #ifdef CONFIG_X86_IO_APIC |
1e4c85f9 LT |
1323 | if (smp_found_config) |
1324 | if (!skip_ioapic_setup && nr_ioapics) | |
1325 | setup_IO_APIC(); | |
1da177e4 LT |
1326 | #endif |
1327 | setup_boot_APIC_clock(); | |
1e4c85f9 LT |
1328 | |
1329 | return 0; | |
1da177e4 | 1330 | } |