Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <linux/mm.h> | |
21 | #include <linux/irq.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/smp_lock.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/mc146818rtc.h> | |
27 | #include <linux/kernel_stat.h> | |
28 | #include <linux/sysdev.h> | |
f3705136 | 29 | #include <linux/cpu.h> |
1da177e4 LT |
30 | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/mtrr.h> | |
34 | #include <asm/mpspec.h> | |
35 | #include <asm/desc.h> | |
36 | #include <asm/arch_hooks.h> | |
37 | #include <asm/hpet.h> | |
306e440d | 38 | #include <asm/i8253.h> |
1da177e4 LT |
39 | |
40 | #include <mach_apic.h> | |
41 | ||
42 | #include "io_ports.h" | |
43 | ||
9635b47d EB |
44 | /* |
45 | * Knob to control our willingness to enable the local APIC. | |
46 | */ | |
47 | int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */ | |
48 | ||
1da177e4 LT |
49 | /* |
50 | * Debug level | |
51 | */ | |
52 | int apic_verbosity; | |
53 | ||
54 | ||
55 | static void apic_pm_activate(void); | |
56 | ||
57 | /* | |
58 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
59 | * each architecture has to answer this themselves. | |
60 | */ | |
61 | void ack_bad_irq(unsigned int irq) | |
62 | { | |
63 | printk("unexpected IRQ trap at vector %02x\n", irq); | |
64 | /* | |
65 | * Currently unexpected vectors happen only on SMP and APIC. | |
66 | * We _must_ ack these because every local APIC has only N | |
67 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
68 | * holds up an irq slot - in excessive cases (when multiple | |
69 | * unexpected vectors occur) that might lock up the APIC | |
70 | * completely. | |
71 | */ | |
72 | ack_APIC_irq(); | |
73 | } | |
74 | ||
75 | void __init apic_intr_init(void) | |
76 | { | |
77 | #ifdef CONFIG_SMP | |
78 | smp_intr_init(); | |
79 | #endif | |
80 | /* self generated IPI for local APIC timer */ | |
81 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
82 | ||
83 | /* IPI vectors for APIC spurious and error interrupts */ | |
84 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
85 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
86 | ||
87 | /* thermal monitor LVT interrupt */ | |
88 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
89 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
90 | #endif | |
91 | } | |
92 | ||
93 | /* Using APIC to generate smp_local_timer_interrupt? */ | |
94 | int using_apic_timer = 0; | |
95 | ||
96 | static DEFINE_PER_CPU(int, prof_multiplier) = 1; | |
97 | static DEFINE_PER_CPU(int, prof_old_multiplier) = 1; | |
98 | static DEFINE_PER_CPU(int, prof_counter) = 1; | |
99 | ||
100 | static int enabled_via_apicbase; | |
101 | ||
102 | void enable_NMI_through_LVT0 (void * dummy) | |
103 | { | |
104 | unsigned int v, ver; | |
105 | ||
106 | ver = apic_read(APIC_LVR); | |
107 | ver = GET_APIC_VERSION(ver); | |
108 | v = APIC_DM_NMI; /* unmask and set to NMI */ | |
109 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
110 | v |= APIC_LVT_LEVEL_TRIGGER; | |
111 | apic_write_around(APIC_LVT0, v); | |
112 | } | |
113 | ||
114 | int get_physical_broadcast(void) | |
115 | { | |
116 | unsigned int lvr, version; | |
117 | lvr = apic_read(APIC_LVR); | |
118 | version = GET_APIC_VERSION(lvr); | |
119 | if (!APIC_INTEGRATED(version) || version >= 0x14) | |
120 | return 0xff; | |
121 | else | |
122 | return 0xf; | |
123 | } | |
124 | ||
125 | int get_maxlvt(void) | |
126 | { | |
127 | unsigned int v, ver, maxlvt; | |
128 | ||
129 | v = apic_read(APIC_LVR); | |
130 | ver = GET_APIC_VERSION(v); | |
131 | /* 82489DXs do not report # of LVT entries. */ | |
132 | maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2; | |
133 | return maxlvt; | |
134 | } | |
135 | ||
136 | void clear_local_APIC(void) | |
137 | { | |
138 | int maxlvt; | |
139 | unsigned long v; | |
140 | ||
141 | maxlvt = get_maxlvt(); | |
142 | ||
143 | /* | |
144 | * Masking an LVT entry on a P6 can trigger a local APIC error | |
145 | * if the vector is zero. Mask LVTERR first to prevent this. | |
146 | */ | |
147 | if (maxlvt >= 3) { | |
148 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
149 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
150 | } | |
151 | /* | |
152 | * Careful: we have to set masks only first to deassert | |
153 | * any level-triggered sources. | |
154 | */ | |
155 | v = apic_read(APIC_LVTT); | |
156 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
157 | v = apic_read(APIC_LVT0); | |
158 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
159 | v = apic_read(APIC_LVT1); | |
160 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
161 | if (maxlvt >= 4) { | |
162 | v = apic_read(APIC_LVTPC); | |
163 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
164 | } | |
165 | ||
166 | /* lets not touch this if we didn't frob it */ | |
167 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
168 | if (maxlvt >= 5) { | |
169 | v = apic_read(APIC_LVTTHMR); | |
170 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
171 | } | |
172 | #endif | |
173 | /* | |
174 | * Clean APIC state for other OSs: | |
175 | */ | |
176 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); | |
177 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
178 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
179 | if (maxlvt >= 3) | |
180 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
181 | if (maxlvt >= 4) | |
182 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
183 | ||
184 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
185 | if (maxlvt >= 5) | |
186 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
187 | #endif | |
188 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
189 | if (APIC_INTEGRATED(v)) { /* !82489DX */ | |
190 | if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */ | |
191 | apic_write(APIC_ESR, 0); | |
192 | apic_read(APIC_ESR); | |
193 | } | |
194 | } | |
195 | ||
196 | void __init connect_bsp_APIC(void) | |
197 | { | |
198 | if (pic_mode) { | |
199 | /* | |
200 | * Do not trust the local APIC being empty at bootup. | |
201 | */ | |
202 | clear_local_APIC(); | |
203 | /* | |
204 | * PIC mode, enable APIC mode in the IMCR, i.e. | |
205 | * connect BSP's local APIC to INT and NMI lines. | |
206 | */ | |
207 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
208 | "enabling APIC mode.\n"); | |
209 | outb(0x70, 0x22); | |
210 | outb(0x01, 0x23); | |
211 | } | |
212 | enable_apic_mode(); | |
213 | } | |
214 | ||
650927ef | 215 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 LT |
216 | { |
217 | if (pic_mode) { | |
218 | /* | |
219 | * Put the board back into PIC mode (has an effect | |
220 | * only on certain older boards). Note that APIC | |
221 | * interrupts, including IPIs, won't work beyond | |
222 | * this point! The only exception are INIT IPIs. | |
223 | */ | |
224 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
225 | "entering PIC mode.\n"); | |
226 | outb(0x70, 0x22); | |
227 | outb(0x00, 0x23); | |
228 | } | |
650927ef EB |
229 | else { |
230 | /* Go back to Virtual Wire compatibility mode */ | |
231 | unsigned long value; | |
232 | ||
233 | /* For the spurious interrupt use vector F, and enable it */ | |
234 | value = apic_read(APIC_SPIV); | |
235 | value &= ~APIC_VECTOR_MASK; | |
236 | value |= APIC_SPIV_APIC_ENABLED; | |
237 | value |= 0xf; | |
238 | apic_write_around(APIC_SPIV, value); | |
239 | ||
240 | if (!virt_wire_setup) { | |
241 | /* For LVT0 make it edge triggered, active high, external and enabled */ | |
242 | value = apic_read(APIC_LVT0); | |
243 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
244 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
245 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
246 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
247 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
248 | apic_write_around(APIC_LVT0, value); | |
249 | } | |
250 | else { | |
251 | /* Disable LVT0 */ | |
252 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
253 | } | |
254 | ||
255 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
256 | value = apic_read(APIC_LVT1); | |
257 | value &= ~( | |
258 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
259 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
260 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
261 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
262 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
263 | apic_write_around(APIC_LVT1, value); | |
264 | } | |
1da177e4 LT |
265 | } |
266 | ||
267 | void disable_local_APIC(void) | |
268 | { | |
269 | unsigned long value; | |
270 | ||
271 | clear_local_APIC(); | |
272 | ||
273 | /* | |
274 | * Disable APIC (implies clearing of registers | |
275 | * for 82489DX!). | |
276 | */ | |
277 | value = apic_read(APIC_SPIV); | |
278 | value &= ~APIC_SPIV_APIC_ENABLED; | |
279 | apic_write_around(APIC_SPIV, value); | |
280 | ||
281 | if (enabled_via_apicbase) { | |
282 | unsigned int l, h; | |
283 | rdmsr(MSR_IA32_APICBASE, l, h); | |
284 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
285 | wrmsr(MSR_IA32_APICBASE, l, h); | |
286 | } | |
287 | } | |
288 | ||
289 | /* | |
290 | * This is to verify that we're looking at a real local APIC. | |
291 | * Check these against your board if the CPUs aren't getting | |
292 | * started for no apparent reason. | |
293 | */ | |
294 | int __init verify_local_APIC(void) | |
295 | { | |
296 | unsigned int reg0, reg1; | |
297 | ||
298 | /* | |
299 | * The version register is read-only in a real APIC. | |
300 | */ | |
301 | reg0 = apic_read(APIC_LVR); | |
302 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
303 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
304 | reg1 = apic_read(APIC_LVR); | |
305 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
306 | ||
307 | /* | |
308 | * The two version reads above should print the same | |
309 | * numbers. If the second one is different, then we | |
310 | * poke at a non-APIC. | |
311 | */ | |
312 | if (reg1 != reg0) | |
313 | return 0; | |
314 | ||
315 | /* | |
316 | * Check if the version looks reasonably. | |
317 | */ | |
318 | reg1 = GET_APIC_VERSION(reg0); | |
319 | if (reg1 == 0x00 || reg1 == 0xff) | |
320 | return 0; | |
321 | reg1 = get_maxlvt(); | |
322 | if (reg1 < 0x02 || reg1 == 0xff) | |
323 | return 0; | |
324 | ||
325 | /* | |
326 | * The ID register is read/write in a real APIC. | |
327 | */ | |
328 | reg0 = apic_read(APIC_ID); | |
329 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
330 | ||
331 | /* | |
332 | * The next two are just to see if we have sane values. | |
333 | * They're only really relevant if we're in Virtual Wire | |
334 | * compatibility mode, but most boxes are anymore. | |
335 | */ | |
336 | reg0 = apic_read(APIC_LVT0); | |
337 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
338 | reg1 = apic_read(APIC_LVT1); | |
339 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
340 | ||
341 | return 1; | |
342 | } | |
343 | ||
344 | void __init sync_Arb_IDs(void) | |
345 | { | |
346 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
347 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
348 | if (ver >= 0x14) /* P4 or higher */ | |
349 | return; | |
350 | /* | |
351 | * Wait for idle. | |
352 | */ | |
353 | apic_wait_icr_idle(); | |
354 | ||
355 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
356 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
357 | | APIC_DM_INIT); | |
358 | } | |
359 | ||
360 | extern void __error_in_apic_c (void); | |
361 | ||
362 | /* | |
363 | * An initial setup of the virtual wire mode. | |
364 | */ | |
365 | void __init init_bsp_APIC(void) | |
366 | { | |
367 | unsigned long value, ver; | |
368 | ||
369 | /* | |
370 | * Don't do the setup now if we have a SMP BIOS as the | |
371 | * through-I/O-APIC virtual wire mode might be active. | |
372 | */ | |
373 | if (smp_found_config || !cpu_has_apic) | |
374 | return; | |
375 | ||
376 | value = apic_read(APIC_LVR); | |
377 | ver = GET_APIC_VERSION(value); | |
378 | ||
379 | /* | |
380 | * Do not trust the local APIC being empty at bootup. | |
381 | */ | |
382 | clear_local_APIC(); | |
383 | ||
384 | /* | |
385 | * Enable APIC. | |
386 | */ | |
387 | value = apic_read(APIC_SPIV); | |
388 | value &= ~APIC_VECTOR_MASK; | |
389 | value |= APIC_SPIV_APIC_ENABLED; | |
390 | ||
391 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
392 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15)) | |
393 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
394 | else | |
395 | value |= APIC_SPIV_FOCUS_DISABLED; | |
396 | value |= SPURIOUS_APIC_VECTOR; | |
397 | apic_write_around(APIC_SPIV, value); | |
398 | ||
399 | /* | |
400 | * Set up the virtual wire mode. | |
401 | */ | |
402 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
403 | value = APIC_DM_NMI; | |
404 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
405 | value |= APIC_LVT_LEVEL_TRIGGER; | |
406 | apic_write_around(APIC_LVT1, value); | |
407 | } | |
408 | ||
0bb3184d | 409 | void __devinit setup_local_APIC(void) |
1da177e4 LT |
410 | { |
411 | unsigned long oldvalue, value, ver, maxlvt; | |
412 | ||
413 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
414 | if (esr_disable) { | |
415 | apic_write(APIC_ESR, 0); | |
416 | apic_write(APIC_ESR, 0); | |
417 | apic_write(APIC_ESR, 0); | |
418 | apic_write(APIC_ESR, 0); | |
419 | } | |
420 | ||
421 | value = apic_read(APIC_LVR); | |
422 | ver = GET_APIC_VERSION(value); | |
423 | ||
424 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) | |
425 | __error_in_apic_c(); | |
426 | ||
427 | /* | |
428 | * Double-check whether this APIC is really registered. | |
429 | */ | |
430 | if (!apic_id_registered()) | |
431 | BUG(); | |
432 | ||
433 | /* | |
434 | * Intel recommends to set DFR, LDR and TPR before enabling | |
435 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
436 | * document number 292116). So here it goes... | |
437 | */ | |
438 | init_apic_ldr(); | |
439 | ||
440 | /* | |
441 | * Set Task Priority to 'accept all'. We never change this | |
442 | * later on. | |
443 | */ | |
444 | value = apic_read(APIC_TASKPRI); | |
445 | value &= ~APIC_TPRI_MASK; | |
446 | apic_write_around(APIC_TASKPRI, value); | |
447 | ||
448 | /* | |
449 | * Now that we are all set up, enable the APIC | |
450 | */ | |
451 | value = apic_read(APIC_SPIV); | |
452 | value &= ~APIC_VECTOR_MASK; | |
453 | /* | |
454 | * Enable APIC | |
455 | */ | |
456 | value |= APIC_SPIV_APIC_ENABLED; | |
457 | ||
458 | /* | |
459 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
460 | * certain networking cards. If high frequency interrupts are | |
461 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
462 | * entry is masked/unmasked at a high rate as well then sooner or | |
463 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
464 | * from the device. If focus CPU is disabled then the hang goes | |
465 | * away, oh well :-( | |
466 | * | |
467 | * [ This bug can be reproduced easily with a level-triggered | |
468 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
469 | * BX chipset. ] | |
470 | */ | |
471 | /* | |
472 | * Actually disabling the focus CPU check just makes the hang less | |
473 | * frequent as it makes the interrupt distributon model be more | |
474 | * like LRU than MRU (the short-term load is more even across CPUs). | |
475 | * See also the comment in end_level_ioapic_irq(). --macro | |
476 | */ | |
477 | #if 1 | |
478 | /* Enable focus processor (bit==0) */ | |
479 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
480 | #else | |
481 | /* Disable focus processor (bit==1) */ | |
482 | value |= APIC_SPIV_FOCUS_DISABLED; | |
483 | #endif | |
484 | /* | |
485 | * Set spurious IRQ vector | |
486 | */ | |
487 | value |= SPURIOUS_APIC_VECTOR; | |
488 | apic_write_around(APIC_SPIV, value); | |
489 | ||
490 | /* | |
491 | * Set up LVT0, LVT1: | |
492 | * | |
493 | * set up through-local-APIC on the BP's LINT0. This is not | |
494 | * strictly necessery in pure symmetric-IO mode, but sometimes | |
495 | * we delegate interrupts to the 8259A. | |
496 | */ | |
497 | /* | |
498 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
499 | */ | |
500 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
501 | if (!smp_processor_id() && (pic_mode || !value)) { | |
502 | value = APIC_DM_EXTINT; | |
503 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
504 | smp_processor_id()); | |
505 | } else { | |
506 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
507 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
508 | smp_processor_id()); | |
509 | } | |
510 | apic_write_around(APIC_LVT0, value); | |
511 | ||
512 | /* | |
513 | * only the BP should see the LINT1 NMI signal, obviously. | |
514 | */ | |
515 | if (!smp_processor_id()) | |
516 | value = APIC_DM_NMI; | |
517 | else | |
518 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
519 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
520 | value |= APIC_LVT_LEVEL_TRIGGER; | |
521 | apic_write_around(APIC_LVT1, value); | |
522 | ||
523 | if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */ | |
524 | maxlvt = get_maxlvt(); | |
525 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
526 | apic_write(APIC_ESR, 0); | |
527 | oldvalue = apic_read(APIC_ESR); | |
528 | ||
529 | value = ERROR_APIC_VECTOR; // enables sending errors | |
530 | apic_write_around(APIC_LVTERR, value); | |
531 | /* | |
532 | * spec says clear errors after enabling vector. | |
533 | */ | |
534 | if (maxlvt > 3) | |
535 | apic_write(APIC_ESR, 0); | |
536 | value = apic_read(APIC_ESR); | |
537 | if (value != oldvalue) | |
538 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
539 | "vector: 0x%08lx after: 0x%08lx\n", | |
540 | oldvalue, value); | |
541 | } else { | |
542 | if (esr_disable) | |
543 | /* | |
544 | * Something untraceble is creating bad interrupts on | |
545 | * secondary quads ... for the moment, just leave the | |
546 | * ESR disabled - we can't do anything useful with the | |
547 | * errors anyway - mbligh | |
548 | */ | |
549 | printk("Leaving ESR disabled.\n"); | |
550 | else | |
551 | printk("No ESR for 82489DX.\n"); | |
552 | } | |
553 | ||
554 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
555 | setup_apic_nmi_watchdog(); | |
556 | apic_pm_activate(); | |
557 | } | |
558 | ||
559 | /* | |
560 | * If Linux enabled the LAPIC against the BIOS default | |
561 | * disable it down before re-entering the BIOS on shutdown. | |
562 | * Otherwise the BIOS may get confused and not power-off. | |
563 | */ | |
564 | void lapic_shutdown(void) | |
565 | { | |
566 | if (!cpu_has_apic || !enabled_via_apicbase) | |
567 | return; | |
568 | ||
569 | local_irq_disable(); | |
570 | disable_local_APIC(); | |
571 | local_irq_enable(); | |
572 | } | |
573 | ||
574 | #ifdef CONFIG_PM | |
575 | ||
576 | static struct { | |
577 | int active; | |
578 | /* r/w apic fields */ | |
579 | unsigned int apic_id; | |
580 | unsigned int apic_taskpri; | |
581 | unsigned int apic_ldr; | |
582 | unsigned int apic_dfr; | |
583 | unsigned int apic_spiv; | |
584 | unsigned int apic_lvtt; | |
585 | unsigned int apic_lvtpc; | |
586 | unsigned int apic_lvt0; | |
587 | unsigned int apic_lvt1; | |
588 | unsigned int apic_lvterr; | |
589 | unsigned int apic_tmict; | |
590 | unsigned int apic_tdcr; | |
591 | unsigned int apic_thmr; | |
592 | } apic_pm_state; | |
593 | ||
438510f6 | 594 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
595 | { |
596 | unsigned long flags; | |
597 | ||
598 | if (!apic_pm_state.active) | |
599 | return 0; | |
600 | ||
601 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
602 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
603 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
604 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
605 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
606 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
607 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
608 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
609 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
610 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
611 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
612 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
613 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
614 | ||
615 | local_irq_save(flags); | |
616 | disable_local_APIC(); | |
617 | local_irq_restore(flags); | |
618 | return 0; | |
619 | } | |
620 | ||
621 | static int lapic_resume(struct sys_device *dev) | |
622 | { | |
623 | unsigned int l, h; | |
624 | unsigned long flags; | |
625 | ||
626 | if (!apic_pm_state.active) | |
627 | return 0; | |
628 | ||
629 | local_irq_save(flags); | |
630 | ||
631 | /* | |
632 | * Make sure the APICBASE points to the right address | |
633 | * | |
634 | * FIXME! This will be wrong if we ever support suspend on | |
635 | * SMP! We'll need to do this as part of the CPU restore! | |
636 | */ | |
637 | rdmsr(MSR_IA32_APICBASE, l, h); | |
638 | l &= ~MSR_IA32_APICBASE_BASE; | |
639 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
640 | wrmsr(MSR_IA32_APICBASE, l, h); | |
641 | ||
642 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
643 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
644 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
645 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
646 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
647 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
648 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
649 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
650 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
651 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
652 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
653 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
654 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
655 | apic_write(APIC_ESR, 0); | |
656 | apic_read(APIC_ESR); | |
657 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
658 | apic_write(APIC_ESR, 0); | |
659 | apic_read(APIC_ESR); | |
660 | local_irq_restore(flags); | |
661 | return 0; | |
662 | } | |
663 | ||
664 | /* | |
665 | * This device has no shutdown method - fully functioning local APICs | |
666 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
667 | */ | |
668 | ||
669 | static struct sysdev_class lapic_sysclass = { | |
670 | set_kset_name("lapic"), | |
671 | .resume = lapic_resume, | |
672 | .suspend = lapic_suspend, | |
673 | }; | |
674 | ||
675 | static struct sys_device device_lapic = { | |
676 | .id = 0, | |
677 | .cls = &lapic_sysclass, | |
678 | }; | |
679 | ||
0bb3184d | 680 | static void __devinit apic_pm_activate(void) |
1da177e4 LT |
681 | { |
682 | apic_pm_state.active = 1; | |
683 | } | |
684 | ||
685 | static int __init init_lapic_sysfs(void) | |
686 | { | |
687 | int error; | |
688 | ||
689 | if (!cpu_has_apic) | |
690 | return 0; | |
691 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
692 | ||
693 | error = sysdev_class_register(&lapic_sysclass); | |
694 | if (!error) | |
695 | error = sysdev_register(&device_lapic); | |
696 | return error; | |
697 | } | |
698 | device_initcall(init_lapic_sysfs); | |
699 | ||
700 | #else /* CONFIG_PM */ | |
701 | ||
702 | static void apic_pm_activate(void) { } | |
703 | ||
704 | #endif /* CONFIG_PM */ | |
705 | ||
706 | /* | |
707 | * Detect and enable local APICs on non-SMP boards. | |
708 | * Original code written by Keir Fraser. | |
709 | */ | |
710 | ||
1da177e4 LT |
711 | static int __init apic_set_verbosity(char *str) |
712 | { | |
713 | if (strcmp("debug", str) == 0) | |
714 | apic_verbosity = APIC_DEBUG; | |
715 | else if (strcmp("verbose", str) == 0) | |
716 | apic_verbosity = APIC_VERBOSE; | |
717 | else | |
718 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
719 | " use apic=verbose or apic=debug", str); | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
724 | __setup("apic=", apic_set_verbosity); | |
725 | ||
726 | static int __init detect_init_APIC (void) | |
727 | { | |
728 | u32 h, l, features; | |
1da177e4 LT |
729 | |
730 | /* Disabled by kernel option? */ | |
731 | if (enable_local_apic < 0) | |
732 | return -1; | |
733 | ||
1da177e4 LT |
734 | switch (boot_cpu_data.x86_vendor) { |
735 | case X86_VENDOR_AMD: | |
736 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
737 | (boot_cpu_data.x86 == 15)) | |
738 | break; | |
739 | goto no_apic; | |
740 | case X86_VENDOR_INTEL: | |
741 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
742 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
743 | break; | |
744 | goto no_apic; | |
745 | default: | |
746 | goto no_apic; | |
747 | } | |
748 | ||
749 | if (!cpu_has_apic) { | |
750 | /* | |
751 | * Over-ride BIOS and try to enable the local | |
752 | * APIC only if "lapic" specified. | |
753 | */ | |
754 | if (enable_local_apic <= 0) { | |
755 | printk("Local APIC disabled by BIOS -- " | |
756 | "you can enable it with \"lapic\"\n"); | |
757 | return -1; | |
758 | } | |
759 | /* | |
760 | * Some BIOSes disable the local APIC in the | |
761 | * APIC_BASE MSR. This can only be done in | |
762 | * software for Intel P6 or later and AMD K7 | |
763 | * (Model > 1) or later. | |
764 | */ | |
765 | rdmsr(MSR_IA32_APICBASE, l, h); | |
766 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
767 | printk("Local APIC disabled by BIOS -- reenabling.\n"); | |
768 | l &= ~MSR_IA32_APICBASE_BASE; | |
769 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
770 | wrmsr(MSR_IA32_APICBASE, l, h); | |
771 | enabled_via_apicbase = 1; | |
772 | } | |
773 | } | |
774 | /* | |
775 | * The APIC feature bit should now be enabled | |
776 | * in `cpuid' | |
777 | */ | |
778 | features = cpuid_edx(1); | |
779 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
780 | printk("Could not enable APIC!\n"); | |
781 | return -1; | |
782 | } | |
783 | set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
784 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
785 | ||
786 | /* The BIOS may have set up the APIC at some other address */ | |
787 | rdmsr(MSR_IA32_APICBASE, l, h); | |
788 | if (l & MSR_IA32_APICBASE_ENABLE) | |
789 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
790 | ||
791 | if (nmi_watchdog != NMI_NONE) | |
792 | nmi_watchdog = NMI_LOCAL_APIC; | |
793 | ||
794 | printk("Found and enabled local APIC!\n"); | |
795 | ||
796 | apic_pm_activate(); | |
797 | ||
798 | return 0; | |
799 | ||
800 | no_apic: | |
801 | printk("No local APIC present or hardware disabled\n"); | |
802 | return -1; | |
803 | } | |
804 | ||
805 | void __init init_apic_mappings(void) | |
806 | { | |
807 | unsigned long apic_phys; | |
808 | ||
809 | /* | |
810 | * If no local APIC can be found then set up a fake all | |
811 | * zeroes page to simulate the local APIC and another | |
812 | * one for the IO-APIC. | |
813 | */ | |
814 | if (!smp_found_config && detect_init_APIC()) { | |
815 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
816 | apic_phys = __pa(apic_phys); | |
817 | } else | |
818 | apic_phys = mp_lapic_addr; | |
819 | ||
820 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
821 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
822 | apic_phys); | |
823 | ||
824 | /* | |
825 | * Fetch the APIC ID of the BSP in case we have a | |
826 | * default configuration (or the MP table is broken). | |
827 | */ | |
828 | if (boot_cpu_physical_apicid == -1U) | |
829 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
830 | ||
831 | #ifdef CONFIG_X86_IO_APIC | |
832 | { | |
833 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
834 | int i; | |
835 | ||
836 | for (i = 0; i < nr_ioapics; i++) { | |
837 | if (smp_found_config) { | |
838 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
839 | if (!ioapic_phys) { | |
840 | printk(KERN_ERR | |
841 | "WARNING: bogus zero IO-APIC " | |
842 | "address found in MPTABLE, " | |
843 | "disabling IO/APIC support!\n"); | |
844 | smp_found_config = 0; | |
845 | skip_ioapic_setup = 1; | |
846 | goto fake_ioapic_page; | |
847 | } | |
848 | } else { | |
849 | fake_ioapic_page: | |
850 | ioapic_phys = (unsigned long) | |
851 | alloc_bootmem_pages(PAGE_SIZE); | |
852 | ioapic_phys = __pa(ioapic_phys); | |
853 | } | |
854 | set_fixmap_nocache(idx, ioapic_phys); | |
855 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
856 | __fix_to_virt(idx), ioapic_phys); | |
857 | idx++; | |
858 | } | |
859 | } | |
860 | #endif | |
861 | } | |
862 | ||
863 | /* | |
864 | * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts | |
865 | * per second. We assume that the caller has already set up the local | |
866 | * APIC. | |
867 | * | |
868 | * The APIC timer is not exactly sync with the external timer chip, it | |
869 | * closely follows bus clocks. | |
870 | */ | |
871 | ||
872 | /* | |
873 | * The timer chip is already set up at HZ interrupts per second here, | |
874 | * but we do not accept timer interrupts yet. We only allow the BP | |
875 | * to calibrate. | |
876 | */ | |
0bb3184d | 877 | static unsigned int __devinit get_8254_timer_count(void) |
1da177e4 | 878 | { |
1da177e4 LT |
879 | unsigned long flags; |
880 | ||
881 | unsigned int count; | |
882 | ||
883 | spin_lock_irqsave(&i8253_lock, flags); | |
884 | ||
885 | outb_p(0x00, PIT_MODE); | |
886 | count = inb_p(PIT_CH0); | |
887 | count |= inb_p(PIT_CH0) << 8; | |
888 | ||
889 | spin_unlock_irqrestore(&i8253_lock, flags); | |
890 | ||
891 | return count; | |
892 | } | |
893 | ||
894 | /* next tick in 8254 can be caught by catching timer wraparound */ | |
0bb3184d | 895 | static void __devinit wait_8254_wraparound(void) |
1da177e4 LT |
896 | { |
897 | unsigned int curr_count, prev_count; | |
898 | ||
899 | curr_count = get_8254_timer_count(); | |
900 | do { | |
901 | prev_count = curr_count; | |
902 | curr_count = get_8254_timer_count(); | |
903 | ||
904 | /* workaround for broken Mercury/Neptune */ | |
905 | if (prev_count >= curr_count + 0x100) | |
906 | curr_count = get_8254_timer_count(); | |
907 | ||
908 | } while (prev_count >= curr_count); | |
909 | } | |
910 | ||
911 | /* | |
912 | * Default initialization for 8254 timers. If we use other timers like HPET, | |
913 | * we override this later | |
914 | */ | |
0bb3184d | 915 | void (*wait_timer_tick)(void) __devinitdata = wait_8254_wraparound; |
1da177e4 LT |
916 | |
917 | /* | |
918 | * This function sets up the local APIC timer, with a timeout of | |
919 | * 'clocks' APIC bus clock. During calibration we actually call | |
920 | * this function twice on the boot CPU, once with a bogus timeout | |
921 | * value, second time for real. The other (noncalibrating) CPUs | |
922 | * call this function only once, with the real, calibrated value. | |
923 | * | |
924 | * We do reads before writes even if unnecessary, to get around the | |
925 | * P5 APIC double write bug. | |
926 | */ | |
927 | ||
928 | #define APIC_DIVISOR 16 | |
929 | ||
930 | static void __setup_APIC_LVTT(unsigned int clocks) | |
931 | { | |
932 | unsigned int lvtt_value, tmp_value, ver; | |
933 | ||
934 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
935 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; | |
936 | if (!APIC_INTEGRATED(ver)) | |
937 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
938 | apic_write_around(APIC_LVTT, lvtt_value); | |
939 | ||
940 | /* | |
941 | * Divide PICLK by 16 | |
942 | */ | |
943 | tmp_value = apic_read(APIC_TDCR); | |
944 | apic_write_around(APIC_TDCR, (tmp_value | |
945 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
946 | | APIC_TDR_DIV_16); | |
947 | ||
948 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
949 | } | |
950 | ||
0bb3184d | 951 | static void __devinit setup_APIC_timer(unsigned int clocks) |
1da177e4 LT |
952 | { |
953 | unsigned long flags; | |
954 | ||
955 | local_irq_save(flags); | |
956 | ||
957 | /* | |
958 | * Wait for IRQ0's slice: | |
959 | */ | |
960 | wait_timer_tick(); | |
961 | ||
962 | __setup_APIC_LVTT(clocks); | |
963 | ||
964 | local_irq_restore(flags); | |
965 | } | |
966 | ||
967 | /* | |
968 | * In this function we calibrate APIC bus clocks to the external | |
969 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
970 | * to calibrate, since some later bootup code depends on getting | |
971 | * the first irq? Ugh. | |
972 | * | |
973 | * We want to do the calibration only once since we | |
974 | * want to have local timer irqs syncron. CPUs connected | |
975 | * by the same APIC bus have the very same bus frequency. | |
976 | * And we want to have irqs off anyways, no accidental | |
977 | * APIC irq that way. | |
978 | */ | |
979 | ||
980 | static int __init calibrate_APIC_clock(void) | |
981 | { | |
982 | unsigned long long t1 = 0, t2 = 0; | |
983 | long tt1, tt2; | |
984 | long result; | |
985 | int i; | |
986 | const int LOOPS = HZ/10; | |
987 | ||
988 | apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n"); | |
989 | ||
990 | /* | |
991 | * Put whatever arbitrary (but long enough) timeout | |
992 | * value into the APIC clock, we just want to get the | |
993 | * counter running for calibration. | |
994 | */ | |
995 | __setup_APIC_LVTT(1000000000); | |
996 | ||
997 | /* | |
998 | * The timer chip counts down to zero. Let's wait | |
999 | * for a wraparound to start exact measurement: | |
1000 | * (the current tick might have been already half done) | |
1001 | */ | |
1002 | ||
1003 | wait_timer_tick(); | |
1004 | ||
1005 | /* | |
1006 | * We wrapped around just now. Let's start: | |
1007 | */ | |
1008 | if (cpu_has_tsc) | |
1009 | rdtscll(t1); | |
1010 | tt1 = apic_read(APIC_TMCCT); | |
1011 | ||
1012 | /* | |
1013 | * Let's wait LOOPS wraprounds: | |
1014 | */ | |
1015 | for (i = 0; i < LOOPS; i++) | |
1016 | wait_timer_tick(); | |
1017 | ||
1018 | tt2 = apic_read(APIC_TMCCT); | |
1019 | if (cpu_has_tsc) | |
1020 | rdtscll(t2); | |
1021 | ||
1022 | /* | |
1023 | * The APIC bus clock counter is 32 bits only, it | |
1024 | * might have overflown, but note that we use signed | |
1025 | * longs, thus no extra care needed. | |
1026 | * | |
1027 | * underflown to be exact, as the timer counts down ;) | |
1028 | */ | |
1029 | ||
1030 | result = (tt1-tt2)*APIC_DIVISOR/LOOPS; | |
1031 | ||
1032 | if (cpu_has_tsc) | |
1033 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " | |
1034 | "%ld.%04ld MHz.\n", | |
1035 | ((long)(t2-t1)/LOOPS)/(1000000/HZ), | |
1036 | ((long)(t2-t1)/LOOPS)%(1000000/HZ)); | |
1037 | ||
1038 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
1039 | "%ld.%04ld MHz.\n", | |
1040 | result/(1000000/HZ), | |
1041 | result%(1000000/HZ)); | |
1042 | ||
1043 | return result; | |
1044 | } | |
1045 | ||
1046 | static unsigned int calibration_result; | |
1047 | ||
1048 | void __init setup_boot_APIC_clock(void) | |
1049 | { | |
1050 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"); | |
1051 | using_apic_timer = 1; | |
1052 | ||
1053 | local_irq_disable(); | |
1054 | ||
1055 | calibration_result = calibrate_APIC_clock(); | |
1056 | /* | |
1057 | * Now set up the timer for real. | |
1058 | */ | |
1059 | setup_APIC_timer(calibration_result); | |
1060 | ||
1061 | local_irq_enable(); | |
1062 | } | |
1063 | ||
0bb3184d | 1064 | void __devinit setup_secondary_APIC_clock(void) |
1da177e4 LT |
1065 | { |
1066 | setup_APIC_timer(calibration_result); | |
1067 | } | |
1068 | ||
f3705136 | 1069 | void __devinit disable_APIC_timer(void) |
1da177e4 LT |
1070 | { |
1071 | if (using_apic_timer) { | |
1072 | unsigned long v; | |
1073 | ||
1074 | v = apic_read(APIC_LVTT); | |
1075 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | void enable_APIC_timer(void) | |
1080 | { | |
1081 | if (using_apic_timer) { | |
1082 | unsigned long v; | |
1083 | ||
1084 | v = apic_read(APIC_LVTT); | |
1085 | apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED); | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | /* | |
1090 | * the frequency of the profiling timer can be changed | |
1091 | * by writing a multiplier value into /proc/profile. | |
1092 | */ | |
1093 | int setup_profiling_timer(unsigned int multiplier) | |
1094 | { | |
1095 | int i; | |
1096 | ||
1097 | /* | |
1098 | * Sanity check. [at least 500 APIC cycles should be | |
1099 | * between APIC interrupts as a rule of thumb, to avoid | |
1100 | * irqs flooding us] | |
1101 | */ | |
1102 | if ( (!multiplier) || (calibration_result/multiplier < 500)) | |
1103 | return -EINVAL; | |
1104 | ||
1105 | /* | |
1106 | * Set the new multiplier for each CPU. CPUs don't start using the | |
1107 | * new values until the next timer interrupt in which they do process | |
1108 | * accounting. At that time they also adjust their APIC timers | |
1109 | * accordingly. | |
1110 | */ | |
1111 | for (i = 0; i < NR_CPUS; ++i) | |
1112 | per_cpu(prof_multiplier, i) = multiplier; | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | #undef APIC_DIVISOR | |
1118 | ||
1119 | /* | |
1120 | * Local timer interrupt handler. It does both profiling and | |
1121 | * process statistics/rescheduling. | |
1122 | * | |
1123 | * We do profiling in every local tick, statistics/rescheduling | |
1124 | * happen only every 'profiling multiplier' ticks. The default | |
1125 | * multiplier is 1 and it can be changed by writing the new multiplier | |
1126 | * value into /proc/profile. | |
1127 | */ | |
1128 | ||
1129 | inline void smp_local_timer_interrupt(struct pt_regs * regs) | |
1130 | { | |
1131 | int cpu = smp_processor_id(); | |
1132 | ||
1133 | profile_tick(CPU_PROFILING, regs); | |
1134 | if (--per_cpu(prof_counter, cpu) <= 0) { | |
1135 | /* | |
1136 | * The multiplier may have changed since the last time we got | |
1137 | * to this point as a result of the user writing to | |
1138 | * /proc/profile. In this case we need to adjust the APIC | |
1139 | * timer accordingly. | |
1140 | * | |
1141 | * Interrupts are already masked off at this point. | |
1142 | */ | |
1143 | per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu); | |
1144 | if (per_cpu(prof_counter, cpu) != | |
1145 | per_cpu(prof_old_multiplier, cpu)) { | |
1146 | __setup_APIC_LVTT( | |
1147 | calibration_result/ | |
1148 | per_cpu(prof_counter, cpu)); | |
1149 | per_cpu(prof_old_multiplier, cpu) = | |
1150 | per_cpu(prof_counter, cpu); | |
1151 | } | |
1152 | ||
1153 | #ifdef CONFIG_SMP | |
fa1e1bdf | 1154 | update_process_times(user_mode_vm(regs)); |
1da177e4 LT |
1155 | #endif |
1156 | } | |
1157 | ||
1158 | /* | |
1159 | * We take the 'long' return path, and there every subsystem | |
1160 | * grabs the apropriate locks (kernel lock/ irq lock). | |
1161 | * | |
1162 | * we might want to decouple profiling from the 'long path', | |
1163 | * and do the profiling totally in assembly. | |
1164 | * | |
1165 | * Currently this isn't too much of an issue (performance wise), | |
1166 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
1167 | */ | |
1168 | } | |
1169 | ||
1170 | /* | |
1171 | * Local APIC timer interrupt. This is the most natural way for doing | |
1172 | * local interrupts, but local timer interrupts can be emulated by | |
1173 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
1174 | * | |
1175 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
1176 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
1177 | */ | |
1178 | ||
1179 | fastcall void smp_apic_timer_interrupt(struct pt_regs *regs) | |
1180 | { | |
1181 | int cpu = smp_processor_id(); | |
1182 | ||
1183 | /* | |
1184 | * the NMI deadlock-detector uses this. | |
1185 | */ | |
1186 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
1187 | ||
1188 | /* | |
1189 | * NOTE! We'd better ACK the irq immediately, | |
1190 | * because timer handling can be slow. | |
1191 | */ | |
1192 | ack_APIC_irq(); | |
1193 | /* | |
1194 | * update_process_times() expects us to have done irq_enter(). | |
1195 | * Besides, if we don't timer interrupts ignore the global | |
1196 | * interrupt lock, which is the WrongThing (tm) to do. | |
1197 | */ | |
1198 | irq_enter(); | |
1199 | smp_local_timer_interrupt(regs); | |
1200 | irq_exit(); | |
1201 | } | |
1202 | ||
1203 | /* | |
1204 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1205 | */ | |
1206 | fastcall void smp_spurious_interrupt(struct pt_regs *regs) | |
1207 | { | |
1208 | unsigned long v; | |
1209 | ||
1210 | irq_enter(); | |
1211 | /* | |
1212 | * Check if this really is a spurious interrupt and ACK it | |
1213 | * if it is a vectored one. Just in case... | |
1214 | * Spurious interrupts should not be ACKed. | |
1215 | */ | |
1216 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1217 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1218 | ack_APIC_irq(); | |
1219 | ||
1220 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
1221 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n", | |
1222 | smp_processor_id()); | |
1223 | irq_exit(); | |
1224 | } | |
1225 | ||
1226 | /* | |
1227 | * This interrupt should never happen with our APIC/SMP architecture | |
1228 | */ | |
1229 | ||
1230 | fastcall void smp_error_interrupt(struct pt_regs *regs) | |
1231 | { | |
1232 | unsigned long v, v1; | |
1233 | ||
1234 | irq_enter(); | |
1235 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1236 | v = apic_read(APIC_ESR); | |
1237 | apic_write(APIC_ESR, 0); | |
1238 | v1 = apic_read(APIC_ESR); | |
1239 | ack_APIC_irq(); | |
1240 | atomic_inc(&irq_err_count); | |
1241 | ||
1242 | /* Here is what the APIC error bits mean: | |
1243 | 0: Send CS error | |
1244 | 1: Receive CS error | |
1245 | 2: Send accept error | |
1246 | 3: Receive accept error | |
1247 | 4: Reserved | |
1248 | 5: Send illegal vector | |
1249 | 6: Received illegal vector | |
1250 | 7: Illegal register address | |
1251 | */ | |
1252 | printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", | |
1253 | smp_processor_id(), v , v1); | |
1254 | irq_exit(); | |
1255 | } | |
1256 | ||
1257 | /* | |
1258 | * This initializes the IO-APIC and APIC hardware if this is | |
1259 | * a UP kernel. | |
1260 | */ | |
1261 | int __init APIC_init_uniprocessor (void) | |
1262 | { | |
1263 | if (enable_local_apic < 0) | |
1264 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1265 | ||
1266 | if (!smp_found_config && !cpu_has_apic) | |
1267 | return -1; | |
1268 | ||
1269 | /* | |
1270 | * Complain if the BIOS pretends there is one. | |
1271 | */ | |
1272 | if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1273 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1274 | boot_cpu_physical_apicid); | |
1275 | return -1; | |
1276 | } | |
1277 | ||
1278 | verify_local_APIC(); | |
1279 | ||
1280 | connect_bsp_APIC(); | |
1281 | ||
1282 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
1283 | ||
1284 | setup_local_APIC(); | |
1285 | ||
1da177e4 LT |
1286 | #ifdef CONFIG_X86_IO_APIC |
1287 | if (smp_found_config) | |
1288 | if (!skip_ioapic_setup && nr_ioapics) | |
1289 | setup_IO_APIC(); | |
1290 | #endif | |
1291 | setup_boot_APIC_clock(); | |
1292 | ||
1293 | return 0; | |
1294 | } |