Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/smp_lock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/mc146818rtc.h> | |
25 | #include <linux/kernel_stat.h> | |
26 | #include <linux/sysdev.h> | |
f3705136 | 27 | #include <linux/cpu.h> |
6eb0a0fd | 28 | #include <linux/module.h> |
1da177e4 LT |
29 | |
30 | #include <asm/atomic.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/mpspec.h> | |
34 | #include <asm/desc.h> | |
35 | #include <asm/arch_hooks.h> | |
36 | #include <asm/hpet.h> | |
306e440d | 37 | #include <asm/i8253.h> |
3e4ff115 | 38 | #include <asm/nmi.h> |
2ff2d3d7 | 39 | #include <asm/idle.h> |
1da177e4 LT |
40 | |
41 | #include <mach_apic.h> | |
382dbd07 | 42 | #include <mach_apicdef.h> |
6eb0a0fd | 43 | #include <mach_ipi.h> |
1da177e4 LT |
44 | |
45 | #include "io_ports.h" | |
46 | ||
e05d723f TG |
47 | /* |
48 | * Sanity check | |
49 | */ | |
50 | #if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F | |
51 | # error SPURIOUS_APIC_VECTOR definition error | |
52 | #endif | |
53 | ||
6eb0a0fd VP |
54 | /* |
55 | * cpu_mask that denotes the CPUs that needs timer interrupt coming in as | |
56 | * IPIs in place of local APIC timers | |
57 | */ | |
58 | static cpumask_t timer_bcast_ipi; | |
59 | ||
9635b47d EB |
60 | /* |
61 | * Knob to control our willingness to enable the local APIC. | |
e05d723f TG |
62 | * |
63 | * -1=force-disable, +1=force-enable | |
9635b47d | 64 | */ |
e05d723f | 65 | static int enable_local_apic __initdata = 0; |
9635b47d | 66 | |
1da177e4 | 67 | /* |
e05d723f | 68 | * Debug level, exported for io_apic.c |
1da177e4 LT |
69 | */ |
70 | int apic_verbosity; | |
71 | ||
1da177e4 LT |
72 | static void apic_pm_activate(void); |
73 | ||
e05d723f TG |
74 | |
75 | /* Using APIC to generate smp_local_timer_interrupt? */ | |
76 | int using_apic_timer __read_mostly = 0; | |
77 | ||
78 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ | |
79 | static int enabled_via_apicbase; | |
80 | ||
81 | /* | |
82 | * Get the LAPIC version | |
83 | */ | |
84 | static inline int lapic_get_version(void) | |
95d769aa | 85 | { |
e05d723f | 86 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
95d769aa AK |
87 | } |
88 | ||
1da177e4 | 89 | /* |
e05d723f | 90 | * Check, if the APIC is integrated or a seperate chip |
1da177e4 | 91 | */ |
e05d723f | 92 | static inline int lapic_is_integrated(void) |
1da177e4 | 93 | { |
e05d723f | 94 | return APIC_INTEGRATED(lapic_get_version()); |
1da177e4 LT |
95 | } |
96 | ||
e05d723f TG |
97 | /* |
98 | * Check, whether this is a modern or a first generation APIC | |
99 | */ | |
100 | static int modern_apic(void) | |
1da177e4 | 101 | { |
e05d723f TG |
102 | /* AMD systems use old APIC versions, so check the CPU */ |
103 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
104 | boot_cpu_data.x86 >= 0xf) | |
105 | return 1; | |
106 | return lapic_get_version() >= 0x14; | |
1da177e4 LT |
107 | } |
108 | ||
e05d723f TG |
109 | /** |
110 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
111 | */ | |
1da177e4 LT |
112 | void enable_NMI_through_LVT0 (void * dummy) |
113 | { | |
e05d723f | 114 | unsigned int v = APIC_DM_NMI; |
1da177e4 | 115 | |
e05d723f TG |
116 | /* Level triggered for 82489DX */ |
117 | if (!lapic_is_integrated()) | |
1da177e4 LT |
118 | v |= APIC_LVT_LEVEL_TRIGGER; |
119 | apic_write_around(APIC_LVT0, v); | |
120 | } | |
121 | ||
e05d723f TG |
122 | /** |
123 | * get_physical_broadcast - Get number of physical broadcast IDs | |
124 | */ | |
1da177e4 LT |
125 | int get_physical_broadcast(void) |
126 | { | |
e05d723f | 127 | return modern_apic() ? 0xff : 0xf; |
1da177e4 LT |
128 | } |
129 | ||
e05d723f TG |
130 | /** |
131 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
132 | */ | |
133 | int lapic_get_maxlvt(void) | |
1da177e4 | 134 | { |
e05d723f | 135 | unsigned int v = apic_read(APIC_LVR); |
1da177e4 | 136 | |
1da177e4 | 137 | /* 82489DXs do not report # of LVT entries. */ |
e05d723f | 138 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; |
1da177e4 LT |
139 | } |
140 | ||
e05d723f TG |
141 | /* |
142 | * Local APIC timer | |
143 | */ | |
144 | ||
145 | /* | |
146 | * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts | |
147 | * per second. We assume that the caller has already set up the local | |
148 | * APIC. | |
149 | * | |
150 | * The APIC timer is not exactly sync with the external timer chip, it | |
151 | * closely follows bus clocks. | |
152 | */ | |
153 | ||
154 | /* | |
155 | * The timer chip is already set up at HZ interrupts per second here, | |
156 | * but we do not accept timer interrupts yet. We only allow the BP | |
157 | * to calibrate. | |
158 | */ | |
159 | static unsigned int __devinit get_8254_timer_count(void) | |
1da177e4 | 160 | { |
e05d723f | 161 | unsigned long flags; |
1da177e4 | 162 | |
e05d723f | 163 | unsigned int count; |
1da177e4 | 164 | |
e05d723f | 165 | spin_lock_irqsave(&i8253_lock, flags); |
1da177e4 | 166 | |
e05d723f TG |
167 | outb_p(0x00, PIT_MODE); |
168 | count = inb_p(PIT_CH0); | |
169 | count |= inb_p(PIT_CH0) << 8; | |
1da177e4 | 170 | |
e05d723f | 171 | spin_unlock_irqrestore(&i8253_lock, flags); |
1da177e4 | 172 | |
e05d723f | 173 | return count; |
1da177e4 LT |
174 | } |
175 | ||
e05d723f TG |
176 | /* next tick in 8254 can be caught by catching timer wraparound */ |
177 | static void __devinit wait_8254_wraparound(void) | |
1da177e4 | 178 | { |
e05d723f | 179 | unsigned int curr_count, prev_count; |
650927ef | 180 | |
e05d723f TG |
181 | curr_count = get_8254_timer_count(); |
182 | do { | |
183 | prev_count = curr_count; | |
184 | curr_count = get_8254_timer_count(); | |
650927ef | 185 | |
e05d723f TG |
186 | /* workaround for broken Mercury/Neptune */ |
187 | if (prev_count >= curr_count + 0x100) | |
188 | curr_count = get_8254_timer_count(); | |
650927ef | 189 | |
e05d723f | 190 | } while (prev_count >= curr_count); |
1da177e4 LT |
191 | } |
192 | ||
e05d723f TG |
193 | /* |
194 | * Default initialization for 8254 timers. If we use other timers like HPET, | |
195 | * we override this later | |
196 | */ | |
197 | void (*wait_timer_tick)(void) __devinitdata = wait_8254_wraparound; | |
198 | ||
199 | /* | |
200 | * This function sets up the local APIC timer, with a timeout of | |
201 | * 'clocks' APIC bus clock. During calibration we actually call | |
202 | * this function twice on the boot CPU, once with a bogus timeout | |
203 | * value, second time for real. The other (noncalibrating) CPUs | |
204 | * call this function only once, with the real, calibrated value. | |
205 | * | |
206 | * We do reads before writes even if unnecessary, to get around the | |
207 | * P5 APIC double write bug. | |
208 | */ | |
209 | ||
210 | #define APIC_DIVISOR 16 | |
211 | ||
212 | static void __setup_APIC_LVTT(unsigned int clocks) | |
1da177e4 | 213 | { |
e05d723f TG |
214 | unsigned int lvtt_value, tmp_value; |
215 | int cpu = smp_processor_id(); | |
1da177e4 | 216 | |
e05d723f TG |
217 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; |
218 | if (!lapic_is_integrated()) | |
219 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
220 | ||
221 | if (cpu_isset(cpu, timer_bcast_ipi)) | |
222 | lvtt_value |= APIC_LVT_MASKED; | |
223 | ||
224 | apic_write_around(APIC_LVTT, lvtt_value); | |
1da177e4 LT |
225 | |
226 | /* | |
e05d723f | 227 | * Divide PICLK by 16 |
1da177e4 | 228 | */ |
e05d723f TG |
229 | tmp_value = apic_read(APIC_TDCR); |
230 | apic_write_around(APIC_TDCR, (tmp_value | |
231 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
232 | | APIC_TDR_DIV_16); | |
1da177e4 | 233 | |
e05d723f | 234 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); |
1da177e4 LT |
235 | } |
236 | ||
e05d723f | 237 | static void __devinit setup_APIC_timer(unsigned int clocks) |
1da177e4 | 238 | { |
e05d723f TG |
239 | unsigned long flags; |
240 | ||
241 | local_irq_save(flags); | |
1da177e4 LT |
242 | |
243 | /* | |
e05d723f | 244 | * Wait for IRQ0's slice: |
1da177e4 | 245 | */ |
e05d723f TG |
246 | wait_timer_tick(); |
247 | ||
248 | __setup_APIC_LVTT(clocks); | |
249 | ||
250 | local_irq_restore(flags); | |
251 | } | |
252 | ||
253 | /* | |
254 | * In this function we calibrate APIC bus clocks to the external | |
255 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
256 | * to calibrate, since some later bootup code depends on getting | |
257 | * the first irq? Ugh. | |
258 | * | |
259 | * We want to do the calibration only once since we | |
260 | * want to have local timer irqs syncron. CPUs connected | |
261 | * by the same APIC bus have the very same bus frequency. | |
262 | * And we want to have irqs off anyways, no accidental | |
263 | * APIC irq that way. | |
264 | */ | |
265 | ||
266 | static int __init calibrate_APIC_clock(void) | |
267 | { | |
268 | unsigned long long t1 = 0, t2 = 0; | |
269 | long tt1, tt2; | |
270 | long result; | |
271 | int i; | |
272 | const int LOOPS = HZ/10; | |
273 | ||
274 | apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n"); | |
1da177e4 LT |
275 | |
276 | /* | |
e05d723f TG |
277 | * Put whatever arbitrary (but long enough) timeout |
278 | * value into the APIC clock, we just want to get the | |
279 | * counter running for calibration. | |
1da177e4 | 280 | */ |
e05d723f | 281 | __setup_APIC_LVTT(1000000000); |
1da177e4 LT |
282 | |
283 | /* | |
e05d723f TG |
284 | * The timer chip counts down to zero. Let's wait |
285 | * for a wraparound to start exact measurement: | |
286 | * (the current tick might have been already half done) | |
1da177e4 | 287 | */ |
e05d723f TG |
288 | |
289 | wait_timer_tick(); | |
1da177e4 LT |
290 | |
291 | /* | |
e05d723f | 292 | * We wrapped around just now. Let's start: |
1da177e4 | 293 | */ |
e05d723f TG |
294 | if (cpu_has_tsc) |
295 | rdtscll(t1); | |
296 | tt1 = apic_read(APIC_TMCCT); | |
1da177e4 LT |
297 | |
298 | /* | |
e05d723f | 299 | * Let's wait LOOPS wraprounds: |
1da177e4 | 300 | */ |
e05d723f TG |
301 | for (i = 0; i < LOOPS; i++) |
302 | wait_timer_tick(); | |
1da177e4 | 303 | |
e05d723f TG |
304 | tt2 = apic_read(APIC_TMCCT); |
305 | if (cpu_has_tsc) | |
306 | rdtscll(t2); | |
1da177e4 | 307 | |
1da177e4 | 308 | /* |
e05d723f TG |
309 | * The APIC bus clock counter is 32 bits only, it |
310 | * might have overflown, but note that we use signed | |
311 | * longs, thus no extra care needed. | |
312 | * | |
313 | * underflown to be exact, as the timer counts down ;) | |
1da177e4 | 314 | */ |
1da177e4 | 315 | |
e05d723f TG |
316 | result = (tt1-tt2)*APIC_DIVISOR/LOOPS; |
317 | ||
318 | if (cpu_has_tsc) | |
319 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " | |
320 | "%ld.%04ld MHz.\n", | |
321 | ((long)(t2-t1)/LOOPS)/(1000000/HZ), | |
322 | ((long)(t2-t1)/LOOPS)%(1000000/HZ)); | |
323 | ||
324 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
325 | "%ld.%04ld MHz.\n", | |
326 | result/(1000000/HZ), | |
327 | result%(1000000/HZ)); | |
328 | ||
329 | return result; | |
1da177e4 LT |
330 | } |
331 | ||
e05d723f | 332 | static unsigned int calibration_result; |
1da177e4 | 333 | |
e05d723f | 334 | void __init setup_boot_APIC_clock(void) |
1da177e4 | 335 | { |
e05d723f TG |
336 | unsigned long flags; |
337 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"); | |
338 | using_apic_timer = 1; | |
339 | ||
340 | local_irq_save(flags); | |
1da177e4 | 341 | |
e05d723f | 342 | calibration_result = calibrate_APIC_clock(); |
1da177e4 | 343 | /* |
e05d723f | 344 | * Now set up the timer for real. |
1da177e4 | 345 | */ |
e05d723f TG |
346 | setup_APIC_timer(calibration_result); |
347 | ||
348 | local_irq_restore(flags); | |
349 | } | |
1da177e4 | 350 | |
e05d723f TG |
351 | void __devinit setup_secondary_APIC_clock(void) |
352 | { | |
353 | setup_APIC_timer(calibration_result); | |
354 | } | |
1da177e4 | 355 | |
e05d723f TG |
356 | void disable_APIC_timer(void) |
357 | { | |
358 | if (using_apic_timer) { | |
359 | unsigned long v; | |
1da177e4 | 360 | |
e05d723f TG |
361 | v = apic_read(APIC_LVTT); |
362 | /* | |
363 | * When an illegal vector value (0-15) is written to an LVT | |
364 | * entry and delivery mode is Fixed, the APIC may signal an | |
365 | * illegal vector error, with out regard to whether the mask | |
366 | * bit is set or whether an interrupt is actually seen on | |
367 | * input. | |
368 | * | |
369 | * Boot sequence might call this function when the LVTT has | |
370 | * '0' vector value. So make sure vector field is set to | |
371 | * valid value. | |
372 | */ | |
373 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
374 | apic_write_around(APIC_LVTT, v); | |
375 | } | |
376 | } | |
1da177e4 | 377 | |
e05d723f TG |
378 | void enable_APIC_timer(void) |
379 | { | |
380 | int cpu = smp_processor_id(); | |
381 | ||
382 | if (using_apic_timer && !cpu_isset(cpu, timer_bcast_ipi)) { | |
383 | unsigned long v; | |
384 | ||
385 | v = apic_read(APIC_LVTT); | |
386 | apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED); | |
387 | } | |
1da177e4 LT |
388 | } |
389 | ||
e05d723f | 390 | void switch_APIC_timer_to_ipi(void *cpumask) |
1da177e4 | 391 | { |
e05d723f TG |
392 | cpumask_t mask = *(cpumask_t *)cpumask; |
393 | int cpu = smp_processor_id(); | |
1da177e4 | 394 | |
e05d723f TG |
395 | if (cpu_isset(cpu, mask) && |
396 | !cpu_isset(cpu, timer_bcast_ipi)) { | |
397 | disable_APIC_timer(); | |
398 | cpu_set(cpu, timer_bcast_ipi); | |
1da177e4 | 399 | } |
e05d723f TG |
400 | } |
401 | EXPORT_SYMBOL(switch_APIC_timer_to_ipi); | |
402 | ||
403 | void switch_ipi_to_APIC_timer(void *cpumask) | |
404 | { | |
405 | cpumask_t mask = *(cpumask_t *)cpumask; | |
406 | int cpu = smp_processor_id(); | |
1da177e4 | 407 | |
e05d723f TG |
408 | if (cpu_isset(cpu, mask) && |
409 | cpu_isset(cpu, timer_bcast_ipi)) { | |
410 | cpu_clear(cpu, timer_bcast_ipi); | |
411 | enable_APIC_timer(); | |
412 | } | |
413 | } | |
414 | EXPORT_SYMBOL(switch_ipi_to_APIC_timer); | |
1da177e4 | 415 | |
e05d723f TG |
416 | /* |
417 | * Local timer interrupt handler. It does both profiling and | |
418 | * process statistics/rescheduling. | |
419 | */ | |
420 | inline void smp_local_timer_interrupt(void) | |
421 | { | |
422 | profile_tick(CPU_PROFILING); | |
423 | #ifdef CONFIG_SMP | |
424 | update_process_times(user_mode_vm(get_irq_regs())); | |
425 | #endif | |
1da177e4 LT |
426 | |
427 | /* | |
e05d723f TG |
428 | * We take the 'long' return path, and there every subsystem |
429 | * grabs the apropriate locks (kernel lock/ irq lock). | |
430 | * | |
431 | * we might want to decouple profiling from the 'long path', | |
432 | * and do the profiling totally in assembly. | |
433 | * | |
434 | * Currently this isn't too much of an issue (performance wise), | |
435 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
1da177e4 | 436 | */ |
e05d723f TG |
437 | } |
438 | ||
439 | /* | |
440 | * Local APIC timer interrupt. This is the most natural way for doing | |
441 | * local interrupts, but local timer interrupts can be emulated by | |
442 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
443 | * | |
444 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
445 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
446 | */ | |
447 | ||
448 | fastcall void smp_apic_timer_interrupt(struct pt_regs *regs) | |
449 | { | |
450 | struct pt_regs *old_regs = set_irq_regs(regs); | |
451 | int cpu = smp_processor_id(); | |
1da177e4 LT |
452 | |
453 | /* | |
e05d723f | 454 | * the NMI deadlock-detector uses this. |
1da177e4 | 455 | */ |
e05d723f | 456 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
1da177e4 LT |
457 | |
458 | /* | |
e05d723f TG |
459 | * NOTE! We'd better ACK the irq immediately, |
460 | * because timer handling can be slow. | |
1da177e4 | 461 | */ |
e05d723f | 462 | ack_APIC_irq(); |
1a75a3f0 | 463 | /* |
e05d723f TG |
464 | * update_process_times() expects us to have done irq_enter(). |
465 | * Besides, if we don't timer interrupts ignore the global | |
466 | * interrupt lock, which is the WrongThing (tm) to do. | |
1a75a3f0 | 467 | */ |
e05d723f TG |
468 | exit_idle(); |
469 | irq_enter(); | |
470 | smp_local_timer_interrupt(); | |
471 | irq_exit(); | |
472 | set_irq_regs(old_regs); | |
473 | } | |
1a75a3f0 | 474 | |
e05d723f TG |
475 | #ifndef CONFIG_SMP |
476 | static void up_apic_timer_interrupt_call(void) | |
477 | { | |
478 | int cpu = smp_processor_id(); | |
1da177e4 LT |
479 | |
480 | /* | |
e05d723f | 481 | * the NMI deadlock-detector uses this. |
1da177e4 | 482 | */ |
e05d723f TG |
483 | per_cpu(irq_stat, cpu).apic_timer_irqs++; |
484 | ||
485 | smp_local_timer_interrupt(); | |
486 | } | |
487 | #endif | |
488 | ||
489 | void smp_send_timer_broadcast_ipi(void) | |
490 | { | |
491 | cpumask_t mask; | |
492 | ||
493 | cpus_and(mask, cpu_online_map, timer_bcast_ipi); | |
494 | if (!cpus_empty(mask)) { | |
495 | #ifdef CONFIG_SMP | |
496 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
1da177e4 | 497 | #else |
e05d723f TG |
498 | /* |
499 | * We can directly call the apic timer interrupt handler | |
500 | * in UP case. Minus all irq related functions | |
501 | */ | |
502 | up_apic_timer_interrupt_call(); | |
1da177e4 | 503 | #endif |
e05d723f TG |
504 | } |
505 | } | |
506 | ||
507 | int setup_profiling_timer(unsigned int multiplier) | |
508 | { | |
509 | return -EINVAL; | |
510 | } | |
511 | ||
512 | /* | |
513 | * Local APIC start and shutdown | |
514 | */ | |
515 | ||
516 | /** | |
517 | * clear_local_APIC - shutdown the local APIC | |
518 | * | |
519 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
520 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
521 | * leftovers during boot. | |
522 | */ | |
523 | void clear_local_APIC(void) | |
524 | { | |
525 | int maxlvt = lapic_get_maxlvt(); | |
526 | unsigned long v; | |
1da177e4 LT |
527 | |
528 | /* | |
e05d723f TG |
529 | * Masking an LVT entry can trigger a local APIC error |
530 | * if the vector is zero. Mask LVTERR first to prevent this. | |
1da177e4 | 531 | */ |
e05d723f TG |
532 | if (maxlvt >= 3) { |
533 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
534 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
535 | } | |
1da177e4 | 536 | /* |
e05d723f TG |
537 | * Careful: we have to set masks only first to deassert |
538 | * any level-triggered sources. | |
1da177e4 | 539 | */ |
e05d723f TG |
540 | v = apic_read(APIC_LVTT); |
541 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
542 | v = apic_read(APIC_LVT0); | |
543 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
544 | v = apic_read(APIC_LVT1); | |
545 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
546 | if (maxlvt >= 4) { | |
547 | v = apic_read(APIC_LVTPC); | |
548 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
1da177e4 | 549 | } |
1da177e4 | 550 | |
e05d723f TG |
551 | /* lets not touch this if we didn't frob it */ |
552 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
553 | if (maxlvt >= 5) { | |
554 | v = apic_read(APIC_LVTTHMR); | |
555 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
556 | } | |
557 | #endif | |
1da177e4 | 558 | /* |
e05d723f | 559 | * Clean APIC state for other OSs: |
1da177e4 | 560 | */ |
e05d723f TG |
561 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); |
562 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
563 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
564 | if (maxlvt >= 3) | |
565 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
566 | if (maxlvt >= 4) | |
567 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
1da177e4 | 568 | |
e05d723f TG |
569 | #ifdef CONFIG_X86_MCE_P4THERMAL |
570 | if (maxlvt >= 5) | |
571 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
572 | #endif | |
573 | /* Integrated APIC (!82489DX) ? */ | |
574 | if (lapic_is_integrated()) { | |
1da177e4 | 575 | if (maxlvt > 3) |
e05d723f | 576 | /* Clear ESR due to Pentium errata 3AP and 11AP */ |
1da177e4 | 577 | apic_write(APIC_ESR, 0); |
e05d723f | 578 | apic_read(APIC_ESR); |
1da177e4 | 579 | } |
e05d723f | 580 | } |
1da177e4 | 581 | |
e05d723f TG |
582 | /** |
583 | * disable_local_APIC - clear and disable the local APIC | |
584 | */ | |
585 | void disable_local_APIC(void) | |
586 | { | |
587 | unsigned long value; | |
588 | ||
589 | clear_local_APIC(); | |
590 | ||
591 | /* | |
592 | * Disable APIC (implies clearing of registers | |
593 | * for 82489DX!). | |
594 | */ | |
595 | value = apic_read(APIC_SPIV); | |
596 | value &= ~APIC_SPIV_APIC_ENABLED; | |
597 | apic_write_around(APIC_SPIV, value); | |
598 | ||
599 | /* | |
600 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
601 | * restore the disabled state. | |
602 | */ | |
603 | if (enabled_via_apicbase) { | |
604 | unsigned int l, h; | |
605 | ||
606 | rdmsr(MSR_IA32_APICBASE, l, h); | |
607 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
608 | wrmsr(MSR_IA32_APICBASE, l, h); | |
609 | } | |
1da177e4 LT |
610 | } |
611 | ||
612 | /* | |
e05d723f TG |
613 | * If Linux enabled the LAPIC against the BIOS default disable it down before |
614 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
615 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
77f72b19 | 616 | * for the case where Linux didn't enable the LAPIC. |
1da177e4 LT |
617 | */ |
618 | void lapic_shutdown(void) | |
619 | { | |
67963132 MS |
620 | unsigned long flags; |
621 | ||
77f72b19 | 622 | if (!cpu_has_apic) |
1da177e4 LT |
623 | return; |
624 | ||
67963132 | 625 | local_irq_save(flags); |
77f72b19 ZM |
626 | clear_local_APIC(); |
627 | ||
628 | if (enabled_via_apicbase) | |
629 | disable_local_APIC(); | |
630 | ||
67963132 | 631 | local_irq_restore(flags); |
1da177e4 LT |
632 | } |
633 | ||
e05d723f TG |
634 | /* |
635 | * This is to verify that we're looking at a real local APIC. | |
636 | * Check these against your board if the CPUs aren't getting | |
637 | * started for no apparent reason. | |
638 | */ | |
639 | int __init verify_local_APIC(void) | |
1da177e4 | 640 | { |
e05d723f | 641 | unsigned int reg0, reg1; |
1da177e4 | 642 | |
e05d723f TG |
643 | /* |
644 | * The version register is read-only in a real APIC. | |
645 | */ | |
646 | reg0 = apic_read(APIC_LVR); | |
647 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
648 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
649 | reg1 = apic_read(APIC_LVR); | |
650 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
651 | ||
652 | /* | |
653 | * The two version reads above should print the same | |
654 | * numbers. If the second one is different, then we | |
655 | * poke at a non-APIC. | |
656 | */ | |
657 | if (reg1 != reg0) | |
1da177e4 LT |
658 | return 0; |
659 | ||
e05d723f TG |
660 | /* |
661 | * Check if the version looks reasonably. | |
662 | */ | |
663 | reg1 = GET_APIC_VERSION(reg0); | |
664 | if (reg1 == 0x00 || reg1 == 0xff) | |
665 | return 0; | |
666 | reg1 = lapic_get_maxlvt(); | |
667 | if (reg1 < 0x02 || reg1 == 0xff) | |
668 | return 0; | |
f990fff4 | 669 | |
e05d723f TG |
670 | /* |
671 | * The ID register is read/write in a real APIC. | |
672 | */ | |
673 | reg0 = apic_read(APIC_ID); | |
674 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
675 | ||
676 | /* | |
677 | * The next two are just to see if we have sane values. | |
678 | * They're only really relevant if we're in Virtual Wire | |
679 | * compatibility mode, but most boxes are anymore. | |
680 | */ | |
681 | reg0 = apic_read(APIC_LVT0); | |
682 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
683 | reg1 = apic_read(APIC_LVT1); | |
684 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
685 | ||
686 | return 1; | |
1da177e4 LT |
687 | } |
688 | ||
e05d723f TG |
689 | /** |
690 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
691 | */ | |
692 | void __init sync_Arb_IDs(void) | |
1da177e4 | 693 | { |
e05d723f TG |
694 | /* |
695 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
696 | * needed on AMD. | |
697 | */ | |
698 | if (modern_apic()) | |
699 | return; | |
700 | /* | |
701 | * Wait for idle. | |
702 | */ | |
703 | apic_wait_icr_idle(); | |
1da177e4 | 704 | |
e05d723f TG |
705 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); |
706 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
707 | | APIC_DM_INIT); | |
708 | } | |
1da177e4 | 709 | |
e05d723f TG |
710 | /* |
711 | * An initial setup of the virtual wire mode. | |
712 | */ | |
713 | void __init init_bsp_APIC(void) | |
714 | { | |
715 | unsigned long value; | |
f990fff4 | 716 | |
e05d723f TG |
717 | /* |
718 | * Don't do the setup now if we have a SMP BIOS as the | |
719 | * through-I/O-APIC virtual wire mode might be active. | |
720 | */ | |
721 | if (smp_found_config || !cpu_has_apic) | |
722 | return; | |
1da177e4 LT |
723 | |
724 | /* | |
e05d723f | 725 | * Do not trust the local APIC being empty at bootup. |
1da177e4 | 726 | */ |
e05d723f | 727 | clear_local_APIC(); |
1da177e4 | 728 | |
e05d723f TG |
729 | /* |
730 | * Enable APIC. | |
731 | */ | |
732 | value = apic_read(APIC_SPIV); | |
733 | value &= ~APIC_VECTOR_MASK; | |
734 | value |= APIC_SPIV_APIC_ENABLED; | |
735 | ||
736 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
737 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
738 | (boot_cpu_data.x86 == 15)) | |
739 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
740 | else | |
741 | value |= APIC_SPIV_FOCUS_DISABLED; | |
742 | value |= SPURIOUS_APIC_VECTOR; | |
743 | apic_write_around(APIC_SPIV, value); | |
744 | ||
745 | /* | |
746 | * Set up the virtual wire mode. | |
747 | */ | |
748 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
749 | value = APIC_DM_NMI; | |
750 | if (!lapic_is_integrated()) /* 82489DX */ | |
751 | value |= APIC_LVT_LEVEL_TRIGGER; | |
752 | apic_write_around(APIC_LVT1, value); | |
1da177e4 LT |
753 | } |
754 | ||
e05d723f TG |
755 | /** |
756 | * setup_local_APIC - setup the local APIC | |
1da177e4 | 757 | */ |
e05d723f TG |
758 | void __devinit setup_local_APIC(void) |
759 | { | |
760 | unsigned long oldvalue, value, maxlvt, integrated; | |
761 | int i, j; | |
1da177e4 | 762 | |
e05d723f TG |
763 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ |
764 | if (esr_disable) { | |
765 | apic_write(APIC_ESR, 0); | |
766 | apic_write(APIC_ESR, 0); | |
767 | apic_write(APIC_ESR, 0); | |
768 | apic_write(APIC_ESR, 0); | |
769 | } | |
1da177e4 | 770 | |
e05d723f | 771 | integrated = lapic_is_integrated(); |
1da177e4 | 772 | |
e05d723f TG |
773 | /* |
774 | * Double-check whether this APIC is really registered. | |
775 | */ | |
776 | if (!apic_id_registered()) | |
777 | BUG(); | |
1da177e4 | 778 | |
e05d723f TG |
779 | /* |
780 | * Intel recommends to set DFR, LDR and TPR before enabling | |
781 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
782 | * document number 292116). So here it goes... | |
783 | */ | |
784 | init_apic_ldr(); | |
1da177e4 | 785 | |
e05d723f TG |
786 | /* |
787 | * Set Task Priority to 'accept all'. We never change this | |
788 | * later on. | |
789 | */ | |
790 | value = apic_read(APIC_TASKPRI); | |
791 | value &= ~APIC_TPRI_MASK; | |
792 | apic_write_around(APIC_TASKPRI, value); | |
1da177e4 | 793 | |
e05d723f TG |
794 | /* |
795 | * After a crash, we no longer service the interrupts and a pending | |
796 | * interrupt from previous kernel might still have ISR bit set. | |
797 | * | |
798 | * Most probably by now CPU has serviced that pending interrupt and | |
799 | * it might not have done the ack_APIC_irq() because it thought, | |
800 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
801 | * does not clear the ISR bit and cpu thinks it has already serivced | |
802 | * the interrupt. Hence a vector might get locked. It was noticed | |
803 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
804 | */ | |
805 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
806 | value = apic_read(APIC_ISR + i*0x10); | |
807 | for (j = 31; j >= 0; j--) { | |
808 | if (value & (1<<j)) | |
809 | ack_APIC_irq(); | |
810 | } | |
811 | } | |
1da177e4 | 812 | |
e05d723f TG |
813 | /* |
814 | * Now that we are all set up, enable the APIC | |
815 | */ | |
816 | value = apic_read(APIC_SPIV); | |
817 | value &= ~APIC_VECTOR_MASK; | |
818 | /* | |
819 | * Enable APIC | |
820 | */ | |
821 | value |= APIC_SPIV_APIC_ENABLED; | |
1da177e4 | 822 | |
e05d723f TG |
823 | /* |
824 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
825 | * certain networking cards. If high frequency interrupts are | |
826 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
827 | * entry is masked/unmasked at a high rate as well then sooner or | |
828 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
829 | * from the device. If focus CPU is disabled then the hang goes | |
830 | * away, oh well :-( | |
831 | * | |
832 | * [ This bug can be reproduced easily with a level-triggered | |
833 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
834 | * BX chipset. ] | |
835 | */ | |
836 | /* | |
837 | * Actually disabling the focus CPU check just makes the hang less | |
838 | * frequent as it makes the interrupt distributon model be more | |
839 | * like LRU than MRU (the short-term load is more even across CPUs). | |
840 | * See also the comment in end_level_ioapic_irq(). --macro | |
841 | */ | |
1da177e4 | 842 | |
e05d723f TG |
843 | /* Enable focus processor (bit==0) */ |
844 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 845 | |
e05d723f TG |
846 | /* |
847 | * Set spurious IRQ vector | |
848 | */ | |
849 | value |= SPURIOUS_APIC_VECTOR; | |
850 | apic_write_around(APIC_SPIV, value); | |
851 | ||
852 | /* | |
853 | * Set up LVT0, LVT1: | |
854 | * | |
855 | * set up through-local-APIC on the BP's LINT0. This is not | |
856 | * strictly necessery in pure symmetric-IO mode, but sometimes | |
857 | * we delegate interrupts to the 8259A. | |
858 | */ | |
859 | /* | |
860 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
861 | */ | |
862 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
863 | if (!smp_processor_id() && (pic_mode || !value)) { | |
864 | value = APIC_DM_EXTINT; | |
865 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
866 | smp_processor_id()); | |
867 | } else { | |
868 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
869 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
870 | smp_processor_id()); | |
871 | } | |
872 | apic_write_around(APIC_LVT0, value); | |
873 | ||
874 | /* | |
875 | * only the BP should see the LINT1 NMI signal, obviously. | |
876 | */ | |
877 | if (!smp_processor_id()) | |
878 | value = APIC_DM_NMI; | |
879 | else | |
880 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
881 | if (!integrated) /* 82489DX */ | |
882 | value |= APIC_LVT_LEVEL_TRIGGER; | |
883 | apic_write_around(APIC_LVT1, value); | |
884 | ||
885 | if (integrated && !esr_disable) { /* !82489DX */ | |
886 | maxlvt = lapic_get_maxlvt(); | |
887 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
888 | apic_write(APIC_ESR, 0); | |
889 | oldvalue = apic_read(APIC_ESR); | |
890 | ||
891 | /* enables sending errors */ | |
892 | value = ERROR_APIC_VECTOR; | |
893 | apic_write_around(APIC_LVTERR, value); | |
894 | /* | |
895 | * spec says clear errors after enabling vector. | |
896 | */ | |
897 | if (maxlvt > 3) | |
898 | apic_write(APIC_ESR, 0); | |
899 | value = apic_read(APIC_ESR); | |
900 | if (value != oldvalue) | |
901 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
902 | "vector: 0x%08lx after: 0x%08lx\n", | |
903 | oldvalue, value); | |
904 | } else { | |
905 | if (esr_disable) | |
906 | /* | |
907 | * Something untraceble is creating bad interrupts on | |
908 | * secondary quads ... for the moment, just leave the | |
909 | * ESR disabled - we can't do anything useful with the | |
910 | * errors anyway - mbligh | |
911 | */ | |
912 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
913 | else | |
914 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
915 | } | |
1da177e4 | 916 | |
e05d723f TG |
917 | setup_apic_nmi_watchdog(NULL); |
918 | apic_pm_activate(); | |
1da177e4 LT |
919 | } |
920 | ||
e05d723f TG |
921 | /* |
922 | * Detect and initialize APIC | |
923 | */ | |
1da177e4 LT |
924 | static int __init detect_init_APIC (void) |
925 | { | |
926 | u32 h, l, features; | |
1da177e4 LT |
927 | |
928 | /* Disabled by kernel option? */ | |
929 | if (enable_local_apic < 0) | |
930 | return -1; | |
931 | ||
1da177e4 LT |
932 | switch (boot_cpu_data.x86_vendor) { |
933 | case X86_VENDOR_AMD: | |
934 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
e05d723f | 935 | (boot_cpu_data.x86 == 15)) |
1da177e4 LT |
936 | break; |
937 | goto no_apic; | |
938 | case X86_VENDOR_INTEL: | |
939 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
940 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
941 | break; | |
942 | goto no_apic; | |
943 | default: | |
944 | goto no_apic; | |
945 | } | |
946 | ||
947 | if (!cpu_has_apic) { | |
948 | /* | |
e05d723f TG |
949 | * Over-ride BIOS and try to enable the local APIC only if |
950 | * "lapic" specified. | |
1da177e4 LT |
951 | */ |
952 | if (enable_local_apic <= 0) { | |
e05d723f | 953 | printk(KERN_INFO "Local APIC disabled by BIOS -- " |
1da177e4 LT |
954 | "you can enable it with \"lapic\"\n"); |
955 | return -1; | |
956 | } | |
957 | /* | |
e05d723f TG |
958 | * Some BIOSes disable the local APIC in the APIC_BASE |
959 | * MSR. This can only be done in software for Intel P6 or later | |
960 | * and AMD K7 (Model > 1) or later. | |
1da177e4 LT |
961 | */ |
962 | rdmsr(MSR_IA32_APICBASE, l, h); | |
963 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
e05d723f TG |
964 | printk(KERN_INFO |
965 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1da177e4 LT |
966 | l &= ~MSR_IA32_APICBASE_BASE; |
967 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
968 | wrmsr(MSR_IA32_APICBASE, l, h); | |
969 | enabled_via_apicbase = 1; | |
970 | } | |
971 | } | |
972 | /* | |
973 | * The APIC feature bit should now be enabled | |
974 | * in `cpuid' | |
975 | */ | |
976 | features = cpuid_edx(1); | |
977 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
e05d723f | 978 | printk(KERN_WARNING "Could not enable APIC!\n"); |
1da177e4 LT |
979 | return -1; |
980 | } | |
981 | set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
982 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
983 | ||
984 | /* The BIOS may have set up the APIC at some other address */ | |
985 | rdmsr(MSR_IA32_APICBASE, l, h); | |
e05d723f TG |
986 | if (l & MSR_IA32_APICBASE_ENABLE) |
987 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1da177e4 | 988 | |
e05d723f TG |
989 | if (nmi_watchdog != NMI_NONE) |
990 | nmi_watchdog = NMI_LOCAL_APIC; | |
1da177e4 | 991 | |
e05d723f | 992 | printk(KERN_INFO "Found and enabled local APIC!\n"); |
1da177e4 | 993 | |
e05d723f | 994 | apic_pm_activate(); |
1da177e4 | 995 | |
e05d723f | 996 | return 0; |
1da177e4 | 997 | |
e05d723f TG |
998 | no_apic: |
999 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1000 | return -1; | |
1001 | } | |
1da177e4 | 1002 | |
e05d723f TG |
1003 | /** |
1004 | * init_apic_mappings - initialize APIC mappings | |
1005 | */ | |
1006 | void __init init_apic_mappings(void) | |
1da177e4 | 1007 | { |
e05d723f | 1008 | unsigned long apic_phys; |
1da177e4 | 1009 | |
1da177e4 | 1010 | /* |
e05d723f TG |
1011 | * If no local APIC can be found then set up a fake all |
1012 | * zeroes page to simulate the local APIC and another | |
1013 | * one for the IO-APIC. | |
1da177e4 | 1014 | */ |
e05d723f TG |
1015 | if (!smp_found_config && detect_init_APIC()) { |
1016 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1017 | apic_phys = __pa(apic_phys); | |
1018 | } else | |
1019 | apic_phys = mp_lapic_addr; | |
1da177e4 | 1020 | |
e05d723f TG |
1021 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); |
1022 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
1023 | apic_phys); | |
1da177e4 | 1024 | |
e05d723f TG |
1025 | /* |
1026 | * Fetch the APIC ID of the BSP in case we have a | |
1027 | * default configuration (or the MP table is broken). | |
1028 | */ | |
1029 | if (boot_cpu_physical_apicid == -1U) | |
1030 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 | 1031 | |
e05d723f TG |
1032 | #ifdef CONFIG_X86_IO_APIC |
1033 | { | |
1034 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
1035 | int i; | |
1da177e4 | 1036 | |
e05d723f TG |
1037 | for (i = 0; i < nr_ioapics; i++) { |
1038 | if (smp_found_config) { | |
1039 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
1040 | if (!ioapic_phys) { | |
1041 | printk(KERN_ERR | |
1042 | "WARNING: bogus zero IO-APIC " | |
1043 | "address found in MPTABLE, " | |
1044 | "disabling IO/APIC support!\n"); | |
1045 | smp_found_config = 0; | |
1046 | skip_ioapic_setup = 1; | |
1047 | goto fake_ioapic_page; | |
1048 | } | |
1049 | } else { | |
1050 | fake_ioapic_page: | |
1051 | ioapic_phys = (unsigned long) | |
1052 | alloc_bootmem_pages(PAGE_SIZE); | |
1053 | ioapic_phys = __pa(ioapic_phys); | |
1054 | } | |
1055 | set_fixmap_nocache(idx, ioapic_phys); | |
1056 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
1057 | __fix_to_virt(idx), ioapic_phys); | |
1058 | idx++; | |
1059 | } | |
1da177e4 | 1060 | } |
e05d723f | 1061 | #endif |
1da177e4 LT |
1062 | } |
1063 | ||
e05d723f TG |
1064 | /* |
1065 | * This initializes the IO-APIC and APIC hardware if this is | |
1066 | * a UP kernel. | |
1067 | */ | |
1068 | int __init APIC_init_uniprocessor (void) | |
1da177e4 | 1069 | { |
e05d723f TG |
1070 | if (enable_local_apic < 0) |
1071 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1da177e4 | 1072 | |
e05d723f TG |
1073 | if (!smp_found_config && !cpu_has_apic) |
1074 | return -1; | |
6eb0a0fd | 1075 | |
e05d723f TG |
1076 | /* |
1077 | * Complain if the BIOS pretends there is one. | |
1078 | */ | |
1079 | if (!cpu_has_apic && | |
1080 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1081 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1082 | boot_cpu_physical_apicid); | |
1083 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1084 | return -1; | |
6eb0a0fd | 1085 | } |
6eb0a0fd | 1086 | |
e05d723f | 1087 | verify_local_APIC(); |
6eb0a0fd | 1088 | |
e05d723f | 1089 | connect_bsp_APIC(); |
6eb0a0fd | 1090 | |
e05d723f TG |
1091 | /* |
1092 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1093 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1094 | * might be zero if read from MP tables. Get it from LAPIC. | |
1095 | */ | |
1096 | #ifdef CONFIG_CRASH_DUMP | |
1097 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1098 | #endif | |
1099 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); | |
1da177e4 | 1100 | |
e05d723f | 1101 | setup_local_APIC(); |
1da177e4 | 1102 | |
e05d723f TG |
1103 | #ifdef CONFIG_X86_IO_APIC |
1104 | if (smp_found_config) | |
1105 | if (!skip_ioapic_setup && nr_ioapics) | |
1106 | setup_IO_APIC(); | |
1da177e4 | 1107 | #endif |
e05d723f | 1108 | setup_boot_clock(); |
1da177e4 | 1109 | |
e05d723f | 1110 | return 0; |
1da177e4 LT |
1111 | } |
1112 | ||
1113 | /* | |
e05d723f | 1114 | * APIC command line parameters |
1da177e4 | 1115 | */ |
e05d723f | 1116 | static int __init parse_lapic(char *arg) |
6eb0a0fd | 1117 | { |
e05d723f TG |
1118 | enable_local_apic = 1; |
1119 | return 0; | |
6eb0a0fd | 1120 | } |
e05d723f | 1121 | early_param("lapic", parse_lapic); |
6eb0a0fd | 1122 | |
e05d723f | 1123 | static int __init parse_nolapic(char *arg) |
6eb0a0fd | 1124 | { |
e05d723f TG |
1125 | enable_local_apic = -1; |
1126 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1127 | return 0; | |
6eb0a0fd | 1128 | } |
e05d723f | 1129 | early_param("nolapic", parse_nolapic); |
6eb0a0fd | 1130 | |
e05d723f | 1131 | static int __init apic_set_verbosity(char *str) |
5a07a30c | 1132 | { |
e05d723f TG |
1133 | if (strcmp("debug", str) == 0) |
1134 | apic_verbosity = APIC_DEBUG; | |
1135 | else if (strcmp("verbose", str) == 0) | |
1136 | apic_verbosity = APIC_VERBOSE; | |
1137 | return 1; | |
5a07a30c VP |
1138 | } |
1139 | ||
e05d723f TG |
1140 | __setup("apic=", apic_set_verbosity); |
1141 | ||
1142 | ||
1143 | /* | |
1144 | * Local APIC interrupts | |
1145 | */ | |
1146 | ||
1da177e4 LT |
1147 | /* |
1148 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1149 | */ | |
1150 | fastcall void smp_spurious_interrupt(struct pt_regs *regs) | |
1151 | { | |
1152 | unsigned long v; | |
1153 | ||
2ff2d3d7 | 1154 | exit_idle(); |
1da177e4 LT |
1155 | irq_enter(); |
1156 | /* | |
1157 | * Check if this really is a spurious interrupt and ACK it | |
1158 | * if it is a vectored one. Just in case... | |
1159 | * Spurious interrupts should not be ACKed. | |
1160 | */ | |
1161 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1162 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1163 | ack_APIC_irq(); | |
1164 | ||
1165 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
e05d723f TG |
1166 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " |
1167 | "should never happen.\n", smp_processor_id()); | |
1da177e4 LT |
1168 | irq_exit(); |
1169 | } | |
1170 | ||
1171 | /* | |
1172 | * This interrupt should never happen with our APIC/SMP architecture | |
1173 | */ | |
1da177e4 LT |
1174 | fastcall void smp_error_interrupt(struct pt_regs *regs) |
1175 | { | |
1176 | unsigned long v, v1; | |
1177 | ||
2ff2d3d7 | 1178 | exit_idle(); |
1da177e4 LT |
1179 | irq_enter(); |
1180 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1181 | v = apic_read(APIC_ESR); | |
1182 | apic_write(APIC_ESR, 0); | |
1183 | v1 = apic_read(APIC_ESR); | |
1184 | ack_APIC_irq(); | |
1185 | atomic_inc(&irq_err_count); | |
1186 | ||
1187 | /* Here is what the APIC error bits mean: | |
1188 | 0: Send CS error | |
1189 | 1: Receive CS error | |
1190 | 2: Send accept error | |
1191 | 3: Receive accept error | |
1192 | 4: Reserved | |
1193 | 5: Send illegal vector | |
1194 | 6: Received illegal vector | |
1195 | 7: Illegal register address | |
1196 | */ | |
1197 | printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", | |
e05d723f | 1198 | smp_processor_id(), v , v1); |
1da177e4 LT |
1199 | irq_exit(); |
1200 | } | |
1201 | ||
1202 | /* | |
e05d723f | 1203 | * Initialize APIC interrupts |
1da177e4 | 1204 | */ |
e05d723f | 1205 | void __init apic_intr_init(void) |
1da177e4 | 1206 | { |
e05d723f TG |
1207 | #ifdef CONFIG_SMP |
1208 | smp_intr_init(); | |
1209 | #endif | |
1210 | /* self generated IPI for local APIC timer */ | |
1211 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
1da177e4 | 1212 | |
e05d723f TG |
1213 | /* IPI vectors for APIC spurious and error interrupts */ |
1214 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
1215 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
1da177e4 | 1216 | |
e05d723f TG |
1217 | /* thermal monitor LVT interrupt */ |
1218 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1219 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
1220 | #endif | |
1221 | } | |
1222 | ||
1223 | /** | |
1224 | * connect_bsp_APIC - attach the APIC to the interrupt system | |
1225 | */ | |
1226 | void __init connect_bsp_APIC(void) | |
1227 | { | |
1228 | if (pic_mode) { | |
1229 | /* | |
1230 | * Do not trust the local APIC being empty at bootup. | |
1231 | */ | |
1232 | clear_local_APIC(); | |
1233 | /* | |
1234 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1235 | * local APIC to INT and NMI lines. | |
1236 | */ | |
1237 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1238 | "enabling APIC mode.\n"); | |
1239 | outb(0x70, 0x22); | |
1240 | outb(0x01, 0x23); | |
1da177e4 | 1241 | } |
e05d723f TG |
1242 | enable_apic_mode(); |
1243 | } | |
1da177e4 | 1244 | |
e05d723f TG |
1245 | /** |
1246 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1247 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1248 | * | |
1249 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1250 | * APIC is disabled. | |
1251 | */ | |
1252 | void disconnect_bsp_APIC(int virt_wire_setup) | |
1253 | { | |
1254 | if (pic_mode) { | |
1255 | /* | |
1256 | * Put the board back into PIC mode (has an effect only on | |
1257 | * certain older boards). Note that APIC interrupts, including | |
1258 | * IPIs, won't work beyond this point! The only exception are | |
1259 | * INIT IPIs. | |
1260 | */ | |
1261 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1262 | "entering PIC mode.\n"); | |
1263 | outb(0x70, 0x22); | |
1264 | outb(0x00, 0x23); | |
1265 | } else { | |
1266 | /* Go back to Virtual Wire compatibility mode */ | |
1267 | unsigned long value; | |
1da177e4 | 1268 | |
e05d723f TG |
1269 | /* For the spurious interrupt use vector F, and enable it */ |
1270 | value = apic_read(APIC_SPIV); | |
1271 | value &= ~APIC_VECTOR_MASK; | |
1272 | value |= APIC_SPIV_APIC_ENABLED; | |
1273 | value |= 0xf; | |
1274 | apic_write_around(APIC_SPIV, value); | |
1da177e4 | 1275 | |
e05d723f TG |
1276 | if (!virt_wire_setup) { |
1277 | /* | |
1278 | * For LVT0 make it edge triggered, active high, | |
1279 | * external and enabled | |
1280 | */ | |
1281 | value = apic_read(APIC_LVT0); | |
1282 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1283 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1284 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
1285 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1286 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1287 | apic_write_around(APIC_LVT0, value); | |
1288 | } else { | |
1289 | /* Disable LVT0 */ | |
1290 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
1291 | } | |
1da177e4 | 1292 | |
e05d723f TG |
1293 | /* |
1294 | * For LVT1 make it edge triggered, active high, nmi and | |
1295 | * enabled | |
1296 | */ | |
1297 | value = apic_read(APIC_LVT1); | |
1298 | value &= ~( | |
1299 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
1300 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1301 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1302 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1303 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1304 | apic_write_around(APIC_LVT1, value); | |
1305 | } | |
1306 | } | |
1da177e4 | 1307 | |
e05d723f TG |
1308 | /* |
1309 | * Power management | |
1310 | */ | |
1311 | #ifdef CONFIG_PM | |
1312 | ||
1313 | static struct { | |
1314 | int active; | |
1315 | /* r/w apic fields */ | |
1316 | unsigned int apic_id; | |
1317 | unsigned int apic_taskpri; | |
1318 | unsigned int apic_ldr; | |
1319 | unsigned int apic_dfr; | |
1320 | unsigned int apic_spiv; | |
1321 | unsigned int apic_lvtt; | |
1322 | unsigned int apic_lvtpc; | |
1323 | unsigned int apic_lvt0; | |
1324 | unsigned int apic_lvt1; | |
1325 | unsigned int apic_lvterr; | |
1326 | unsigned int apic_tmict; | |
1327 | unsigned int apic_tdcr; | |
1328 | unsigned int apic_thmr; | |
1329 | } apic_pm_state; | |
1330 | ||
1331 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1332 | { | |
1333 | unsigned long flags; | |
1334 | int maxlvt; | |
1335 | ||
1336 | if (!apic_pm_state.active) | |
1337 | return 0; | |
1338 | ||
1339 | maxlvt = lapic_get_maxlvt(); | |
1340 | ||
1341 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
1342 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1343 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1344 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1345 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1346 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1347 | if (maxlvt >= 4) | |
1348 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1349 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1350 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1351 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1352 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1353 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1354 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1355 | if (maxlvt >= 5) | |
1356 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1da177e4 | 1357 | #endif |
1e4c85f9 | 1358 | |
e05d723f TG |
1359 | local_irq_save(flags); |
1360 | disable_local_APIC(); | |
1361 | local_irq_restore(flags); | |
1e4c85f9 | 1362 | return 0; |
1da177e4 | 1363 | } |
1a3f239d | 1364 | |
e05d723f | 1365 | static int lapic_resume(struct sys_device *dev) |
1a3f239d | 1366 | { |
e05d723f TG |
1367 | unsigned int l, h; |
1368 | unsigned long flags; | |
1369 | int maxlvt; | |
1370 | ||
1371 | if (!apic_pm_state.active) | |
1372 | return 0; | |
1373 | ||
1374 | maxlvt = lapic_get_maxlvt(); | |
1375 | ||
1376 | local_irq_save(flags); | |
1377 | ||
1378 | /* | |
1379 | * Make sure the APICBASE points to the right address | |
1380 | * | |
1381 | * FIXME! This will be wrong if we ever support suspend on | |
1382 | * SMP! We'll need to do this as part of the CPU restore! | |
1383 | */ | |
1384 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1385 | l &= ~MSR_IA32_APICBASE_BASE; | |
1386 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1387 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1388 | ||
1389 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1390 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1391 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1392 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1393 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1394 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1395 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1396 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1397 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
1398 | if (maxlvt >= 5) | |
1399 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1400 | #endif | |
1401 | if (maxlvt >= 4) | |
1402 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1403 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1404 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1405 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1406 | apic_write(APIC_ESR, 0); | |
1407 | apic_read(APIC_ESR); | |
1408 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1409 | apic_write(APIC_ESR, 0); | |
1410 | apic_read(APIC_ESR); | |
1411 | local_irq_restore(flags); | |
1a3f239d RR |
1412 | return 0; |
1413 | } | |
1a3f239d | 1414 | |
e05d723f TG |
1415 | /* |
1416 | * This device has no shutdown method - fully functioning local APICs | |
1417 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1418 | */ | |
1419 | ||
1420 | static struct sysdev_class lapic_sysclass = { | |
1421 | set_kset_name("lapic"), | |
1422 | .resume = lapic_resume, | |
1423 | .suspend = lapic_suspend, | |
1424 | }; | |
1425 | ||
1426 | static struct sys_device device_lapic = { | |
1427 | .id = 0, | |
1428 | .cls = &lapic_sysclass, | |
1429 | }; | |
1430 | ||
1431 | static void __devinit apic_pm_activate(void) | |
1a3f239d | 1432 | { |
e05d723f | 1433 | apic_pm_state.active = 1; |
1a3f239d | 1434 | } |
1a3f239d | 1435 | |
e05d723f TG |
1436 | static int __init init_lapic_sysfs(void) |
1437 | { | |
1438 | int error; | |
1439 | ||
1440 | if (!cpu_has_apic) | |
1441 | return 0; | |
1442 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1443 | ||
1444 | error = sysdev_class_register(&lapic_sysclass); | |
1445 | if (!error) | |
1446 | error = sysdev_register(&device_lapic); | |
1447 | return error; | |
1448 | } | |
1449 | device_initcall(init_lapic_sysfs); | |
1450 | ||
1451 | #else /* CONFIG_PM */ | |
1452 | ||
1453 | static void apic_pm_activate(void) { } | |
1454 | ||
1455 | #endif /* CONFIG_PM */ |