Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/init.h> | |
19 | ||
20 | #include <linux/mm.h> | |
1da177e4 LT |
21 | #include <linux/delay.h> |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/smp_lock.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/mc146818rtc.h> | |
26 | #include <linux/kernel_stat.h> | |
27 | #include <linux/sysdev.h> | |
f3705136 | 28 | #include <linux/cpu.h> |
1da177e4 LT |
29 | |
30 | #include <asm/atomic.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/mpspec.h> | |
34 | #include <asm/desc.h> | |
35 | #include <asm/arch_hooks.h> | |
36 | #include <asm/hpet.h> | |
306e440d | 37 | #include <asm/i8253.h> |
1da177e4 LT |
38 | |
39 | #include <mach_apic.h> | |
40 | ||
41 | #include "io_ports.h" | |
42 | ||
9635b47d EB |
43 | /* |
44 | * Knob to control our willingness to enable the local APIC. | |
45 | */ | |
46 | int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */ | |
47 | ||
1da177e4 LT |
48 | /* |
49 | * Debug level | |
50 | */ | |
51 | int apic_verbosity; | |
52 | ||
53 | ||
54 | static void apic_pm_activate(void); | |
55 | ||
56 | /* | |
57 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
58 | * each architecture has to answer this themselves. | |
59 | */ | |
60 | void ack_bad_irq(unsigned int irq) | |
61 | { | |
62 | printk("unexpected IRQ trap at vector %02x\n", irq); | |
63 | /* | |
64 | * Currently unexpected vectors happen only on SMP and APIC. | |
65 | * We _must_ ack these because every local APIC has only N | |
66 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
67 | * holds up an irq slot - in excessive cases (when multiple | |
68 | * unexpected vectors occur) that might lock up the APIC | |
69 | * completely. | |
70 | */ | |
71 | ack_APIC_irq(); | |
72 | } | |
73 | ||
74 | void __init apic_intr_init(void) | |
75 | { | |
76 | #ifdef CONFIG_SMP | |
77 | smp_intr_init(); | |
78 | #endif | |
79 | /* self generated IPI for local APIC timer */ | |
80 | set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | |
81 | ||
82 | /* IPI vectors for APIC spurious and error interrupts */ | |
83 | set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | |
84 | set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | |
85 | ||
86 | /* thermal monitor LVT interrupt */ | |
87 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
88 | set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); | |
89 | #endif | |
90 | } | |
91 | ||
92 | /* Using APIC to generate smp_local_timer_interrupt? */ | |
93 | int using_apic_timer = 0; | |
94 | ||
95 | static DEFINE_PER_CPU(int, prof_multiplier) = 1; | |
96 | static DEFINE_PER_CPU(int, prof_old_multiplier) = 1; | |
97 | static DEFINE_PER_CPU(int, prof_counter) = 1; | |
98 | ||
99 | static int enabled_via_apicbase; | |
100 | ||
101 | void enable_NMI_through_LVT0 (void * dummy) | |
102 | { | |
103 | unsigned int v, ver; | |
104 | ||
105 | ver = apic_read(APIC_LVR); | |
106 | ver = GET_APIC_VERSION(ver); | |
107 | v = APIC_DM_NMI; /* unmask and set to NMI */ | |
108 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
109 | v |= APIC_LVT_LEVEL_TRIGGER; | |
110 | apic_write_around(APIC_LVT0, v); | |
111 | } | |
112 | ||
113 | int get_physical_broadcast(void) | |
114 | { | |
115 | unsigned int lvr, version; | |
116 | lvr = apic_read(APIC_LVR); | |
117 | version = GET_APIC_VERSION(lvr); | |
118 | if (!APIC_INTEGRATED(version) || version >= 0x14) | |
119 | return 0xff; | |
120 | else | |
121 | return 0xf; | |
122 | } | |
123 | ||
124 | int get_maxlvt(void) | |
125 | { | |
126 | unsigned int v, ver, maxlvt; | |
127 | ||
128 | v = apic_read(APIC_LVR); | |
129 | ver = GET_APIC_VERSION(v); | |
130 | /* 82489DXs do not report # of LVT entries. */ | |
131 | maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2; | |
132 | return maxlvt; | |
133 | } | |
134 | ||
135 | void clear_local_APIC(void) | |
136 | { | |
137 | int maxlvt; | |
138 | unsigned long v; | |
139 | ||
140 | maxlvt = get_maxlvt(); | |
141 | ||
142 | /* | |
143 | * Masking an LVT entry on a P6 can trigger a local APIC error | |
144 | * if the vector is zero. Mask LVTERR first to prevent this. | |
145 | */ | |
146 | if (maxlvt >= 3) { | |
147 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
148 | apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); | |
149 | } | |
150 | /* | |
151 | * Careful: we have to set masks only first to deassert | |
152 | * any level-triggered sources. | |
153 | */ | |
154 | v = apic_read(APIC_LVTT); | |
155 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
156 | v = apic_read(APIC_LVT0); | |
157 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
158 | v = apic_read(APIC_LVT1); | |
159 | apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); | |
160 | if (maxlvt >= 4) { | |
161 | v = apic_read(APIC_LVTPC); | |
162 | apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); | |
163 | } | |
164 | ||
165 | /* lets not touch this if we didn't frob it */ | |
166 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
167 | if (maxlvt >= 5) { | |
168 | v = apic_read(APIC_LVTTHMR); | |
169 | apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
170 | } | |
171 | #endif | |
172 | /* | |
173 | * Clean APIC state for other OSs: | |
174 | */ | |
175 | apic_write_around(APIC_LVTT, APIC_LVT_MASKED); | |
176 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
177 | apic_write_around(APIC_LVT1, APIC_LVT_MASKED); | |
178 | if (maxlvt >= 3) | |
179 | apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); | |
180 | if (maxlvt >= 4) | |
181 | apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); | |
182 | ||
183 | #ifdef CONFIG_X86_MCE_P4THERMAL | |
184 | if (maxlvt >= 5) | |
185 | apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED); | |
186 | #endif | |
187 | v = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
188 | if (APIC_INTEGRATED(v)) { /* !82489DX */ | |
189 | if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */ | |
190 | apic_write(APIC_ESR, 0); | |
191 | apic_read(APIC_ESR); | |
192 | } | |
193 | } | |
194 | ||
195 | void __init connect_bsp_APIC(void) | |
196 | { | |
197 | if (pic_mode) { | |
198 | /* | |
199 | * Do not trust the local APIC being empty at bootup. | |
200 | */ | |
201 | clear_local_APIC(); | |
202 | /* | |
203 | * PIC mode, enable APIC mode in the IMCR, i.e. | |
204 | * connect BSP's local APIC to INT and NMI lines. | |
205 | */ | |
206 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
207 | "enabling APIC mode.\n"); | |
208 | outb(0x70, 0x22); | |
209 | outb(0x01, 0x23); | |
210 | } | |
211 | enable_apic_mode(); | |
212 | } | |
213 | ||
650927ef | 214 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 LT |
215 | { |
216 | if (pic_mode) { | |
217 | /* | |
218 | * Put the board back into PIC mode (has an effect | |
219 | * only on certain older boards). Note that APIC | |
220 | * interrupts, including IPIs, won't work beyond | |
221 | * this point! The only exception are INIT IPIs. | |
222 | */ | |
223 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
224 | "entering PIC mode.\n"); | |
225 | outb(0x70, 0x22); | |
226 | outb(0x00, 0x23); | |
227 | } | |
650927ef EB |
228 | else { |
229 | /* Go back to Virtual Wire compatibility mode */ | |
230 | unsigned long value; | |
231 | ||
232 | /* For the spurious interrupt use vector F, and enable it */ | |
233 | value = apic_read(APIC_SPIV); | |
234 | value &= ~APIC_VECTOR_MASK; | |
235 | value |= APIC_SPIV_APIC_ENABLED; | |
236 | value |= 0xf; | |
237 | apic_write_around(APIC_SPIV, value); | |
238 | ||
239 | if (!virt_wire_setup) { | |
240 | /* For LVT0 make it edge triggered, active high, external and enabled */ | |
241 | value = apic_read(APIC_LVT0); | |
242 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
243 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
244 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); | |
245 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
246 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
247 | apic_write_around(APIC_LVT0, value); | |
248 | } | |
249 | else { | |
250 | /* Disable LVT0 */ | |
251 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED); | |
252 | } | |
253 | ||
254 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
255 | value = apic_read(APIC_LVT1); | |
256 | value &= ~( | |
257 | APIC_MODE_MASK | APIC_SEND_PENDING | | |
258 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
259 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
260 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
261 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
262 | apic_write_around(APIC_LVT1, value); | |
263 | } | |
1da177e4 LT |
264 | } |
265 | ||
266 | void disable_local_APIC(void) | |
267 | { | |
268 | unsigned long value; | |
269 | ||
270 | clear_local_APIC(); | |
271 | ||
272 | /* | |
273 | * Disable APIC (implies clearing of registers | |
274 | * for 82489DX!). | |
275 | */ | |
276 | value = apic_read(APIC_SPIV); | |
277 | value &= ~APIC_SPIV_APIC_ENABLED; | |
278 | apic_write_around(APIC_SPIV, value); | |
279 | ||
280 | if (enabled_via_apicbase) { | |
281 | unsigned int l, h; | |
282 | rdmsr(MSR_IA32_APICBASE, l, h); | |
283 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
284 | wrmsr(MSR_IA32_APICBASE, l, h); | |
285 | } | |
286 | } | |
287 | ||
288 | /* | |
289 | * This is to verify that we're looking at a real local APIC. | |
290 | * Check these against your board if the CPUs aren't getting | |
291 | * started for no apparent reason. | |
292 | */ | |
293 | int __init verify_local_APIC(void) | |
294 | { | |
295 | unsigned int reg0, reg1; | |
296 | ||
297 | /* | |
298 | * The version register is read-only in a real APIC. | |
299 | */ | |
300 | reg0 = apic_read(APIC_LVR); | |
301 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
302 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
303 | reg1 = apic_read(APIC_LVR); | |
304 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
305 | ||
306 | /* | |
307 | * The two version reads above should print the same | |
308 | * numbers. If the second one is different, then we | |
309 | * poke at a non-APIC. | |
310 | */ | |
311 | if (reg1 != reg0) | |
312 | return 0; | |
313 | ||
314 | /* | |
315 | * Check if the version looks reasonably. | |
316 | */ | |
317 | reg1 = GET_APIC_VERSION(reg0); | |
318 | if (reg1 == 0x00 || reg1 == 0xff) | |
319 | return 0; | |
320 | reg1 = get_maxlvt(); | |
321 | if (reg1 < 0x02 || reg1 == 0xff) | |
322 | return 0; | |
323 | ||
324 | /* | |
325 | * The ID register is read/write in a real APIC. | |
326 | */ | |
327 | reg0 = apic_read(APIC_ID); | |
328 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
329 | ||
330 | /* | |
331 | * The next two are just to see if we have sane values. | |
332 | * They're only really relevant if we're in Virtual Wire | |
333 | * compatibility mode, but most boxes are anymore. | |
334 | */ | |
335 | reg0 = apic_read(APIC_LVT0); | |
336 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); | |
337 | reg1 = apic_read(APIC_LVT1); | |
338 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
339 | ||
340 | return 1; | |
341 | } | |
342 | ||
343 | void __init sync_Arb_IDs(void) | |
344 | { | |
345 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
346 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
347 | if (ver >= 0x14) /* P4 or higher */ | |
348 | return; | |
349 | /* | |
350 | * Wait for idle. | |
351 | */ | |
352 | apic_wait_icr_idle(); | |
353 | ||
354 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
355 | apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | |
356 | | APIC_DM_INIT); | |
357 | } | |
358 | ||
359 | extern void __error_in_apic_c (void); | |
360 | ||
361 | /* | |
362 | * An initial setup of the virtual wire mode. | |
363 | */ | |
364 | void __init init_bsp_APIC(void) | |
365 | { | |
366 | unsigned long value, ver; | |
367 | ||
368 | /* | |
369 | * Don't do the setup now if we have a SMP BIOS as the | |
370 | * through-I/O-APIC virtual wire mode might be active. | |
371 | */ | |
372 | if (smp_found_config || !cpu_has_apic) | |
373 | return; | |
374 | ||
375 | value = apic_read(APIC_LVR); | |
376 | ver = GET_APIC_VERSION(value); | |
377 | ||
378 | /* | |
379 | * Do not trust the local APIC being empty at bootup. | |
380 | */ | |
381 | clear_local_APIC(); | |
382 | ||
383 | /* | |
384 | * Enable APIC. | |
385 | */ | |
386 | value = apic_read(APIC_SPIV); | |
387 | value &= ~APIC_VECTOR_MASK; | |
388 | value |= APIC_SPIV_APIC_ENABLED; | |
389 | ||
390 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
391 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15)) | |
392 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
393 | else | |
394 | value |= APIC_SPIV_FOCUS_DISABLED; | |
395 | value |= SPURIOUS_APIC_VECTOR; | |
396 | apic_write_around(APIC_SPIV, value); | |
397 | ||
398 | /* | |
399 | * Set up the virtual wire mode. | |
400 | */ | |
401 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
402 | value = APIC_DM_NMI; | |
403 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
404 | value |= APIC_LVT_LEVEL_TRIGGER; | |
405 | apic_write_around(APIC_LVT1, value); | |
406 | } | |
407 | ||
0bb3184d | 408 | void __devinit setup_local_APIC(void) |
1da177e4 LT |
409 | { |
410 | unsigned long oldvalue, value, ver, maxlvt; | |
411 | ||
412 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
413 | if (esr_disable) { | |
414 | apic_write(APIC_ESR, 0); | |
415 | apic_write(APIC_ESR, 0); | |
416 | apic_write(APIC_ESR, 0); | |
417 | apic_write(APIC_ESR, 0); | |
418 | } | |
419 | ||
420 | value = apic_read(APIC_LVR); | |
421 | ver = GET_APIC_VERSION(value); | |
422 | ||
423 | if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) | |
424 | __error_in_apic_c(); | |
425 | ||
426 | /* | |
427 | * Double-check whether this APIC is really registered. | |
428 | */ | |
429 | if (!apic_id_registered()) | |
430 | BUG(); | |
431 | ||
432 | /* | |
433 | * Intel recommends to set DFR, LDR and TPR before enabling | |
434 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
435 | * document number 292116). So here it goes... | |
436 | */ | |
437 | init_apic_ldr(); | |
438 | ||
439 | /* | |
440 | * Set Task Priority to 'accept all'. We never change this | |
441 | * later on. | |
442 | */ | |
443 | value = apic_read(APIC_TASKPRI); | |
444 | value &= ~APIC_TPRI_MASK; | |
445 | apic_write_around(APIC_TASKPRI, value); | |
446 | ||
447 | /* | |
448 | * Now that we are all set up, enable the APIC | |
449 | */ | |
450 | value = apic_read(APIC_SPIV); | |
451 | value &= ~APIC_VECTOR_MASK; | |
452 | /* | |
453 | * Enable APIC | |
454 | */ | |
455 | value |= APIC_SPIV_APIC_ENABLED; | |
456 | ||
457 | /* | |
458 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
459 | * certain networking cards. If high frequency interrupts are | |
460 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
461 | * entry is masked/unmasked at a high rate as well then sooner or | |
462 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
463 | * from the device. If focus CPU is disabled then the hang goes | |
464 | * away, oh well :-( | |
465 | * | |
466 | * [ This bug can be reproduced easily with a level-triggered | |
467 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
468 | * BX chipset. ] | |
469 | */ | |
470 | /* | |
471 | * Actually disabling the focus CPU check just makes the hang less | |
472 | * frequent as it makes the interrupt distributon model be more | |
473 | * like LRU than MRU (the short-term load is more even across CPUs). | |
474 | * See also the comment in end_level_ioapic_irq(). --macro | |
475 | */ | |
476 | #if 1 | |
477 | /* Enable focus processor (bit==0) */ | |
478 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
479 | #else | |
480 | /* Disable focus processor (bit==1) */ | |
481 | value |= APIC_SPIV_FOCUS_DISABLED; | |
482 | #endif | |
483 | /* | |
484 | * Set spurious IRQ vector | |
485 | */ | |
486 | value |= SPURIOUS_APIC_VECTOR; | |
487 | apic_write_around(APIC_SPIV, value); | |
488 | ||
489 | /* | |
490 | * Set up LVT0, LVT1: | |
491 | * | |
492 | * set up through-local-APIC on the BP's LINT0. This is not | |
493 | * strictly necessery in pure symmetric-IO mode, but sometimes | |
494 | * we delegate interrupts to the 8259A. | |
495 | */ | |
496 | /* | |
497 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
498 | */ | |
499 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
500 | if (!smp_processor_id() && (pic_mode || !value)) { | |
501 | value = APIC_DM_EXTINT; | |
502 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", | |
503 | smp_processor_id()); | |
504 | } else { | |
505 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
506 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", | |
507 | smp_processor_id()); | |
508 | } | |
509 | apic_write_around(APIC_LVT0, value); | |
510 | ||
511 | /* | |
512 | * only the BP should see the LINT1 NMI signal, obviously. | |
513 | */ | |
514 | if (!smp_processor_id()) | |
515 | value = APIC_DM_NMI; | |
516 | else | |
517 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
518 | if (!APIC_INTEGRATED(ver)) /* 82489DX */ | |
519 | value |= APIC_LVT_LEVEL_TRIGGER; | |
520 | apic_write_around(APIC_LVT1, value); | |
521 | ||
522 | if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */ | |
523 | maxlvt = get_maxlvt(); | |
524 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
525 | apic_write(APIC_ESR, 0); | |
526 | oldvalue = apic_read(APIC_ESR); | |
527 | ||
528 | value = ERROR_APIC_VECTOR; // enables sending errors | |
529 | apic_write_around(APIC_LVTERR, value); | |
530 | /* | |
531 | * spec says clear errors after enabling vector. | |
532 | */ | |
533 | if (maxlvt > 3) | |
534 | apic_write(APIC_ESR, 0); | |
535 | value = apic_read(APIC_ESR); | |
536 | if (value != oldvalue) | |
537 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
538 | "vector: 0x%08lx after: 0x%08lx\n", | |
539 | oldvalue, value); | |
540 | } else { | |
541 | if (esr_disable) | |
542 | /* | |
543 | * Something untraceble is creating bad interrupts on | |
544 | * secondary quads ... for the moment, just leave the | |
545 | * ESR disabled - we can't do anything useful with the | |
546 | * errors anyway - mbligh | |
547 | */ | |
548 | printk("Leaving ESR disabled.\n"); | |
549 | else | |
550 | printk("No ESR for 82489DX.\n"); | |
551 | } | |
552 | ||
553 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
554 | setup_apic_nmi_watchdog(); | |
555 | apic_pm_activate(); | |
556 | } | |
557 | ||
558 | /* | |
559 | * If Linux enabled the LAPIC against the BIOS default | |
560 | * disable it down before re-entering the BIOS on shutdown. | |
561 | * Otherwise the BIOS may get confused and not power-off. | |
77f72b19 ZM |
562 | * Additionally clear all LVT entries before disable_local_APIC |
563 | * for the case where Linux didn't enable the LAPIC. | |
1da177e4 LT |
564 | */ |
565 | void lapic_shutdown(void) | |
566 | { | |
77f72b19 | 567 | if (!cpu_has_apic) |
1da177e4 LT |
568 | return; |
569 | ||
570 | local_irq_disable(); | |
77f72b19 ZM |
571 | clear_local_APIC(); |
572 | ||
573 | if (enabled_via_apicbase) | |
574 | disable_local_APIC(); | |
575 | ||
1da177e4 LT |
576 | local_irq_enable(); |
577 | } | |
578 | ||
579 | #ifdef CONFIG_PM | |
580 | ||
581 | static struct { | |
582 | int active; | |
583 | /* r/w apic fields */ | |
584 | unsigned int apic_id; | |
585 | unsigned int apic_taskpri; | |
586 | unsigned int apic_ldr; | |
587 | unsigned int apic_dfr; | |
588 | unsigned int apic_spiv; | |
589 | unsigned int apic_lvtt; | |
590 | unsigned int apic_lvtpc; | |
591 | unsigned int apic_lvt0; | |
592 | unsigned int apic_lvt1; | |
593 | unsigned int apic_lvterr; | |
594 | unsigned int apic_tmict; | |
595 | unsigned int apic_tdcr; | |
596 | unsigned int apic_thmr; | |
597 | } apic_pm_state; | |
598 | ||
438510f6 | 599 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
600 | { |
601 | unsigned long flags; | |
602 | ||
603 | if (!apic_pm_state.active) | |
604 | return 0; | |
605 | ||
606 | apic_pm_state.apic_id = apic_read(APIC_ID); | |
607 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
608 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
609 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
610 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
611 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
612 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
613 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
614 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
615 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
616 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
617 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
618 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
619 | ||
620 | local_irq_save(flags); | |
621 | disable_local_APIC(); | |
622 | local_irq_restore(flags); | |
623 | return 0; | |
624 | } | |
625 | ||
626 | static int lapic_resume(struct sys_device *dev) | |
627 | { | |
628 | unsigned int l, h; | |
629 | unsigned long flags; | |
630 | ||
631 | if (!apic_pm_state.active) | |
632 | return 0; | |
633 | ||
634 | local_irq_save(flags); | |
635 | ||
636 | /* | |
637 | * Make sure the APICBASE points to the right address | |
638 | * | |
639 | * FIXME! This will be wrong if we ever support suspend on | |
640 | * SMP! We'll need to do this as part of the CPU restore! | |
641 | */ | |
642 | rdmsr(MSR_IA32_APICBASE, l, h); | |
643 | l &= ~MSR_IA32_APICBASE_BASE; | |
644 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
645 | wrmsr(MSR_IA32_APICBASE, l, h); | |
646 | ||
647 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
648 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
649 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
650 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
651 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
652 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
653 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
654 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
655 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
656 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
657 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
658 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
659 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
660 | apic_write(APIC_ESR, 0); | |
661 | apic_read(APIC_ESR); | |
662 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
663 | apic_write(APIC_ESR, 0); | |
664 | apic_read(APIC_ESR); | |
665 | local_irq_restore(flags); | |
666 | return 0; | |
667 | } | |
668 | ||
669 | /* | |
670 | * This device has no shutdown method - fully functioning local APICs | |
671 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
672 | */ | |
673 | ||
674 | static struct sysdev_class lapic_sysclass = { | |
675 | set_kset_name("lapic"), | |
676 | .resume = lapic_resume, | |
677 | .suspend = lapic_suspend, | |
678 | }; | |
679 | ||
680 | static struct sys_device device_lapic = { | |
681 | .id = 0, | |
682 | .cls = &lapic_sysclass, | |
683 | }; | |
684 | ||
0bb3184d | 685 | static void __devinit apic_pm_activate(void) |
1da177e4 LT |
686 | { |
687 | apic_pm_state.active = 1; | |
688 | } | |
689 | ||
690 | static int __init init_lapic_sysfs(void) | |
691 | { | |
692 | int error; | |
693 | ||
694 | if (!cpu_has_apic) | |
695 | return 0; | |
696 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
697 | ||
698 | error = sysdev_class_register(&lapic_sysclass); | |
699 | if (!error) | |
700 | error = sysdev_register(&device_lapic); | |
701 | return error; | |
702 | } | |
703 | device_initcall(init_lapic_sysfs); | |
704 | ||
705 | #else /* CONFIG_PM */ | |
706 | ||
707 | static void apic_pm_activate(void) { } | |
708 | ||
709 | #endif /* CONFIG_PM */ | |
710 | ||
711 | /* | |
712 | * Detect and enable local APICs on non-SMP boards. | |
713 | * Original code written by Keir Fraser. | |
714 | */ | |
715 | ||
1da177e4 LT |
716 | static int __init apic_set_verbosity(char *str) |
717 | { | |
718 | if (strcmp("debug", str) == 0) | |
719 | apic_verbosity = APIC_DEBUG; | |
720 | else if (strcmp("verbose", str) == 0) | |
721 | apic_verbosity = APIC_VERBOSE; | |
722 | else | |
723 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
e31b88ba | 724 | " use apic=verbose or apic=debug\n", str); |
1da177e4 LT |
725 | |
726 | return 0; | |
727 | } | |
728 | ||
729 | __setup("apic=", apic_set_verbosity); | |
730 | ||
731 | static int __init detect_init_APIC (void) | |
732 | { | |
733 | u32 h, l, features; | |
1da177e4 LT |
734 | |
735 | /* Disabled by kernel option? */ | |
736 | if (enable_local_apic < 0) | |
737 | return -1; | |
738 | ||
1da177e4 LT |
739 | switch (boot_cpu_data.x86_vendor) { |
740 | case X86_VENDOR_AMD: | |
741 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
742 | (boot_cpu_data.x86 == 15)) | |
743 | break; | |
744 | goto no_apic; | |
745 | case X86_VENDOR_INTEL: | |
746 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
747 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
748 | break; | |
749 | goto no_apic; | |
750 | default: | |
751 | goto no_apic; | |
752 | } | |
753 | ||
754 | if (!cpu_has_apic) { | |
755 | /* | |
756 | * Over-ride BIOS and try to enable the local | |
757 | * APIC only if "lapic" specified. | |
758 | */ | |
759 | if (enable_local_apic <= 0) { | |
760 | printk("Local APIC disabled by BIOS -- " | |
761 | "you can enable it with \"lapic\"\n"); | |
762 | return -1; | |
763 | } | |
764 | /* | |
765 | * Some BIOSes disable the local APIC in the | |
766 | * APIC_BASE MSR. This can only be done in | |
767 | * software for Intel P6 or later and AMD K7 | |
768 | * (Model > 1) or later. | |
769 | */ | |
770 | rdmsr(MSR_IA32_APICBASE, l, h); | |
771 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
772 | printk("Local APIC disabled by BIOS -- reenabling.\n"); | |
773 | l &= ~MSR_IA32_APICBASE_BASE; | |
774 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
775 | wrmsr(MSR_IA32_APICBASE, l, h); | |
776 | enabled_via_apicbase = 1; | |
777 | } | |
778 | } | |
779 | /* | |
780 | * The APIC feature bit should now be enabled | |
781 | * in `cpuid' | |
782 | */ | |
783 | features = cpuid_edx(1); | |
784 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
785 | printk("Could not enable APIC!\n"); | |
786 | return -1; | |
787 | } | |
788 | set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
789 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
790 | ||
791 | /* The BIOS may have set up the APIC at some other address */ | |
792 | rdmsr(MSR_IA32_APICBASE, l, h); | |
793 | if (l & MSR_IA32_APICBASE_ENABLE) | |
794 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
795 | ||
796 | if (nmi_watchdog != NMI_NONE) | |
797 | nmi_watchdog = NMI_LOCAL_APIC; | |
798 | ||
799 | printk("Found and enabled local APIC!\n"); | |
800 | ||
801 | apic_pm_activate(); | |
802 | ||
803 | return 0; | |
804 | ||
805 | no_apic: | |
806 | printk("No local APIC present or hardware disabled\n"); | |
807 | return -1; | |
808 | } | |
809 | ||
810 | void __init init_apic_mappings(void) | |
811 | { | |
812 | unsigned long apic_phys; | |
813 | ||
814 | /* | |
815 | * If no local APIC can be found then set up a fake all | |
816 | * zeroes page to simulate the local APIC and another | |
817 | * one for the IO-APIC. | |
818 | */ | |
819 | if (!smp_found_config && detect_init_APIC()) { | |
820 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
821 | apic_phys = __pa(apic_phys); | |
822 | } else | |
823 | apic_phys = mp_lapic_addr; | |
824 | ||
825 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
826 | printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE, | |
827 | apic_phys); | |
828 | ||
829 | /* | |
830 | * Fetch the APIC ID of the BSP in case we have a | |
831 | * default configuration (or the MP table is broken). | |
832 | */ | |
1e4c85f9 LT |
833 | if (boot_cpu_physical_apicid == -1U) |
834 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 LT |
835 | |
836 | #ifdef CONFIG_X86_IO_APIC | |
837 | { | |
838 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
839 | int i; | |
840 | ||
841 | for (i = 0; i < nr_ioapics; i++) { | |
842 | if (smp_found_config) { | |
843 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
844 | if (!ioapic_phys) { | |
845 | printk(KERN_ERR | |
846 | "WARNING: bogus zero IO-APIC " | |
847 | "address found in MPTABLE, " | |
848 | "disabling IO/APIC support!\n"); | |
849 | smp_found_config = 0; | |
850 | skip_ioapic_setup = 1; | |
851 | goto fake_ioapic_page; | |
852 | } | |
853 | } else { | |
854 | fake_ioapic_page: | |
855 | ioapic_phys = (unsigned long) | |
856 | alloc_bootmem_pages(PAGE_SIZE); | |
857 | ioapic_phys = __pa(ioapic_phys); | |
858 | } | |
859 | set_fixmap_nocache(idx, ioapic_phys); | |
860 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
861 | __fix_to_virt(idx), ioapic_phys); | |
862 | idx++; | |
863 | } | |
864 | } | |
865 | #endif | |
866 | } | |
867 | ||
868 | /* | |
869 | * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts | |
870 | * per second. We assume that the caller has already set up the local | |
871 | * APIC. | |
872 | * | |
873 | * The APIC timer is not exactly sync with the external timer chip, it | |
874 | * closely follows bus clocks. | |
875 | */ | |
876 | ||
877 | /* | |
878 | * The timer chip is already set up at HZ interrupts per second here, | |
879 | * but we do not accept timer interrupts yet. We only allow the BP | |
880 | * to calibrate. | |
881 | */ | |
0bb3184d | 882 | static unsigned int __devinit get_8254_timer_count(void) |
1da177e4 | 883 | { |
1da177e4 LT |
884 | unsigned long flags; |
885 | ||
886 | unsigned int count; | |
887 | ||
888 | spin_lock_irqsave(&i8253_lock, flags); | |
889 | ||
890 | outb_p(0x00, PIT_MODE); | |
891 | count = inb_p(PIT_CH0); | |
892 | count |= inb_p(PIT_CH0) << 8; | |
893 | ||
894 | spin_unlock_irqrestore(&i8253_lock, flags); | |
895 | ||
896 | return count; | |
897 | } | |
898 | ||
899 | /* next tick in 8254 can be caught by catching timer wraparound */ | |
0bb3184d | 900 | static void __devinit wait_8254_wraparound(void) |
1da177e4 LT |
901 | { |
902 | unsigned int curr_count, prev_count; | |
903 | ||
904 | curr_count = get_8254_timer_count(); | |
905 | do { | |
906 | prev_count = curr_count; | |
907 | curr_count = get_8254_timer_count(); | |
908 | ||
909 | /* workaround for broken Mercury/Neptune */ | |
910 | if (prev_count >= curr_count + 0x100) | |
911 | curr_count = get_8254_timer_count(); | |
912 | ||
913 | } while (prev_count >= curr_count); | |
914 | } | |
915 | ||
916 | /* | |
917 | * Default initialization for 8254 timers. If we use other timers like HPET, | |
918 | * we override this later | |
919 | */ | |
0bb3184d | 920 | void (*wait_timer_tick)(void) __devinitdata = wait_8254_wraparound; |
1da177e4 LT |
921 | |
922 | /* | |
923 | * This function sets up the local APIC timer, with a timeout of | |
924 | * 'clocks' APIC bus clock. During calibration we actually call | |
925 | * this function twice on the boot CPU, once with a bogus timeout | |
926 | * value, second time for real. The other (noncalibrating) CPUs | |
927 | * call this function only once, with the real, calibrated value. | |
928 | * | |
929 | * We do reads before writes even if unnecessary, to get around the | |
930 | * P5 APIC double write bug. | |
931 | */ | |
932 | ||
933 | #define APIC_DIVISOR 16 | |
934 | ||
935 | static void __setup_APIC_LVTT(unsigned int clocks) | |
936 | { | |
937 | unsigned int lvtt_value, tmp_value, ver; | |
938 | ||
939 | ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
940 | lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; | |
941 | if (!APIC_INTEGRATED(ver)) | |
942 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
943 | apic_write_around(APIC_LVTT, lvtt_value); | |
944 | ||
945 | /* | |
946 | * Divide PICLK by 16 | |
947 | */ | |
948 | tmp_value = apic_read(APIC_TDCR); | |
949 | apic_write_around(APIC_TDCR, (tmp_value | |
950 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
951 | | APIC_TDR_DIV_16); | |
952 | ||
953 | apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); | |
954 | } | |
955 | ||
0bb3184d | 956 | static void __devinit setup_APIC_timer(unsigned int clocks) |
1da177e4 LT |
957 | { |
958 | unsigned long flags; | |
959 | ||
960 | local_irq_save(flags); | |
961 | ||
962 | /* | |
963 | * Wait for IRQ0's slice: | |
964 | */ | |
965 | wait_timer_tick(); | |
966 | ||
967 | __setup_APIC_LVTT(clocks); | |
968 | ||
969 | local_irq_restore(flags); | |
970 | } | |
971 | ||
972 | /* | |
973 | * In this function we calibrate APIC bus clocks to the external | |
974 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
975 | * to calibrate, since some later bootup code depends on getting | |
976 | * the first irq? Ugh. | |
977 | * | |
978 | * We want to do the calibration only once since we | |
979 | * want to have local timer irqs syncron. CPUs connected | |
980 | * by the same APIC bus have the very same bus frequency. | |
981 | * And we want to have irqs off anyways, no accidental | |
982 | * APIC irq that way. | |
983 | */ | |
984 | ||
985 | static int __init calibrate_APIC_clock(void) | |
986 | { | |
987 | unsigned long long t1 = 0, t2 = 0; | |
988 | long tt1, tt2; | |
989 | long result; | |
990 | int i; | |
991 | const int LOOPS = HZ/10; | |
992 | ||
993 | apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n"); | |
994 | ||
995 | /* | |
996 | * Put whatever arbitrary (but long enough) timeout | |
997 | * value into the APIC clock, we just want to get the | |
998 | * counter running for calibration. | |
999 | */ | |
1000 | __setup_APIC_LVTT(1000000000); | |
1001 | ||
1002 | /* | |
1003 | * The timer chip counts down to zero. Let's wait | |
1004 | * for a wraparound to start exact measurement: | |
1005 | * (the current tick might have been already half done) | |
1006 | */ | |
1007 | ||
1008 | wait_timer_tick(); | |
1009 | ||
1010 | /* | |
1011 | * We wrapped around just now. Let's start: | |
1012 | */ | |
1013 | if (cpu_has_tsc) | |
1014 | rdtscll(t1); | |
1015 | tt1 = apic_read(APIC_TMCCT); | |
1016 | ||
1017 | /* | |
1018 | * Let's wait LOOPS wraprounds: | |
1019 | */ | |
1020 | for (i = 0; i < LOOPS; i++) | |
1021 | wait_timer_tick(); | |
1022 | ||
1023 | tt2 = apic_read(APIC_TMCCT); | |
1024 | if (cpu_has_tsc) | |
1025 | rdtscll(t2); | |
1026 | ||
1027 | /* | |
1028 | * The APIC bus clock counter is 32 bits only, it | |
1029 | * might have overflown, but note that we use signed | |
1030 | * longs, thus no extra care needed. | |
1031 | * | |
1032 | * underflown to be exact, as the timer counts down ;) | |
1033 | */ | |
1034 | ||
1035 | result = (tt1-tt2)*APIC_DIVISOR/LOOPS; | |
1036 | ||
1037 | if (cpu_has_tsc) | |
1038 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " | |
1039 | "%ld.%04ld MHz.\n", | |
1040 | ((long)(t2-t1)/LOOPS)/(1000000/HZ), | |
1041 | ((long)(t2-t1)/LOOPS)%(1000000/HZ)); | |
1042 | ||
1043 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
1044 | "%ld.%04ld MHz.\n", | |
1045 | result/(1000000/HZ), | |
1046 | result%(1000000/HZ)); | |
1047 | ||
1048 | return result; | |
1049 | } | |
1050 | ||
1051 | static unsigned int calibration_result; | |
1052 | ||
1053 | void __init setup_boot_APIC_clock(void) | |
1054 | { | |
f2b36db6 | 1055 | unsigned long flags; |
1da177e4 LT |
1056 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"); |
1057 | using_apic_timer = 1; | |
1058 | ||
f2b36db6 | 1059 | local_irq_save(flags); |
1da177e4 LT |
1060 | |
1061 | calibration_result = calibrate_APIC_clock(); | |
1062 | /* | |
1063 | * Now set up the timer for real. | |
1064 | */ | |
1065 | setup_APIC_timer(calibration_result); | |
1066 | ||
f2b36db6 | 1067 | local_irq_restore(flags); |
1da177e4 LT |
1068 | } |
1069 | ||
0bb3184d | 1070 | void __devinit setup_secondary_APIC_clock(void) |
1da177e4 LT |
1071 | { |
1072 | setup_APIC_timer(calibration_result); | |
1073 | } | |
1074 | ||
f3705136 | 1075 | void __devinit disable_APIC_timer(void) |
1da177e4 LT |
1076 | { |
1077 | if (using_apic_timer) { | |
1078 | unsigned long v; | |
1079 | ||
1080 | v = apic_read(APIC_LVTT); | |
1081 | apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); | |
1082 | } | |
1083 | } | |
1084 | ||
1085 | void enable_APIC_timer(void) | |
1086 | { | |
1087 | if (using_apic_timer) { | |
1088 | unsigned long v; | |
1089 | ||
1090 | v = apic_read(APIC_LVTT); | |
1091 | apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED); | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | /* | |
1096 | * the frequency of the profiling timer can be changed | |
1097 | * by writing a multiplier value into /proc/profile. | |
1098 | */ | |
1099 | int setup_profiling_timer(unsigned int multiplier) | |
1100 | { | |
1101 | int i; | |
1102 | ||
1103 | /* | |
1104 | * Sanity check. [at least 500 APIC cycles should be | |
1105 | * between APIC interrupts as a rule of thumb, to avoid | |
1106 | * irqs flooding us] | |
1107 | */ | |
1108 | if ( (!multiplier) || (calibration_result/multiplier < 500)) | |
1109 | return -EINVAL; | |
1110 | ||
1111 | /* | |
1112 | * Set the new multiplier for each CPU. CPUs don't start using the | |
1113 | * new values until the next timer interrupt in which they do process | |
1114 | * accounting. At that time they also adjust their APIC timers | |
1115 | * accordingly. | |
1116 | */ | |
1117 | for (i = 0; i < NR_CPUS; ++i) | |
1118 | per_cpu(prof_multiplier, i) = multiplier; | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | #undef APIC_DIVISOR | |
1124 | ||
1125 | /* | |
1126 | * Local timer interrupt handler. It does both profiling and | |
1127 | * process statistics/rescheduling. | |
1128 | * | |
1129 | * We do profiling in every local tick, statistics/rescheduling | |
1130 | * happen only every 'profiling multiplier' ticks. The default | |
1131 | * multiplier is 1 and it can be changed by writing the new multiplier | |
1132 | * value into /proc/profile. | |
1133 | */ | |
1134 | ||
1135 | inline void smp_local_timer_interrupt(struct pt_regs * regs) | |
1136 | { | |
1137 | int cpu = smp_processor_id(); | |
1138 | ||
1139 | profile_tick(CPU_PROFILING, regs); | |
1140 | if (--per_cpu(prof_counter, cpu) <= 0) { | |
1141 | /* | |
1142 | * The multiplier may have changed since the last time we got | |
1143 | * to this point as a result of the user writing to | |
1144 | * /proc/profile. In this case we need to adjust the APIC | |
1145 | * timer accordingly. | |
1146 | * | |
1147 | * Interrupts are already masked off at this point. | |
1148 | */ | |
1149 | per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu); | |
1150 | if (per_cpu(prof_counter, cpu) != | |
1151 | per_cpu(prof_old_multiplier, cpu)) { | |
1152 | __setup_APIC_LVTT( | |
1153 | calibration_result/ | |
1154 | per_cpu(prof_counter, cpu)); | |
1155 | per_cpu(prof_old_multiplier, cpu) = | |
1156 | per_cpu(prof_counter, cpu); | |
1157 | } | |
1158 | ||
1159 | #ifdef CONFIG_SMP | |
fa1e1bdf | 1160 | update_process_times(user_mode_vm(regs)); |
1da177e4 LT |
1161 | #endif |
1162 | } | |
1163 | ||
1164 | /* | |
1165 | * We take the 'long' return path, and there every subsystem | |
1166 | * grabs the apropriate locks (kernel lock/ irq lock). | |
1167 | * | |
1168 | * we might want to decouple profiling from the 'long path', | |
1169 | * and do the profiling totally in assembly. | |
1170 | * | |
1171 | * Currently this isn't too much of an issue (performance wise), | |
1172 | * we can take more than 100K local irqs per second on a 100 MHz P5. | |
1173 | */ | |
1174 | } | |
1175 | ||
1176 | /* | |
1177 | * Local APIC timer interrupt. This is the most natural way for doing | |
1178 | * local interrupts, but local timer interrupts can be emulated by | |
1179 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
1180 | * | |
1181 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
1182 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
1183 | */ | |
1184 | ||
1185 | fastcall void smp_apic_timer_interrupt(struct pt_regs *regs) | |
1186 | { | |
1187 | int cpu = smp_processor_id(); | |
1188 | ||
1189 | /* | |
1190 | * the NMI deadlock-detector uses this. | |
1191 | */ | |
1192 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
1193 | ||
1194 | /* | |
1195 | * NOTE! We'd better ACK the irq immediately, | |
1196 | * because timer handling can be slow. | |
1197 | */ | |
1198 | ack_APIC_irq(); | |
1199 | /* | |
1200 | * update_process_times() expects us to have done irq_enter(). | |
1201 | * Besides, if we don't timer interrupts ignore the global | |
1202 | * interrupt lock, which is the WrongThing (tm) to do. | |
1203 | */ | |
1204 | irq_enter(); | |
1205 | smp_local_timer_interrupt(regs); | |
1206 | irq_exit(); | |
1207 | } | |
1208 | ||
1209 | /* | |
1210 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1211 | */ | |
1212 | fastcall void smp_spurious_interrupt(struct pt_regs *regs) | |
1213 | { | |
1214 | unsigned long v; | |
1215 | ||
1216 | irq_enter(); | |
1217 | /* | |
1218 | * Check if this really is a spurious interrupt and ACK it | |
1219 | * if it is a vectored one. Just in case... | |
1220 | * Spurious interrupts should not be ACKed. | |
1221 | */ | |
1222 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); | |
1223 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1224 | ack_APIC_irq(); | |
1225 | ||
1226 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
1227 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n", | |
1228 | smp_processor_id()); | |
1229 | irq_exit(); | |
1230 | } | |
1231 | ||
1232 | /* | |
1233 | * This interrupt should never happen with our APIC/SMP architecture | |
1234 | */ | |
1235 | ||
1236 | fastcall void smp_error_interrupt(struct pt_regs *regs) | |
1237 | { | |
1238 | unsigned long v, v1; | |
1239 | ||
1240 | irq_enter(); | |
1241 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1242 | v = apic_read(APIC_ESR); | |
1243 | apic_write(APIC_ESR, 0); | |
1244 | v1 = apic_read(APIC_ESR); | |
1245 | ack_APIC_irq(); | |
1246 | atomic_inc(&irq_err_count); | |
1247 | ||
1248 | /* Here is what the APIC error bits mean: | |
1249 | 0: Send CS error | |
1250 | 1: Receive CS error | |
1251 | 2: Send accept error | |
1252 | 3: Receive accept error | |
1253 | 4: Reserved | |
1254 | 5: Send illegal vector | |
1255 | 6: Received illegal vector | |
1256 | 7: Illegal register address | |
1257 | */ | |
1258 | printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n", | |
1259 | smp_processor_id(), v , v1); | |
1260 | irq_exit(); | |
1261 | } | |
1262 | ||
1263 | /* | |
1e4c85f9 LT |
1264 | * This initializes the IO-APIC and APIC hardware if this is |
1265 | * a UP kernel. | |
1da177e4 | 1266 | */ |
1e4c85f9 | 1267 | int __init APIC_init_uniprocessor (void) |
1da177e4 | 1268 | { |
1e4c85f9 LT |
1269 | if (enable_local_apic < 0) |
1270 | clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); | |
1da177e4 | 1271 | |
1e4c85f9 | 1272 | if (!smp_found_config && !cpu_has_apic) |
1da177e4 LT |
1273 | return -1; |
1274 | ||
1275 | /* | |
1e4c85f9 | 1276 | * Complain if the BIOS pretends there is one. |
1da177e4 LT |
1277 | */ |
1278 | if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1279 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1280 | boot_cpu_physical_apicid); | |
1281 | return -1; | |
1282 | } | |
1283 | ||
1284 | verify_local_APIC(); | |
1285 | ||
1286 | connect_bsp_APIC(); | |
1287 | ||
1e4c85f9 | 1288 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); |
1da177e4 | 1289 | |
1e4c85f9 | 1290 | setup_local_APIC(); |
1da177e4 | 1291 | |
1da177e4 | 1292 | #ifdef CONFIG_X86_IO_APIC |
1e4c85f9 LT |
1293 | if (smp_found_config) |
1294 | if (!skip_ioapic_setup && nr_ioapics) | |
1295 | setup_IO_APIC(); | |
1da177e4 LT |
1296 | #endif |
1297 | setup_boot_APIC_clock(); | |
1e4c85f9 LT |
1298 | |
1299 | return 0; | |
1da177e4 | 1300 | } |