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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/string.h> | |
3 | #include <linux/delay.h> | |
4 | #include <linux/smp.h> | |
5 | #include <linux/module.h> | |
6 | #include <linux/percpu.h> | |
2b932f6c | 7 | #include <linux/bootmem.h> |
1da177e4 LT |
8 | #include <asm/semaphore.h> |
9 | #include <asm/processor.h> | |
10 | #include <asm/i387.h> | |
11 | #include <asm/msr.h> | |
12 | #include <asm/io.h> | |
13 | #include <asm/mmu_context.h> | |
27b07da7 | 14 | #include <asm/mtrr.h> |
a03a3e28 | 15 | #include <asm/mce.h> |
1da177e4 LT |
16 | #ifdef CONFIG_X86_LOCAL_APIC |
17 | #include <asm/mpspec.h> | |
18 | #include <asm/apic.h> | |
19 | #include <mach_apic.h> | |
20 | #endif | |
62111195 | 21 | #include <asm/pda.h> |
1da177e4 LT |
22 | |
23 | #include "cpu.h" | |
24 | ||
bf504672 RR |
25 | DEFINE_PER_CPU(struct desc_struct, cpu_gdt[GDT_ENTRIES]) = { |
26 | [GDT_ENTRY_KERNEL_CS] = { 0x0000ffff, 0x00cf9a00 }, | |
27 | [GDT_ENTRY_KERNEL_DS] = { 0x0000ffff, 0x00cf9200 }, | |
28 | [GDT_ENTRY_DEFAULT_USER_CS] = { 0x0000ffff, 0x00cffa00 }, | |
29 | [GDT_ENTRY_DEFAULT_USER_DS] = { 0x0000ffff, 0x00cff200 }, | |
30 | /* | |
31 | * Segments used for calling PnP BIOS have byte granularity. | |
32 | * They code segments and data segments have fixed 64k limits, | |
33 | * the transfer segment sizes are set at run time. | |
34 | */ | |
35 | [GDT_ENTRY_PNPBIOS_CS32] = { 0x0000ffff, 0x00409a00 },/* 32-bit code */ | |
36 | [GDT_ENTRY_PNPBIOS_CS16] = { 0x0000ffff, 0x00009a00 },/* 16-bit code */ | |
37 | [GDT_ENTRY_PNPBIOS_DS] = { 0x0000ffff, 0x00009200 }, /* 16-bit data */ | |
38 | [GDT_ENTRY_PNPBIOS_TS1] = { 0x00000000, 0x00009200 },/* 16-bit data */ | |
39 | [GDT_ENTRY_PNPBIOS_TS2] = { 0x00000000, 0x00009200 },/* 16-bit data */ | |
40 | /* | |
41 | * The APM segments have byte granularity and their bases | |
42 | * are set at run time. All have 64k limits. | |
43 | */ | |
44 | [GDT_ENTRY_APMBIOS_BASE] = { 0x0000ffff, 0x00409a00 },/* 32-bit code */ | |
45 | /* 16-bit code */ | |
46 | [GDT_ENTRY_APMBIOS_BASE+1] = { 0x0000ffff, 0x00009a00 }, | |
47 | [GDT_ENTRY_APMBIOS_BASE+2] = { 0x0000ffff, 0x00409200 }, /* data */ | |
48 | ||
49 | [GDT_ENTRY_ESPFIX_SS] = { 0x00000000, 0x00c09200 }, | |
50 | [GDT_ENTRY_PDA] = { 0x00000000, 0x00c09200 }, /* set in setup_pda */ | |
51 | }; | |
4fbb5968 | 52 | EXPORT_PER_CPU_SYMBOL_GPL(cpu_gdt); |
ae1ee11b RR |
53 | |
54 | DEFINE_PER_CPU(struct i386_pda, _cpu_pda); | |
55 | EXPORT_PER_CPU_SYMBOL(_cpu_pda); | |
62111195 | 56 | |
3bc9b76b | 57 | static int cachesize_override __cpuinitdata = -1; |
4f886511 | 58 | static int disable_x86_fxsr __cpuinitdata; |
3bc9b76b | 59 | static int disable_x86_serial_nr __cpuinitdata = 1; |
4f886511 | 60 | static int disable_x86_sep __cpuinitdata; |
1da177e4 LT |
61 | |
62 | struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {}; | |
63 | ||
1da177e4 LT |
64 | extern int disable_pse; |
65 | ||
b4af3f7c | 66 | static void __cpuinit default_init(struct cpuinfo_x86 * c) |
1da177e4 LT |
67 | { |
68 | /* Not much we can do here... */ | |
69 | /* Check if at least it has cpuid */ | |
70 | if (c->cpuid_level == -1) { | |
71 | /* No cpuid. It must be an ancient CPU */ | |
72 | if (c->x86 == 4) | |
73 | strcpy(c->x86_model_id, "486"); | |
74 | else if (c->x86 == 3) | |
75 | strcpy(c->x86_model_id, "386"); | |
76 | } | |
77 | } | |
78 | ||
95414930 | 79 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 80 | .c_init = default_init, |
fe38d855 | 81 | .c_vendor = "Unknown", |
1da177e4 | 82 | }; |
9dbeeec9 | 83 | static struct cpu_dev * this_cpu __cpuinitdata = &default_cpu; |
1da177e4 LT |
84 | |
85 | static int __init cachesize_setup(char *str) | |
86 | { | |
87 | get_option (&str, &cachesize_override); | |
88 | return 1; | |
89 | } | |
90 | __setup("cachesize=", cachesize_setup); | |
91 | ||
3bc9b76b | 92 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
93 | { |
94 | unsigned int *v; | |
95 | char *p, *q; | |
96 | ||
97 | if (cpuid_eax(0x80000000) < 0x80000004) | |
98 | return 0; | |
99 | ||
100 | v = (unsigned int *) c->x86_model_id; | |
101 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
102 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
103 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
104 | c->x86_model_id[48] = 0; | |
105 | ||
106 | /* Intel chips right-justify this string for some dumb reason; | |
107 | undo that brain damage */ | |
108 | p = q = &c->x86_model_id[0]; | |
109 | while ( *p == ' ' ) | |
110 | p++; | |
111 | if ( p != q ) { | |
112 | while ( *p ) | |
113 | *q++ = *p++; | |
114 | while ( q <= &c->x86_model_id[48] ) | |
115 | *q++ = '\0'; /* Zero-pad the rest */ | |
116 | } | |
117 | ||
118 | return 1; | |
119 | } | |
120 | ||
121 | ||
3bc9b76b | 122 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 LT |
123 | { |
124 | unsigned int n, dummy, ecx, edx, l2size; | |
125 | ||
126 | n = cpuid_eax(0x80000000); | |
127 | ||
128 | if (n >= 0x80000005) { | |
129 | cpuid(0x80000005, &dummy, &dummy, &ecx, &edx); | |
130 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", | |
131 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); | |
132 | c->x86_cache_size=(ecx>>24)+(edx>>24); | |
133 | } | |
134 | ||
135 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
136 | return; | |
137 | ||
138 | ecx = cpuid_ecx(0x80000006); | |
139 | l2size = ecx >> 16; | |
140 | ||
141 | /* do processor-specific cache resizing */ | |
142 | if (this_cpu->c_size_cache) | |
143 | l2size = this_cpu->c_size_cache(c,l2size); | |
144 | ||
145 | /* Allow user to override all this if necessary. */ | |
146 | if (cachesize_override != -1) | |
147 | l2size = cachesize_override; | |
148 | ||
149 | if ( l2size == 0 ) | |
150 | return; /* Again, no L2 cache is possible */ | |
151 | ||
152 | c->x86_cache_size = l2size; | |
153 | ||
154 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
155 | l2size, ecx & 0xFF); | |
156 | } | |
157 | ||
158 | /* Naming convention should be: <Name> [(<Codename>)] */ | |
159 | /* This table only is used unless init_<vendor>() below doesn't set it; */ | |
160 | /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */ | |
161 | ||
162 | /* Look up CPU names by table lookup. */ | |
3bc9b76b | 163 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) |
1da177e4 LT |
164 | { |
165 | struct cpu_model_info *info; | |
166 | ||
167 | if ( c->x86_model >= 16 ) | |
168 | return NULL; /* Range check */ | |
169 | ||
170 | if (!this_cpu) | |
171 | return NULL; | |
172 | ||
173 | info = this_cpu->c_models; | |
174 | ||
175 | while (info && info->family) { | |
176 | if (info->family == c->x86) | |
177 | return info->model_names[c->x86_model]; | |
178 | info++; | |
179 | } | |
180 | return NULL; /* Not found */ | |
181 | } | |
182 | ||
183 | ||
3bc9b76b | 184 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early) |
1da177e4 LT |
185 | { |
186 | char *v = c->x86_vendor_id; | |
187 | int i; | |
fe38d855 | 188 | static int printed; |
1da177e4 LT |
189 | |
190 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
191 | if (cpu_devs[i]) { | |
192 | if (!strcmp(v,cpu_devs[i]->c_ident[0]) || | |
193 | (cpu_devs[i]->c_ident[1] && | |
194 | !strcmp(v,cpu_devs[i]->c_ident[1]))) { | |
195 | c->x86_vendor = i; | |
196 | if (!early) | |
197 | this_cpu = cpu_devs[i]; | |
fe38d855 | 198 | return; |
1da177e4 LT |
199 | } |
200 | } | |
201 | } | |
fe38d855 CE |
202 | if (!printed) { |
203 | printed++; | |
204 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
205 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
206 | } | |
207 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
208 | this_cpu = &default_cpu; | |
1da177e4 LT |
209 | } |
210 | ||
211 | ||
212 | static int __init x86_fxsr_setup(char * s) | |
213 | { | |
8ccb3dcd | 214 | /* Tell all the other CPU's to not use it... */ |
1da177e4 | 215 | disable_x86_fxsr = 1; |
8ccb3dcd LT |
216 | |
217 | /* | |
218 | * ... and clear the bits early in the boot_cpu_data | |
219 | * so that the bootup process doesn't try to do this | |
220 | * either. | |
221 | */ | |
222 | clear_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability); | |
223 | clear_bit(X86_FEATURE_XMM, boot_cpu_data.x86_capability); | |
1da177e4 LT |
224 | return 1; |
225 | } | |
226 | __setup("nofxsr", x86_fxsr_setup); | |
227 | ||
228 | ||
4f886511 CE |
229 | static int __init x86_sep_setup(char * s) |
230 | { | |
231 | disable_x86_sep = 1; | |
232 | return 1; | |
233 | } | |
234 | __setup("nosep", x86_sep_setup); | |
235 | ||
236 | ||
1da177e4 LT |
237 | /* Standard macro to see if a specific flag is changeable */ |
238 | static inline int flag_is_changeable_p(u32 flag) | |
239 | { | |
240 | u32 f1, f2; | |
241 | ||
242 | asm("pushfl\n\t" | |
243 | "pushfl\n\t" | |
244 | "popl %0\n\t" | |
245 | "movl %0,%1\n\t" | |
246 | "xorl %2,%0\n\t" | |
247 | "pushl %0\n\t" | |
248 | "popfl\n\t" | |
249 | "pushfl\n\t" | |
250 | "popl %0\n\t" | |
251 | "popfl\n\t" | |
252 | : "=&r" (f1), "=&r" (f2) | |
253 | : "ir" (flag)); | |
254 | ||
255 | return ((f1^f2) & flag) != 0; | |
256 | } | |
257 | ||
258 | ||
259 | /* Probe for the CPUID instruction */ | |
3bc9b76b | 260 | static int __cpuinit have_cpuid_p(void) |
1da177e4 LT |
261 | { |
262 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
263 | } | |
264 | ||
d7cd5611 | 265 | void __init cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 266 | { |
1da177e4 LT |
267 | /* Get vendor name */ |
268 | cpuid(0x00000000, &c->cpuid_level, | |
269 | (int *)&c->x86_vendor_id[0], | |
270 | (int *)&c->x86_vendor_id[8], | |
271 | (int *)&c->x86_vendor_id[4]); | |
272 | ||
1da177e4 LT |
273 | c->x86 = 4; |
274 | if (c->cpuid_level >= 0x00000001) { | |
275 | u32 junk, tfms, cap0, misc; | |
276 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
277 | c->x86 = (tfms >> 8) & 15; | |
278 | c->x86_model = (tfms >> 4) & 15; | |
f5f786d0 | 279 | if (c->x86 == 0xf) |
1da177e4 | 280 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 281 | if (c->x86 >= 0x6) |
1da177e4 | 282 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 LT |
283 | c->x86_mask = tfms & 15; |
284 | if (cap0 & (1<<19)) | |
285 | c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8; | |
286 | } | |
1da177e4 LT |
287 | } |
288 | ||
d7cd5611 RR |
289 | /* Do minimum CPU detection early. |
290 | Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment. | |
291 | The others are not touched to avoid unwanted side effects. | |
292 | ||
293 | WARNING: this function is only called on the BP. Don't add code here | |
294 | that is supposed to run on all CPUs. */ | |
295 | static void __init early_cpu_detect(void) | |
296 | { | |
297 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
298 | ||
299 | c->x86_cache_alignment = 32; | |
300 | ||
301 | if (!have_cpuid_p()) | |
302 | return; | |
303 | ||
304 | cpu_detect(c); | |
305 | ||
306 | get_cpu_vendor(c, 1); | |
307 | } | |
308 | ||
68bbc172 | 309 | static void __cpuinit generic_identify(struct cpuinfo_x86 * c) |
1da177e4 LT |
310 | { |
311 | u32 tfms, xlvl; | |
1e9f28fa | 312 | int ebx; |
1da177e4 LT |
313 | |
314 | if (have_cpuid_p()) { | |
315 | /* Get vendor name */ | |
316 | cpuid(0x00000000, &c->cpuid_level, | |
317 | (int *)&c->x86_vendor_id[0], | |
318 | (int *)&c->x86_vendor_id[8], | |
319 | (int *)&c->x86_vendor_id[4]); | |
320 | ||
321 | get_cpu_vendor(c, 0); | |
322 | /* Initialize the standard set of capabilities */ | |
323 | /* Note that the vendor-specific code below might override */ | |
324 | ||
325 | /* Intel-defined flags: level 0x00000001 */ | |
326 | if ( c->cpuid_level >= 0x00000001 ) { | |
327 | u32 capability, excap; | |
1e9f28fa | 328 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
1da177e4 LT |
329 | c->x86_capability[0] = capability; |
330 | c->x86_capability[4] = excap; | |
331 | c->x86 = (tfms >> 8) & 15; | |
332 | c->x86_model = (tfms >> 4) & 15; | |
ed2da193 | 333 | if (c->x86 == 0xf) |
1da177e4 | 334 | c->x86 += (tfms >> 20) & 0xff; |
ed2da193 | 335 | if (c->x86 >= 0x6) |
1da177e4 | 336 | c->x86_model += ((tfms >> 16) & 0xF) << 4; |
1da177e4 | 337 | c->x86_mask = tfms & 15; |
96c52749 | 338 | #ifdef CONFIG_X86_HT |
1e9f28fa SS |
339 | c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0); |
340 | #else | |
341 | c->apicid = (ebx >> 24) & 0xFF; | |
342 | #endif | |
770d132f AK |
343 | if (c->x86_capability[0] & (1<<19)) |
344 | c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8; | |
1da177e4 LT |
345 | } else { |
346 | /* Have CPUID level 0 only - unheard of */ | |
347 | c->x86 = 4; | |
348 | } | |
349 | ||
350 | /* AMD-defined flags: level 0x80000001 */ | |
351 | xlvl = cpuid_eax(0x80000000); | |
352 | if ( (xlvl & 0xffff0000) == 0x80000000 ) { | |
353 | if ( xlvl >= 0x80000001 ) { | |
354 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
355 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
356 | } | |
357 | if ( xlvl >= 0x80000004 ) | |
358 | get_model_name(c); /* Default name */ | |
359 | } | |
360 | } | |
2e664aa2 AK |
361 | |
362 | early_intel_workaround(c); | |
363 | ||
364 | #ifdef CONFIG_X86_HT | |
4b89aff9 | 365 | c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff; |
2e664aa2 | 366 | #endif |
1da177e4 LT |
367 | } |
368 | ||
3bc9b76b | 369 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
1da177e4 LT |
370 | { |
371 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) { | |
372 | /* Disable processor serial number */ | |
373 | unsigned long lo,hi; | |
374 | rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
375 | lo |= 0x200000; | |
376 | wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi); | |
377 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
378 | clear_bit(X86_FEATURE_PN, c->x86_capability); | |
379 | ||
380 | /* Disabling the serial number may affect the cpuid level */ | |
381 | c->cpuid_level = cpuid_eax(0); | |
382 | } | |
383 | } | |
384 | ||
385 | static int __init x86_serial_nr_setup(char *s) | |
386 | { | |
387 | disable_x86_serial_nr = 0; | |
388 | return 1; | |
389 | } | |
390 | __setup("serialnumber", x86_serial_nr_setup); | |
391 | ||
392 | ||
393 | ||
394 | /* | |
395 | * This does the hard work of actually picking apart the CPU stuff... | |
396 | */ | |
a6c4e076 | 397 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
398 | { |
399 | int i; | |
400 | ||
401 | c->loops_per_jiffy = loops_per_jiffy; | |
402 | c->x86_cache_size = -1; | |
403 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
404 | c->cpuid_level = -1; /* CPUID not detected */ | |
405 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
406 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
407 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 408 | c->x86_max_cores = 1; |
770d132f | 409 | c->x86_clflush_size = 32; |
1da177e4 LT |
410 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
411 | ||
412 | if (!have_cpuid_p()) { | |
413 | /* First of all, decide if this is a 486 or higher */ | |
414 | /* It's a 486 if we can modify the AC flag */ | |
415 | if ( flag_is_changeable_p(X86_EFLAGS_AC) ) | |
416 | c->x86 = 4; | |
417 | else | |
418 | c->x86 = 3; | |
419 | } | |
420 | ||
421 | generic_identify(c); | |
422 | ||
423 | printk(KERN_DEBUG "CPU: After generic identify, caps:"); | |
424 | for (i = 0; i < NCAPINTS; i++) | |
425 | printk(" %08lx", c->x86_capability[i]); | |
426 | printk("\n"); | |
427 | ||
428 | if (this_cpu->c_identify) { | |
429 | this_cpu->c_identify(c); | |
430 | ||
431 | printk(KERN_DEBUG "CPU: After vendor identify, caps:"); | |
432 | for (i = 0; i < NCAPINTS; i++) | |
433 | printk(" %08lx", c->x86_capability[i]); | |
434 | printk("\n"); | |
435 | } | |
436 | ||
437 | /* | |
438 | * Vendor-specific initialization. In this section we | |
439 | * canonicalize the feature flags, meaning if there are | |
440 | * features a certain CPU supports which CPUID doesn't | |
441 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
442 | * we handle them here. | |
443 | * | |
444 | * At the end of this section, c->x86_capability better | |
445 | * indicate the features this CPU genuinely supports! | |
446 | */ | |
447 | if (this_cpu->c_init) | |
448 | this_cpu->c_init(c); | |
449 | ||
450 | /* Disable the PN if appropriate */ | |
451 | squash_the_stupid_serial_number(c); | |
452 | ||
453 | /* | |
454 | * The vendor-specific functions might have changed features. Now | |
455 | * we do "generic changes." | |
456 | */ | |
457 | ||
458 | /* TSC disabled? */ | |
459 | if ( tsc_disable ) | |
460 | clear_bit(X86_FEATURE_TSC, c->x86_capability); | |
461 | ||
462 | /* FXSR disabled? */ | |
463 | if (disable_x86_fxsr) { | |
464 | clear_bit(X86_FEATURE_FXSR, c->x86_capability); | |
465 | clear_bit(X86_FEATURE_XMM, c->x86_capability); | |
466 | } | |
467 | ||
4f886511 CE |
468 | /* SEP disabled? */ |
469 | if (disable_x86_sep) | |
470 | clear_bit(X86_FEATURE_SEP, c->x86_capability); | |
471 | ||
1da177e4 LT |
472 | if (disable_pse) |
473 | clear_bit(X86_FEATURE_PSE, c->x86_capability); | |
474 | ||
475 | /* If the model name is still unset, do table lookup. */ | |
476 | if ( !c->x86_model_id[0] ) { | |
477 | char *p; | |
478 | p = table_lookup_model(c); | |
479 | if ( p ) | |
480 | strcpy(c->x86_model_id, p); | |
481 | else | |
482 | /* Last resort... */ | |
483 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 484 | c->x86, c->x86_model); |
1da177e4 LT |
485 | } |
486 | ||
487 | /* Now the feature flags better reflect actual CPU features! */ | |
488 | ||
489 | printk(KERN_DEBUG "CPU: After all inits, caps:"); | |
490 | for (i = 0; i < NCAPINTS; i++) | |
491 | printk(" %08lx", c->x86_capability[i]); | |
492 | printk("\n"); | |
493 | ||
494 | /* | |
495 | * On SMP, boot_cpu_data holds the common feature set between | |
496 | * all CPUs; so make sure that we indicate which features are | |
497 | * common between the CPUs. The first time this routine gets | |
498 | * executed, c == &boot_cpu_data. | |
499 | */ | |
500 | if ( c != &boot_cpu_data ) { | |
501 | /* AND the already accumulated flags with these */ | |
502 | for ( i = 0 ; i < NCAPINTS ; i++ ) | |
503 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; | |
504 | } | |
505 | ||
506 | /* Init Machine Check Exception if available. */ | |
1da177e4 | 507 | mcheck_init(c); |
a6c4e076 | 508 | } |
31ab269a | 509 | |
a6c4e076 JF |
510 | void __init identify_boot_cpu(void) |
511 | { | |
512 | identify_cpu(&boot_cpu_data); | |
513 | sysenter_setup(); | |
6fe940d6 | 514 | enable_sep_cpu(); |
a6c4e076 JF |
515 | mtrr_bp_init(); |
516 | } | |
3b520b23 | 517 | |
a6c4e076 JF |
518 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
519 | { | |
520 | BUG_ON(c == &boot_cpu_data); | |
521 | identify_cpu(c); | |
522 | enable_sep_cpu(); | |
523 | mtrr_ap_init(); | |
1da177e4 LT |
524 | } |
525 | ||
526 | #ifdef CONFIG_X86_HT | |
3bc9b76b | 527 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 LT |
528 | { |
529 | u32 eax, ebx, ecx, edx; | |
94605eff | 530 | int index_msb, core_bits; |
1da177e4 | 531 | |
94605eff SS |
532 | cpuid(1, &eax, &ebx, &ecx, &edx); |
533 | ||
63518644 | 534 | if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
1da177e4 LT |
535 | return; |
536 | ||
1da177e4 LT |
537 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
538 | ||
539 | if (smp_num_siblings == 1) { | |
540 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
541 | } else if (smp_num_siblings > 1 ) { | |
1da177e4 LT |
542 | |
543 | if (smp_num_siblings > NR_CPUS) { | |
4b89aff9 RS |
544 | printk(KERN_WARNING "CPU: Unsupported number of the " |
545 | "siblings %d", smp_num_siblings); | |
1da177e4 LT |
546 | smp_num_siblings = 1; |
547 | return; | |
548 | } | |
94605eff SS |
549 | |
550 | index_msb = get_count_order(smp_num_siblings); | |
4b89aff9 | 551 | c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb); |
1da177e4 LT |
552 | |
553 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
4b89aff9 | 554 | c->phys_proc_id); |
3dd9d514 | 555 | |
94605eff | 556 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
3dd9d514 | 557 | |
94605eff | 558 | index_msb = get_count_order(smp_num_siblings) ; |
3dd9d514 | 559 | |
94605eff | 560 | core_bits = get_count_order(c->x86_max_cores); |
3dd9d514 | 561 | |
4b89aff9 | 562 | c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) & |
94605eff | 563 | ((1 << core_bits) - 1); |
3dd9d514 | 564 | |
94605eff | 565 | if (c->x86_max_cores > 1) |
3dd9d514 | 566 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", |
4b89aff9 | 567 | c->cpu_core_id); |
1da177e4 LT |
568 | } |
569 | } | |
570 | #endif | |
571 | ||
3bc9b76b | 572 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
573 | { |
574 | char *vendor = NULL; | |
575 | ||
576 | if (c->x86_vendor < X86_VENDOR_NUM) | |
577 | vendor = this_cpu->c_vendor; | |
578 | else if (c->cpuid_level >= 0) | |
579 | vendor = c->x86_vendor_id; | |
580 | ||
581 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
582 | printk("%s ", vendor); | |
583 | ||
584 | if (!c->x86_model_id[0]) | |
585 | printk("%d86", c->x86); | |
586 | else | |
587 | printk("%s", c->x86_model_id); | |
588 | ||
589 | if (c->x86_mask || c->cpuid_level >= 0) | |
590 | printk(" stepping %02x\n", c->x86_mask); | |
591 | else | |
592 | printk("\n"); | |
593 | } | |
594 | ||
3bc9b76b | 595 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 LT |
596 | |
597 | /* This is hacky. :) | |
598 | * We're emulating future behavior. | |
599 | * In the future, the cpu-specific init functions will be called implicitly | |
600 | * via the magic of initcalls. | |
601 | * They will insert themselves into the cpu_devs structure. | |
602 | * Then, when cpu_init() is called, we can just iterate over that array. | |
603 | */ | |
604 | ||
605 | extern int intel_cpu_init(void); | |
606 | extern int cyrix_init_cpu(void); | |
607 | extern int nsc_init_cpu(void); | |
608 | extern int amd_init_cpu(void); | |
609 | extern int centaur_init_cpu(void); | |
610 | extern int transmeta_init_cpu(void); | |
611 | extern int rise_init_cpu(void); | |
612 | extern int nexgen_init_cpu(void); | |
613 | extern int umc_init_cpu(void); | |
614 | ||
615 | void __init early_cpu_init(void) | |
616 | { | |
617 | intel_cpu_init(); | |
618 | cyrix_init_cpu(); | |
619 | nsc_init_cpu(); | |
620 | amd_init_cpu(); | |
621 | centaur_init_cpu(); | |
622 | transmeta_init_cpu(); | |
623 | rise_init_cpu(); | |
624 | nexgen_init_cpu(); | |
625 | umc_init_cpu(); | |
626 | early_cpu_detect(); | |
627 | ||
628 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
629 | /* pse is not compatible with on-the-fly unmapping, | |
630 | * disable it even if the cpus claim to support it. | |
631 | */ | |
632 | clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability); | |
633 | disable_pse = 1; | |
634 | #endif | |
635 | } | |
62111195 | 636 | |
f95d47ca JF |
637 | /* Make sure %gs is initialized properly in idle threads */ |
638 | struct pt_regs * __devinit idle_regs(struct pt_regs *regs) | |
639 | { | |
640 | memset(regs, 0, sizeof(struct pt_regs)); | |
464d1a78 | 641 | regs->xfs = __KERNEL_PDA; |
f95d47ca JF |
642 | return regs; |
643 | } | |
644 | ||
62111195 JF |
645 | /* Initial PDA used by boot CPU */ |
646 | struct i386_pda boot_pda = { | |
647 | ._pda = &boot_pda, | |
b2938f88 | 648 | .cpu_number = 0, |
ec7fcaab | 649 | .pcurrent = &init_task, |
62111195 JF |
650 | }; |
651 | ||
d2cbcc49 RR |
652 | /* |
653 | * cpu_init() initializes state that is per-CPU. Some data is already | |
654 | * initialized (naturally) in the bootstrap process, such as the GDT | |
655 | * and IDT. We reload them nevertheless, this function acts as a | |
656 | * 'CPU state barrier', nothing should get across. | |
657 | */ | |
658 | void __cpuinit cpu_init(void) | |
9ee79a3d | 659 | { |
d2cbcc49 RR |
660 | int cpu = smp_processor_id(); |
661 | struct task_struct *curr = current; | |
9ee79a3d JB |
662 | struct tss_struct * t = &per_cpu(init_tss, cpu); |
663 | struct thread_struct *thread = &curr->thread; | |
62111195 JF |
664 | |
665 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
666 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
667 | for (;;) local_irq_enable(); | |
668 | } | |
669 | ||
670 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
671 | ||
672 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
673 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
674 | if (tsc_disable && cpu_has_tsc) { | |
675 | printk(KERN_NOTICE "Disabling TSC...\n"); | |
676 | /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/ | |
677 | clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability); | |
678 | set_in_cr4(X86_CR4_TSD); | |
679 | } | |
680 | ||
4d37e7e3 | 681 | load_idt(&idt_descr); |
1da177e4 | 682 | |
1da177e4 LT |
683 | /* |
684 | * Set up and load the per-CPU TSS and LDT | |
685 | */ | |
686 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
687 | curr->active_mm = &init_mm; |
688 | if (curr->mm) | |
689 | BUG(); | |
690 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 LT |
691 | |
692 | load_esp0(t, thread); | |
693 | set_tss_desc(cpu,t); | |
694 | load_TR_desc(); | |
695 | load_LDT(&init_mm.context); | |
696 | ||
22c4e308 | 697 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
698 | /* Set up doublefault TSS pointer in the GDT */ |
699 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 700 | #endif |
1da177e4 | 701 | |
464d1a78 JF |
702 | /* Clear %gs. */ |
703 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
704 | |
705 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
706 | set_debugreg(0, 0); |
707 | set_debugreg(0, 1); | |
708 | set_debugreg(0, 2); | |
709 | set_debugreg(0, 3); | |
710 | set_debugreg(0, 6); | |
711 | set_debugreg(0, 7); | |
1da177e4 LT |
712 | |
713 | /* | |
714 | * Force FPU initialization: | |
715 | */ | |
716 | current_thread_info()->status = 0; | |
717 | clear_used_math(); | |
718 | mxcsr_feature_mask_init(); | |
719 | } | |
e1367daf LS |
720 | |
721 | #ifdef CONFIG_HOTPLUG_CPU | |
3bc9b76b | 722 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
723 | { |
724 | int cpu = raw_smp_processor_id(); | |
725 | cpu_clear(cpu, cpu_initialized); | |
726 | ||
727 | /* lazy TLB state */ | |
728 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
729 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
730 | } | |
731 | #endif |